CN102263020A - Manufacture method of power semiconductor structure with low grid impedance - Google Patents
Manufacture method of power semiconductor structure with low grid impedance Download PDFInfo
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- CN102263020A CN102263020A CN2010101867627A CN201010186762A CN102263020A CN 102263020 A CN102263020 A CN 102263020A CN 2010101867627 A CN2010101867627 A CN 2010101867627A CN 201010186762 A CN201010186762 A CN 201010186762A CN 102263020 A CN102263020 A CN 102263020A
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Abstract
The invention provides a manufacture method of a power semiconductor structure with low grid impedance. The method comprises the following steps: forming a grid groove in a silicon substrate; forming a dielectric layer to cover a bare surface of the silicon substrate; forming a grid polysilicon structure in the grid groove; implanting adulterant in the silicon substrate; before a drive-in process, depositing a separating layer to cover at least the bare surface of the grid polysilicon structure; carrying out the drive-in process, and at least forming a body encircling grid polysilicon structure; removing the separating layer in order to expose the grid polysilicon structure; depositing a metal layer on the dielectric layer and the grid polysilicon structure, and subjecting the metal layer to a heating process in order to form a self-aligning metal silicide layer on an upper surface of the grid polysilicon structure. According to the manufacture method provided in the invention, a manufacture flow of the self-aligning metal silicide layer is simplified, and manufacture of the power semiconductor structure with low grid impedance is facilitated.
Description
Technical field
The present invention relates to the manufacture method of the power semiconductor structure of a kind of manufacture method of power semiconductor structure, particularly a kind of low grid impedance.
Background technology
Along with energy-conservation sound is surging gradually, need higher energy conversion efficiency.These are the strict design code requirement day by day, is a severe challenge for the power supply changeover device designer.For in response to this demand, new-type power component institute's role in high-effect transducer is healed and is become important.Wherein, power MOSFET transistor (Power MOSFET) has been widely used in various power supply changeover devices at present.
Figure 1A to Fig. 1 C is that the part of a typical groove power semiconductor structure is made flow process.Below describing with N type power MOSFET transistor (trench power MOSFET) is example.Shown in Figure 1A, at first provide a N type silicon substrate 110.Then, utilize a light shield (figure do not show) to define the position of gate trench 120, and in N type silicon substrate 110, produce a plurality of gate trenchs 120 in the mode of dry ecthing.Subsequently, form the exposed surface of a grid oxic horizon 130,132 in N type silicon substrate 110.
Next, deposit a polysilicon layer (figure does not show) and cover N type silicon substrate 110, and fill up gate trench 120.Then, eat-back (etch back) and remove the part polysilicon layer that is positioned at N type silicon substrate 110 tops, to constitute a plurality of polysilicon gate constructions 140.Subsequently, shown in Figure 1B, implant P type alloy in N type silicon substrate 110 in the mode of comprehensive implanting ions (blanket ion implantation), to form a doped region 150.Then, shown in Fig. 1 C, heat drives in the P type alloy that (drive-in) implants, by to form a P type body (P-body) 150 ' in N type silicon substrate 110.
For the size of dwindling metal-oxide half field effect transistor to improve element integration (integration), the width of gate trench 120 and the degree of depth must be dwindled.Yet the size of gate trench 120 is dwindled the resistance that can cause polysilicon gate construction 140 and is improved, and causes adverse effect for transistorized switch speed, and then causes the increase of switch cost (switching loss).
Because the resistivity of polycrystalline silicon material is higher (usually greater than 1m Ω-cm), in order to reduce the resistance of polysilicon gate construction 140, a typical method is to make metal silicide (Silicide) on polysilicon gate construction 140.Because metal silicide has lower resistance compared to polycrystalline silicon material, therefore can effectively solve the too high problem of grid impedance.
With regard to the processing procedure of typical autoregistration (self-aligned) metal silicide, in order effectively to control its thickness, the making of metal silicide prevents metallic atom under hot environment, spreading simultaneously and pollutes, after must be delayed and drive in step and finish to the ion of ion implantation step and high temperature.Shown in Figure 1B and Fig. 1 C, usually can aerating oxygen in the step that ion heat drives in, and form silicon oxide layer 132 ' in the surface of silicon substrate 110 to prevent that implanting ions is to outdiffusion.But, because the polysilicon gate construction 140 in the gate trench 120 also is outside being exposed to, also can form silicon oxide layer 134 on the surface of polysilicon gate construction 140.Simultaneously because the doping that polysilicon gate construction 140 has high concentration, the thickness of the silicon oxide layers 132 ' that the thickness of the silicon oxide layers 134 that form on polysilicon gate construction 140 surfaces often forms greater than silicon substrate 110 surfaces.
Because silicon oxide layer 134,132 ' can hinder the generation of metal silicide.Therefore, please if desire is made self-aligned metal silicate, must remove the silicon oxide layer 134 on polysilicon gate construction 140 surfaces earlier, keep the silicon oxide layer 132 ' on silicon substrate 110 surfaces simultaneously simultaneously with reference to Fig. 1 C.But, because the thickness of the silicon oxide layer 134 on polysilicon gate construction 140 surfaces is greater than the thickness of the silicon oxide layer 132 ' on silicon substrate 110 surfaces, therefore, be difficult to optionally remove the silicon oxide layer 134 on polysilicon gate construction 140 surfaces, keep the silicon oxide layer 132 ' on silicon substrate 110 surfaces simultaneously by comprehensive etched mode.Also therefore, the silicon oxide layer 132 ' that is difficult to utilize silicon substrate 110 surfaces forms self-aligned metal silicate as shade on polysilicon gate construction 140 surfaces.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of power semiconductor structure, can on polysilicon gate, form self-aligned metal silicate, to reduce the grid impedance of power semiconductor structure.
One embodiment of the invention provide a kind of manufacture method of power semiconductor structure of low grid impedance.At first, form a grid polycrystalline silicon structure in a silicon substrate.This grid polycrystalline silicon structure can be a channel grid polysilicon structure, also can be a plane formula grid polycrystalline silicon structure.Subsequently, implant alloy in silicon substrate by the grid polycrystalline silicon structure.Next, form a separator cover gate polysilicon structure.Then, impose a thermal diffusion (drive-in) processing procedure, form a body all around gate polysilicon structure at least.Subsequently, remove separator, with exposed grid polycrystalline silicon structure.At last, deposit a metal level on dielectric layer and grid polycrystalline silicon structure, and impose a hot processing procedure, to form a self-aligned metal silicate layer in the surface of grid polycrystalline silicon structure.
Can be further understood by means of the following detailed description and accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Figure 1A to Fig. 1 C is the making flow process of a typical groove power semiconductor structure;
Fig. 2 A to Fig. 2 F is first embodiment of the manufacture method of the groove power semiconductor structure of the low grid impedance of the present invention;
Fig. 3 A to Fig. 3 C is second embodiment of the manufacture method of the groove power semiconductor structure of the low grid impedance of the present invention;
Fig. 4 A to Fig. 4 C is the 3rd embodiment of the manufacture method of the groove power semiconductor structure of the low grid impedance of the present invention;
Fig. 5 A to Fig. 5 D is the 4th embodiment of the manufacture method of the groove power semiconductor structure of the low grid impedance of the present invention.
[main element description of reference numerals]
Gate trench 120
Grid oxic horizon 130,132
Polysilicon gate construction 140
Body 150 '
Dielectric layer 230,232
Grid polycrystalline silicon structure 240
Body 250 '
Self-aligned metal silicate layer 285
First doped region 350
Second doped region 370
Body 350 '
Source doping region 370 '
Source doping region 470 '
Separator 560
Embodiment
Major technique feature of the present invention is before bulk doped heat drives in (drive-in) processing procedure, deposit a silicon nitride layer, drive in (body drive-in) processing procedure and source dopant heat drives in (source drive-in) processing procedure and can not form oxide layer in follow-up bulk doped heat with the surface of guaranteeing the grid polycrystalline silicon structure.Thus, can carry out self-aligned metal silicate (salicide) processing procedure, to reduce grid impedance by being positioned at the silicon oxide layer on silicon substrate surface.Technology provided by the present invention is not only applicable to the channel grid polysilicon structure, also applicable to plane formula grid polycrystalline silicon structure.Generally speaking, the manufacture method of plane formula power semiconductor structure is more simple in structure than groove power semiconductor usually, and therefore, following examples only describe with regard to the manufacture method of ditch mortise formula power semiconductor structure.
Fig. 2 A to Fig. 2 F is first embodiment of the manufacture method of the groove power semiconductor structure of the low grid impedance of the present invention.Shown in Fig. 2 A, form a gate trench 220 in a silicon substrate 210.Subsequently, form the exposed surface that a dielectric layer 230,232 covers silicon substrate 210, comprise the inner surface of gate trench and the upper surface of silicon substrate 210.This dielectric layer 230,232 is made of silica, silicon nitride or other dielectric materials that is fit to.Next, form a grid polycrystalline silicon structure 240 in gate trench 220.Then, implant first conductivity type dopant in silicon substrate 210, to form a doped region 250.
Next, please refer to Fig. 2 B,, deposit a separator 260 comprehensively along the surface undulation of silicon substrate 210 with grid polycrystalline silicon structure 240.Mainly in order to the contacting of isolated grid polycrystalline silicon structure 240 and environmental gas, with regard to a preferred embodiment, this separator 260 is made of silicon nitride this separator 260.
Subsequently, shown in Fig. 2 C,, carry out thermal diffusion (drive-in) processing procedure at first conductivity type dopant in the doped region 250 (as shown in phantom in FIG.).In this thermal diffusion processing procedure, the alloy in the doped region 250 spreads (dispersal direction is shown in arrow among the figure) downwards, and forms a body 250 ' all around gate polysilicon structure 240.
Subsequently, shown in Fig. 2 D, the dielectric layer 232 and the separator 260 of the upper surface by being covered in silicon substrate 210 are implanted second conductivity type dopant in body 250 ', and impose another road thermal diffusion processing procedure, to form source doping region 270 in the surf zone of silicon substrate 210.
Next, shown in Fig. 2 E, remove separator 260, make outside the dielectric layer 232 of the upper surface that is positioned at silicon substrate 210 is exposed to the upper surface with gate pole polysilicon structure 240.Then, deposit a metal level 280 on dielectric layer 232 and grid polycrystalline silicon structure 240.Shown in Fig. 2 F, impose a hot processing procedure, for example: rapid thermal annealing processing procedure (Rapid Thermal Annealing, RTA), make the metal level 280 and the interface of grid polycrystalline silicon structure 240 produce reaction, and form self-aligned metal silicate layer 285 on the interface of grid polycrystalline silicon structure 240 and metal level 280.Then, remove unnecessary metal level 280.As for the step of follow-up making source electrode contact hole, non-emphasis of the present invention place does not repeat them here.
In the making flow process of traditional aqueduct type power semiconductor structure, understand because of ion implantation manufacture process and subsequent thermal diffusion process on the surface of polysilicon gate construction 140, and form silicon oxide layer 134, hinder the generation of metal silicide.Simultaneously, the thickness of silicon oxide layer 134 that is formed at polysilicon gate construction 140 surfaces is often greater than the thickness of the silicon oxide layer 132 ' that is formed at silicon substrate 110 surfaces, therefore, be difficult to only remove the silicon oxide layer 134 that is covered in polysilicon gate construction 140 surfaces by etched mode.Also therefore, in processing procedure, be difficult to utilize the silicon oxide layer 132 ' that is covered in silicon substrate 110 surfaces, form the self-aligned metal silicate layer on polysilicon gate construction 140 as shade.
In comparison, shown in Fig. 2 B, present embodiment deposits the surface of a separator 260 cover gate polysilicon structures 240 immediately behind the ion implantation step, thereby can avoid the surface of grid polycrystalline silicon structure 240 to generate silicon oxide layer in the subsequent thermal diffusing step.Also therefore, shown in Fig. 2 E, after the making of finishing body 250 ' and source doping region 270, can utilize the dielectric layer 232 of the upper surface that is positioned at silicon substrate 210 to be shade, form self-aligned metal silicate layer 285 in polysilicon gate construction 140.
Fig. 3 A to Fig. 3 C is second embodiment of the manufacture method of the groove power semiconductor structure of the low grid impedance of the present invention.Please refer to shown in Fig. 3 A, be different from the first embodiment of the present invention, implant the first conductivity type alloy in silicon substrate 210 with after forming a doped region 250, make a separator 260 cover gate polysilicon structures 240 immediately, present embodiment carries out another road ion implantation step again and implants the second conductivity type alloy in silicon substrate 210 implanting the first conductivity type alloy after the step of silicon substrate 210.Through behind this twice ion implantation step, in silicon substrate 210, be formed with second doped region 370 that darker first doped region 350 and of a degree of depth is positioned at silicon substrate 210 surfaces.Wherein, first doped region 350 is first conductivity type, and 370 of second doped regions are second conductivity types.
Subsequently, shown in Fig. 3 B,, deposit a separator 260 along the surface undulation of silicon substrate 210 with grid polycrystalline silicon structure 240 comprehensively.Then, shown in Fig. 3 C, the alloy in first doped region 350 and second doped region 370 (as shown in phantom in FIG.) carries out thermal diffusion (drive-in) processing procedure.In this thermal diffusion processing procedure, the alloys that alloy in first doped region 350 spreads downwards in (dispersal direction is shown in arrow among the figure) formation one body 350 ' all around gate polysilicon structure 240, the second doped regions 370 then are that downward diffusion (dispersal direction is shown in arrow among the figure) forms one source pole doped region 370 ' in the surf zone of silicon substrate 210.
Fig. 4 A to Fig. 4 C is the 3rd embodiment of the manufacture method of the groove power semiconductor structure of the low grid impedance of the present invention, and wherein, the step shown in Fig. 4 A is accepted the step shown in Fig. 2 C.Shown in Fig. 4 A, after forming body 450 all around gate polysilicon structures 240, the dielectric layer 232 and the separator 260 of the upper surface by being covered in silicon substrate 210, implant second conductivity type dopant in body 450, to form a doped region 470, as the source doping region of this groove power semiconductor structure.
Subsequently, shown in Fig. 4 B, remove separator 260, make outside the dielectric layer 232 of the upper surface that is positioned at silicon substrate 210 is exposed to the upper surface with gate pole polysilicon structure 240.Then, deposit a metal level 280 on dielectric layer 232 and grid polycrystalline silicon structure 240.Next, shown in Fig. 2 F, impose a hot processing procedure, for example: rapid thermal annealing processing procedure (Rapid Thermal Annealing, RTA), make the metal level 280 and the interface of grid polycrystalline silicon structure 240 produce reaction, and form self-aligned metal silicate layer 285 in the upper surface of grid polycrystalline silicon structure 240.At the same time, the alloy in the doped region 470 also can spread downwards because of this hot processing procedure, and forms source doping region 470 '.Then, remove unnecessary metal level 280.As for the step of follow-up making source electrode contact hole, non-emphasis of the present invention place does not repeat them here.
Fig. 5 A and Fig. 5 B are the 4th embodiment of the manufacture method of the groove power semiconductor structure of the low grid impedance of the present invention, and wherein, Fig. 5 A accepts Fig. 2 A.Shown in Fig. 5 A, implant first conductivity type dopant and in silicon substrate 210, after the step with formation doped region 250, deposit a separator 560 on silicon substrate 210 and grid polycrystalline silicon structure 240 comprehensively.The thickness of the separator 560 of present embodiment is greater than the separator 260 of the first embodiment of the present invention, and fills up gate trench 220.
Next, shown in Fig. 5 B, remove unnecessary separator 560 materials to eat-back processing procedure, and stay the part separator 562 that is positioned at gate trench 220.This is separator 562 surface of cover gate polysilicon structure 240 only partly, as for 232 of the dielectric layers of the upper surface of silicon substrate 210 be exposed to outside.Eat-back processing procedure in order to carry out this, with regard to a preferred embodiment, can select for use silica to make dielectric layer 232, select for use silicon nitride to make separator 560 simultaneously, to reach the purpose of selective removal separator 560.Certainly, dielectric layer 232 is not limited to this with the constituent material of separator 560, and other are applicable to the dielectric material that eat-backs processing procedure, also can be applicable to the present invention.
Next, shown in Fig. 5 C,, carry out thermal diffusion (drive-in) processing procedure, to form a body 250 ' all around gate polysilicon structure 240 at first conductivity type dopant in the doped region 250 (as shown in phantom in FIG.).Then, shown in Fig. 5 D, implant the second conductivity type alloy in body 250 ' by dielectric layer 232, and impose another road thermal diffusion processing procedure, to form source doping region 270 in the surf zone of silicon substrate 210.The subsequent step and the first embodiment of the invention of present embodiment are roughly the same, do not repeat them here.
Manufacture method provided by the present invention is before the ion thermal diffusion step, and first layer deposited isolating 260 isolated grid polycrystalline silicon structures 240 contact with outside air, can avoid the surface of grid polycrystalline silicon structure 240 to generate silicon oxide layer in thermal diffusion step.Therefore, after the making of the body 250 ' of finishing power semiconductor structure and source doping region 270, can directly utilize the dielectric layer 232 of the upper surface that is positioned at silicon substrate 210 to form self-aligned metal silicate layer 285 in polysilicon gate construction 140 for shade.Thus, manufacture method provided by the present invention can be simplified the making flow process of self-aligned metal silicate layer, and helps the making of the power semiconductor structure of low grid impedance.
But; the above only is preferred embodiment of the present invention, when not limiting claim protection range of the present invention with this; be that all simple equivalent of being done according to claim of the present invention and invention description content change and revise, all still belong in the scope that claim of the present invention contains.Arbitrary embodiment of the present invention in addition or claim must not reach disclosed whole purposes or advantage or characteristics.In addition, summary part and title only are the usefulness that is used for assisting the patent document search, are not to be used for limiting claim protection range of the present invention.
Claims (10)
1. the manufacture method of the power semiconductor structure of a low grid impedance is characterized in that, comprises the following steps:
Form a gate trench in this silicon substrate;
Form a dielectric layer and cover the inner surface of this gate trench and a upper surface of this silicon substrate;
Form this grid polycrystalline silicon structure in this gate trench;
Implant alloy in this silicon substrate;
Form a separator and cover this grid polycrystalline silicon structure;
Impose a thermal diffusion processing procedure, form a body at least around this grid polycrystalline silicon structure;
Remove this separator, with exposed this grid polycrystalline silicon structure; And
Deposit a metal level on this dielectric layer and this grid polycrystalline silicon structure, and impose a hot processing procedure, to form a self-aligned metal silicate layer in the surface of this grid polycrystalline silicon structure.
2. the manufacture method of the power semiconductor structure of low grid impedance as claimed in claim 1 is characterized in that, implants the step of alloy in this silicon substrate and comprises:
One first alloy of implanting first conductivity type is in this silicon substrate; And
One second alloy of implanting second conductivity type is in this silicon substrate;
Wherein, this thermal diffusion processing procedure makes this first alloy and diffusion formation respectively of this second alloy this body and one source pole doped region.
3. the manufacture method of the power semiconductor structure of low grid impedance as claimed in claim 1, it is characterized in that, one first alloy that the step of implantation alloy in this silicon substrate implanted first conductivity type is in this silicon substrate, and this thermal diffusion processing procedure makes this first alloy diffuse to form this body.
4. the manufacture method of the power semiconductor structure of low grid impedance as claimed in claim 3, it is characterized in that, impose this thermal diffusion processing procedure with the step that forms this body after, remove the step of this separator before, comprise that more one second alloy of implanting second conductivity type is in this body.
5. the manufacture method of the power semiconductor structure of low grid impedance as claimed in claim 4 is characterized in that, implant the step of this second alloy in this silicon substrate after, more comprise imposing another thermal diffusion processing procedure, to form the one source pole doped region in this body.
6. the manufacture method of the power semiconductor structure of low grid impedance as claimed in claim 1 is characterized in that, this separator is made of silicon nitride.
7. the manufacture method of the power semiconductor structure of low grid impedance as claimed in claim 1 is characterized in that, this dielectric layer is made of silica.
8. the manufacture method of the power semiconductor structure of low grid impedance as claimed in claim 1 is characterized in that, the step that forms this self-aligned metal silicate layer comprises:
Deposit this metal level comprehensively; And
Impose this hot processing procedure, to form this self-aligned metal silicate layer on the interface of this metal level and this grid polycrystalline silicon structure.
9. the manufacture method of the power semiconductor structure of low grid impedance as claimed in claim 1, it is characterized in that, form this separator and cover of the surface undulation of the step of this grid polycrystalline silicon structure, deposit this separator comprehensively along this silicon substrate and this grid polycrystalline silicon structure.
10. the manufacture method of the power semiconductor structure of low grid impedance as claimed in claim 1 is characterized in that, forms the step that this separator covers this grid polycrystalline silicon structure and comprises:
Deposit this separator comprehensively on this silicon substrate and this grid polycrystalline silicon structure, and fill up this gate trench; And
Processing procedure is eat-back in utilization, stays this separator of part that is positioned at this gate trench.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108231557A (en) * | 2016-12-22 | 2018-06-29 | 英飞凌科技奥地利有限公司 | Complex centre is formed in the semiconductor device |
| CN109103153A (en) * | 2018-08-15 | 2018-12-28 | 深圳市金誉半导体有限公司 | A kind of power device and preparation method thereof |
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Application publication date: 20111130 |