CN102760652A - Manufacture method of semiconductor device - Google Patents
Manufacture method of semiconductor device Download PDFInfo
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- CN102760652A CN102760652A CN2011101043176A CN201110104317A CN102760652A CN 102760652 A CN102760652 A CN 102760652A CN 2011101043176 A CN2011101043176 A CN 2011101043176A CN 201110104317 A CN201110104317 A CN 201110104317A CN 102760652 A CN102760652 A CN 102760652A
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Abstract
The invention discloses a manufacture method of a semiconductor device. The manufacture method comprises the following steps: forming an amorphous dummy grid on a substrate; removing the dummy grid by using a TMAH (tetramethylammonium hydroxide) wet method so as to form a grid opening; and forming a high-k grid dielectric layer and a metal grid layer in the grid opening. According to the manufacture method, the dummy grid of traditional polycrystalline silicon is replaced by the amorphous dummy grid, so that different etching speeds of TMAH cause by different crystal orientations in wet etching can be prevented, the slot surface obtained by TMAH wet method etched amorphous silicon is flat, and the etching speed of each area is the same, reliability reduction, even failure, of the device caused by over etching or incomplete etching of the dummy grid can be avoided, and the reliability of the device is finally improved.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly relate to the method that a kind of use TMAH (TMAH) comes even etching amorphous state dummy grid.
Background technology
IC integrated level constantly increases needs device size lasting scaled, however electrical work voltage remain unchanged sometimes, make actual MOS device internal electric field intensity constantly increase.High electric field brings a series of integrity problems, makes device performance degeneration.For example, during the continuous attenuate of gate oxide, electric field strength is crossed conference and is caused oxide layer breakdown, forms the grid oxic horizon electric leakage, destroys the insulating properties of gate dielectric layer.In order to reduce gate leakage, adopt high k grid dielectric material to substitute SiO
2As gate dielectric.But high k grid dielectric material and polysilicon gate technology are incompatible, so grid often adopts metal material to process.
Form multidigit " back grid " technology that this high k grid dielectric material and metal gate structure are adopted at present.Have shallow trench isolation and be formed with dummy gate structure from the channel region top of the substrate of (STI); Be formed with isolation side walls around the dummy gate structure; Be infused in the source-drain area that the isolation side walls both sides are formed with light dope structure (LDD) through twice ion; Be coated with interlayer dielectric layer on the total, remove dummy gate structure, in the perforate that interlayer dielectric layer stays, fill high k grid dielectric material and metal gates successively to constitute final grid structure.Because the deposition dummy grid forms metal gates more earlier, therefore this process quilt is called the back grid technique, after the high k grid dielectric material of deposition, also will carry out a high annealing to eliminate the defective in the high k grid dielectric material usually.In interlayer dielectric layer, form contact hole corresponding to source-drain area position etching subsequently, the contact site of plated metal in contact hole forms final semiconductor device structure.
From the consideration of process compatible and cost control, the material as dummy grid is a polysilicon usually.The lithographic method of polysilicon dummy grid can be the plasma dry etching; But this dry etching consuming time more, processing step is various and cost is higher; And that dummy grid only is used to fill grid space, back is used, adopts wet etching polysilicon dummy grid so start from cost consideration more.
The wet etching liquid multiselect of current silicon is with TMAH (TMAH), this be because, at first; Metal ion not among the TMAH can not cause damage because of foreign metal ion pair semiconductor device, secondly TMAH have with the approaching corrosion rate of KOH with select ratio; Corrosion surface is effective, and TMAH does not corrode silica and nitrogen oxide basically once more, and the two is used as etching mask convenient use; Last TMAH nontoxic pollution-free, easy to operate.
But, use the dummy grid of TMAH etch silicon material to have certain defective.Because atomic ratio (100) face of (111) face is arranged closeer in the lattice structure of the inside crystal grain of polysilicon; Therefore etch ratio (100) face of (111) face is little; The groove that on small size device, obtains possibly be V-arrangement, is not suitable for controlling the shape of later stage metal gates, during particularly for crystal grain crystal orientation skewness; Etch rate is inconsistent in each zone, and the rustic out-of-flatness even the meeting that can cause etching to form damage substrate because of over etching.Therefore, actual meeting cause dummy grid over etching or etching incomplete owing to the different crystal orientations etch rate is inconsistent when using the dummy grid of TMAH wet etching silicon material, makes device reliability reduce or even component failure.
Generally speaking; There is defective in the dummy grid method of grid technique behind the current employing TMAH wet etching; The inconsistent etching groove shape that causes of etch rate differs under the different crystal orientations, makes that dummy grid over etching or etching are incomplete, makes device reliability reduce or even component failure.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of method that can use the even etch silicon material of TMAH dummy grid, improve etching homogeneity and and then the reliability of boost device.
The invention provides a kind of method, semi-conductor device manufacturing method, comprising: on substrate, form amorphous dummy grid; Use the TMAH wet method to remove said dummy grid, to form gate openings; In said gate openings, form high-k gate dielectric layer and metal gate layers.
Wherein, The step that forms said amorphous dummy grid comprises; On said substrate, form the polysilicon dummy grid; On said polysilicon dummy grid, form cap rock and interlayer dielectric layer, said interlayer dielectric layer of planarization and cap rock carry out decrystallized ion and inject so that said polysilicon dummy grid is converted into said amorphous dummy grid until exposing said polysilicon dummy grid.Wherein, the kind of said decrystallized ion injection comprises Ge, Si, B, As, P or its combination.Wherein, said decrystallized ion implantation dosage scope is from 1 * 10
15To 1 * 10
17Cm
-2Wherein, said cap rock and/or said interlayer dielectric layer comprise silica, silicon nitride or silicon oxynitride.Wherein, said cap rock and said interlayer dielectric layer are the high different materials of etching selection ratio.Wherein, use CVD to form said polysilicon dummy grid, control CVD temperature is higher than 625 ℃.
Wherein, the step that forms said amorphous dummy grid comprises that control CVD temperature is to form amorphous dummy grid.Wherein, said amorphous dummy grid material comprises amorphous silicon, amorphous germanium, amorphous germanium silicon or its combination.Wherein, the said CVD temperature that forms amorphous dummy grid is lower than 580 ℃.
According to method, semi-conductor device manufacturing method of the present invention; Dummy grid 40 through with polysilicon replaces with amorphous dummy grid; Make TMAH when wet etching no longer because crystal orientation difference and etch rate does not wait, the flute surfaces that TMAH wet etching amorphous silicon obtains is smooth, each regional etch rate is identical; Avoid dummy grid over etching or etching to make that not exclusively device reliability reduces or even component failure, finally improved the reliability of device.
Purpose according to the invention, and in these other unlisted purposes, in the scope of the application's independent claims, be able to satisfy.Embodiments of the invention are limited in the independent claims, and concrete characteristic is limited in its dependent claims.
Description of drawings
Followingly specify technical scheme of the present invention with reference to accompanying drawing, wherein:
Figure 1A～Fig. 1 D has shown the generalized section that forms the processing step of the foundation structure that has dummy grid;
Fig. 2 has shown the generalized section of the processing step that decrystallized ion injects;
Fig. 3 has shown the generalized section of the processing step that removes dummy grid;
Fig. 4 has shown the generalized section of the processing step that deposits high k gate dielectric layer;
Fig. 5 has shown the generalized section of the processing step of deposition gate metal layer; And
Fig. 6 has shown the generalized section of the processing step of high k gate dielectric layer of planarization and gate metal layer.
Embodiment
Following with reference to accompanying drawing and combine schematic embodiment to specify the characteristic and the technique effect thereof of technical scheme of the present invention, the method that can use the even etch silicon material of TMAH dummy grid is disclosed.It is pointed out that structure like the similar Reference numeral representation class, used term " first " among the application, " second ", " on ", D score or the like can be used for modifying various device architectures or processing step.These are modified is not space, order or the hierarchical relationship of hint institute's modification device architecture or processing step unless stated otherwise.
Embodiment 1
Embodiment 1 is for forming the illustrative embodiments of back grid technique semiconductor device according to the even etch polysilicon dummy grid of use TMAH of the present invention.
With reference to Figure 1A-1D, shown step (A) according to the embodiment 1 of semiconductor device making method of the present invention, form the foundation structure that has dummy grid.
At first, shown in Figure 1A, for example be that shallow trench isolation deposits pad oxide 30 on the substrate 10 of the isolation structure 20 of (STI) having.Wherein substrate 10 can be body silicon, silicon-on-insulator (SOI) or other siliceous compound semiconductor substrate, for example SiGe, SiC or the like, and the combination of these materials.Except STI, isolation structure 20 can also adopt LOCOS technology to form the thermal oxide isolation, but for small size device, the still preferred STI that uses.Pad oxide is used for protecting substrate in the dummy grid etching process, for example is silica, particularly silicon dioxide (SiO
2).Pad oxide also can also be the grid oxic horizon in the grid technique of back, for example HfO
2Deng high-k dielectric material.Method through for example CVD on pad oxide 30 deposits dummy gate layer 40, and the material of dummy gate layer 40 is polysilicons.Can obtain the polysilicon of unlike material characteristic through the control depositing temperature; For example obtain (110) crystal orientation in the temperature range about 625 ℃ and account for leading polysilicon; Obtain (100) crystal orientation in the temperature range about 675 ℃ and account for leading polysilicon, obtain (111) crystal orientation structure under the 900-1000 ℃ of higher temperature.Adopt mask etching technics commonly used to form the dummy grid stacked structure that overlaps by pad oxide 30, dummy gate layer 40.Carry out source leakage first time dopant ion and inject, it is lower to inject energy, and the source-drain area of formation is more shallow, also promptly forms light dope structure LDD.Uniform deposition cover material 50 on dummy gate layer 40 and substrate 10; Its material is oxide or nitride normally; For example silica (SiO), silicon nitride (SiN) or silicon oxynitride (SiON) or its combination, photoetching subsequently forms the side wall of dummy grid stacked structure side periphery and the cap rock 50 at top.Utilize side wall and cap rock 50 to be mask, carry out source leakage second time dopant ion and inject, it is higher to inject energy, and the source-drain area of formation is darker, therefore forms the heavy-doped source drain region 60 with LDD.
Secondly, shown in Figure 1B, thicker interlayer dielectric layer (ILD) material 70 of deposition on total.The material of interlayer dielectric layer 70 is different with the material of side wall and cap rock 50; The material of etching or polishing selection ratio higher (selection percentage as greater than 2: 1) preferably; For example ILD layer 70 is nitride when side wall and cap rock 50 are oxide, or ILD layer 70 is oxides when side wall and cap rock 50 are nitride.Because dummy gate structure exceeds substrate 10 surfaces, therefore the interlayer dielectric layer 70 of deposition formation exceeds other flat sites in dummy gate region, forms the protuberance shown in Figure 1B.
Subsequently, shown in Fig. 1 C, ILD layer 70 is carried out planarization.Usually adopt chemico-mechanical polishing (CMP), until the top of exposing cap rock 50.
At last, further adopting for example is the flatening process processing of CMP, removes cap rock 50, until the dummy grid that exposes polysilicon 40, receives the protection of ILD layer 70 this moment, and the material layer of dummy grid 40 side periphery is able to keep, and forms side wall 50.
Formation has after the foundation structure of dummy grid, with reference to Fig. 2, carries out decrystallized ion and injects.It is decrystallized to carry out that whole foundation structure is carried out the ion injection, and this decrystallized ionic species comprises germanium Ge, silicon Si, boron, arsenic As, phosphorus P or its combination, is preferably Ge, Si.The implantation dosage scope is from 1 * 10
15To 1 * 10
17Cm
-2Inject energy and select with dosage according to ionic species, if can satisfy feasible decrystallized fully as the polysilicon dummy grid 40 of injection region, for example for 10
16Cm
-2B inject, required injection energy is 40keV.Because material for example is the fine and close ILD layer 70 of nitride or oxide and the existence of isolation side walls 50 and pad oxide 30; Decrystallized ion can only inject the polysilicon dummy grid 40 that exposes; And can't arrive substrate 10 and source-drain area 60; Particularly, thereby further the energy control injection degree of depth is injected in control rationally, and avoiding decrystallized ion to inject influences substrate 10 and source-drain area 60.The decrystallized ion of these high doses has changed the crystal structure of polysilicon in the process of the polysilicon that is injected into dummy grid 40, formed the dummy grid 41 of amorphous silicon in the local original position of dummy grid 40, and is as shown in Figure 2.
Subsequently, remove amorphous silicon dummy gate layer 41 and pad oxide 30.As shown in Figure 3; The TMAH solution of employing 10%～25% comes wet etching to remove dummy gate layer 41; Because dummy gate layer 41 be amorphous silicon, no longer because of the crystal orientation difference and etch rate does not wait, the flute surfaces that TMAH wet etching amorphous silicon obtains is smooth to TMAH when wet etching; Each regional etch rate is identical, has improved the reliability of device.Adopting concentration subsequently is that 5% HF etching liquid comes etching to remove the pad oxide 30 of silica.Remove after dummy grid 41 and the pad oxide 30, stay gate openings 42 in the original place.
Then, deposit high k grid dielectric material.Shown in 4, deposit high k grid dielectric materials layer 80 through methods such as CVD or MBE in gate openings 42 and on the ILD layer 70, thereby and under 500 to 850 ℃ of temperature, anneal alternatively and improve reliability with the defective of repairing in the high k grid dielectric material.High k grid dielectric materials layer 80 materials for example are HfO
2, Al
2O
3, Ta
2O
5, barium titanate BTO or the like or its combination.High k grid dielectric materials layer 80 partially filled gate openings 42.
Then, deposition gate metal layer 90.As shown in Figure 5; On high k grid dielectric materials layer 80, deposit gate metal layer 90 through methods such as CVD or PVD; Its material needs according to the semiconductor device electric property and decides, and particularly, selectes metal material by the gate work-function of decision threshold voltage; Can be Ti, Ta, W, Al or the like metal and alloy, can also be the nitride of these metals.Between gate metal layer 90 and high k grid dielectric materials layer 80, can also form seed layer or depletion layer (not shown), be used to strengthen bond strength and prevent that metallic from diffusing into substrate channel.Though gate metal layer 90 complete filling gate openings 42 shown in Figure 5; But also can partially filled gate openings 42; And then fill gate metal contact layer (not shown) above that, the gate metal contact layer is different with gate metal layer 90 materials, does not possess the effect of regulating gate work-function; Only be used to realize the electrical connection of grid, so its material can be electric conductivity good metal commonly used such as Al, Cu.As shown in Figure 5, high k grid dielectric materials layer 80 constitutes gate stack structure with gate metal layer 90, and wherein high k grid dielectric materials layer 80 not only is positioned at gate metal layer 90 belows, also is positioned at its side periphery.
At last, planarized gate stacked structure.As shown in Figure 6; For example adopt the method for CMP to come the planarized gate stacked structure, remove unnecessary gate metal layer 90 and high k grid dielectric materials layer 80, until exposing ILD layer 70; This moment, gate metal layer 90 was exposed to device surface, so that formation Metal Contact after a while.
Subsequent technique is treated to known in this field; For example in interlayer dielectric layer 70, form the through source-drain area 60 of contact hole after photoetching and the etching; Fill thin contact hole buried regions and thick filling metal level (not shown) in contact hole and on the interlayer dielectric layer 70 successively, cmp planarization contact hole buried regions and filling metal level are until exposing interlayer dielectric layer 70 and gate metal layer 90.The material of contact hole buried regions can be TiN, Ti, TaN or Ta and combination thereof, and its effect is to strengthen the bonding force between the silicon of filling metal level and source-drain area and stop diffusion of impurities.The material of filling metal level can be W, Cu, TiAl or Al and combination thereof, and material is selected the needs according to integrated circuit line layout, preferentially selects the good material of electric conductivity for use.
Embodiment 2
Embodiment 2 and embodiment 1 are similar; Comprise that the formation shown in Figure 1A～Fig. 1 D has the step of the foundation structure of dummy grid, and Fig. 3～shown in Figure 6 removing amorphous state dummy grid, the high k gate dielectric layer of deposition, deposition gate metal layer, cmp planarization gate metal layer and remove high k gate dielectric layer.Embodiment 2 is with the difference of embodiment 1, directly adopts amorphous material as dummy gate layer 40, therefore need not the operation that decrystallized ion shown in Figure 2 injects, and technology is simpler, and cost is lower.Amorphous material for example is amorphous silicon, amorphous germanium or amorphous germanium silicon or the like.
Particularly; In the process of the formation foundation structure shown in Figure 1A; When the method through for example CVD on pad oxide 30 deposits dummy gate layer 40; Can obtain the silicon of unlike material characteristic through the control depositing temperature, for example be lower than under 580 ℃ the temperature, the silicon of deposition is amorphous state basically.Embodiments of the invention 2 adopt be lower than 580 ℃ for example be 450～580 ℃ CVD temperature, preferably adopt 500～550 ℃, particularly 530 ℃.Adopt mask etching technics commonly used to form the dummy grid stacked structure that overlaps by pad oxide 30, dummy gate layer 40 subsequently.
Afterwards, shown in Figure 1B～1D, form cap rock 50, source-drain area 60, ILD layer 70 successively.Again, do not carry out decrystallized ion shown in Figure 2 and inject, but directly execution graph 3～TMAH wet method shown in Figure 6 removes subsequent handlings such as the high k material layer of amorphous dummy gate layer, deposition 80, gate metal layer 90 and planarization and handles.These subsequent handlings and embodiment 1 are similar, no longer stroll at this and state.
According to method, semi-conductor device manufacturing method of the present invention; Dummy grid 40 through with polysilicon replaces with amorphous dummy grid; Make TMAH when wet etching no longer because crystal orientation difference and etch rate does not wait, the flute surfaces that TMAH wet etching amorphous silicon obtains is smooth, each regional etch rate is identical; Avoid dummy grid over etching or etching to make that not exclusively device reliability reduces or even component failure, finally improved the reliability of device.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and device architecture is made various suitable changes and equivalents.In addition, can make by disclosed instruction and manyly possibly be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, the object of the invention does not lie in and is limited to as being used to realize preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacturing approach thereof will comprise all embodiment that fall in the scope of the invention.
Claims (10)
1. method, semi-conductor device manufacturing method comprises:
On substrate, form amorphous dummy grid;
Use the TMAH wet method to remove said dummy grid, to form gate openings;
In said gate openings, form high-k gate dielectric layer and metal gate layers.
2. method, semi-conductor device manufacturing method as claimed in claim 1; Wherein, The step that forms said amorphous dummy grid comprises, on said substrate, forms the polysilicon dummy grid, on said polysilicon dummy grid, forms cap rock and interlayer dielectric layer; Said interlayer dielectric layer of planarization and cap rock carry out decrystallized ion and inject so that said polysilicon dummy grid is converted into said amorphous dummy grid until exposing said polysilicon dummy grid.
3. method, semi-conductor device manufacturing method as claimed in claim 2, wherein, the kind that said decrystallized ion injects comprises Ge, Si, B, As, P or its combination.
4. method, semi-conductor device manufacturing method as claimed in claim 2, wherein, said decrystallized ion implantation dosage scope is from 1 * 10
15To 1 * 10
17Cm
-2
5. method, semi-conductor device manufacturing method as claimed in claim 2, wherein, said cap rock and/or said interlayer dielectric layer comprise silica, silicon nitride or silicon oxynitride.
6. method, semi-conductor device manufacturing method as claimed in claim 5, wherein, said cap rock and said interlayer dielectric layer are the high different materials of etching selection ratio.
7. method, semi-conductor device manufacturing method as claimed in claim 2 wherein, uses CVD to form said polysilicon dummy grid, and control CVD temperature is higher than 625 ℃.
8. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the step that forms said amorphous dummy grid comprises that control CVD temperature is to form amorphous dummy grid.
9. method, semi-conductor device manufacturing method as claimed in claim 8, wherein, said amorphous dummy grid material comprises amorphous silicon, amorphous germanium, amorphous germanium silicon or its combination.
10. method, semi-conductor device manufacturing method as claimed in claim 8, wherein, the temperature that said CVD forms amorphous dummy grid is lower than 580 ℃.
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| CN104681428A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Transistor structure and forming method thereof |
| CN104752180A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device forming method |
| CN104851797A (en) * | 2014-02-14 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Method for removing virtual grid residuals |
| CN106158612A (en) * | 2015-04-14 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN106716624A (en) * | 2014-09-24 | 2017-05-24 | 高通股份有限公司 | Metal-gate with an amorphous metal layer |
| CN107845576A (en) * | 2016-09-19 | 2018-03-27 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN109494149A (en) * | 2017-09-13 | 2019-03-19 | 联华电子股份有限公司 | The production method of semiconductor structure |
| CN109585546A (en) * | 2017-09-29 | 2019-04-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109979812A (en) * | 2019-03-26 | 2019-07-05 | 上海华力集成电路制造有限公司 | The manufacturing method of metal gate |
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| CN109494149A (en) * | 2017-09-13 | 2019-03-19 | 联华电子股份有限公司 | The production method of semiconductor structure |
| CN109585546A (en) * | 2017-09-29 | 2019-04-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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| CN112289681A (en) * | 2020-10-28 | 2021-01-29 | 上海华力集成电路制造有限公司 | Method for removing amorphous silicon layer in groove |
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Application publication date: 20121031 |