CN102024690A - Method for forming self-aligned metal silicide - Google Patents
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Abstract
The invention relates to a method for forming a self-aligned metal silicide, which comprises the following steps of: providing a semiconductor base, wherein the surface of the semiconductor base is provided with at least one silicon area; forming at least two metal layers on the semiconductor base, wherein the sputtering powers of the at least two metal layers are sequentially increased with the sequence of forming each metal layer; carrying out an annealing process on the semiconductor base, and generating a metal silicide through the reaction of the silicon area and the at least two metal layers; and etching to remove the unreacted parts in the at least two metal layers. The invention avoids the problem of nonuniform distribution of alloy elements in the metal layers, prevents the problems of diffusion and intrusion of nickel elements in the central area of the semiconductor base and improves the reliability of devices.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of self-aligned metal silicate.
Background technology
In semiconductor fabrication, metal silicide is widely used in source/drain contact and contacts with grid and reduce contact resistance owing to having lower resistivity and having good adhesiveness with other materials.High-melting point metal and silicon react and fuse the formation metal silicide, can form the metal silicide of low-resistivity by a step or multistep annealing process.Along with the raising of semiconductor process technology, particularly at 90nm and following technology node thereof, in order to obtain lower contact resistance, the alloy of nickel and nickel becomes the main material that forms metal silicide.
At disclosed application number is the formation method that discloses a kind of self-aligned metal silicate in 200780015617.9 the Chinese patent application, and this method selects nickel alloy as the material that forms metal silicide.Fig. 1 to Fig. 3 has provided the cross-sectional view in this method formation each stage of self-aligned silicide.
As shown in Figure 1, the semiconductor-based end 100, at first be provided, be formed with a plurality of MOS transistor (being example only among Fig. 1) at described the semiconductor-based end 100, be formed with isolated area 110 between the adjacent MOS transistor, be filled with insulating material in the described isolated area 110 with a MOS transistor; Described MOS transistor comprises: be formed on the gate dielectric layer 104 at the semiconductor-based end 100, the gate electrode 103 that on described gate dielectric layer 104, forms, the side wall 105 that forms in the both sides of described gate electrode 103 and gate dielectric layer 104, source electrode 101 that described gate electrode 103 both sides form at semiconductor-based the end 100 and drain electrode 102.
As shown in Figure 2, form metal level 106 on the surface at the described semiconductor-based end 100, described metal level 106 covers described source electrode 101, drain electrode 102, grid 103 and side wall 105, and the material of described metal level 106 is the nickel platinum alloy.Further, can form protective layer 107 on metal level 106, the material of described protective layer 107 is titanium nitride (TiN), is used for preventing that metal level 106 is oxidized, and the formation of protective layer 107 is optionally, can be left in the basket.
As shown in Figure 3, to carrying out annealing process in the described semiconductor-based end 100, by annealing, described source electrode 101, drain electrode 102, grid 103 lip-deep metal level 106 materials and described source electrode 101, drain 102 and grid 103 in the silicon materials generation metal silicide layer that reacts, be respectively 101a, 102a, 103a.The metal level 106 that will not react by selective etch is removed afterwards, makes metal silicide layer 101a, the 102a, the 103a that form be exposed to the surface at the described semiconductor-based end 100.
The material of metal level 106 is not selected the nickel metal but the selection nickel alloy in the such scheme, its main cause is that the nickel element activity is higher, spread easily, in the raceway groove below the intrusion grid oxic horizon 104, and the alloying element in the nickel alloy can effectively prevent the diffusion penetration phenomenon of nickel element.
In the prior art, the generally sputtering sedimentation formation under lower-wattage of described metal level 106, main cause is that the metal level that forms under the lower-wattage has resistance consistency (Rs Uniformity) and step coverage (step coverage) preferably on the one hand; Be under the lower-wattage on the other hand, can avoid the ion pair device in the sputter procedure to cause damage.But, the inventor finds, the distribution of alloying element is even inadequately in the metal level 106 that forms under lower-wattage, as shown in Figure 5, the alloying element content of the central area 100a at the described semiconductor-based end 100 is lower than the neighboring area, therefore, the nickel element diffusion phenomena can take place in the device that is distributed in central area 100a, reduce the reliability of device.Though and in sputter procedure, use the more high-power alloying element content that can promote the metal level central area, can cause the resistance consistency and the step coverage reduction of metal level, therefore, need improve the formation method of metal level.
Summary of the invention
The invention provides a kind of formation method of self-aligned metal silicate, avoided the uneven problem of alloying elements distribution in the metal level, prevented the nickel element diffusion penetration phenomenon of central area, the semiconductor-based end, improved the reliability of device.
The invention provides a kind of formation method of self-aligned metal silicate, comprise the steps:
The semiconductor-based end is provided, and this semiconductor-based basal surface has a silicon area at least;
Form two metal layers at least on the described semiconductor-based end, the sputtering power of described two metal layers at least increases successively with the order that forms each layer metal level;
To carrying out annealing process in the described semiconductor-based end, described silicon area and the reaction of described two metal layers at least generate metal silicide;
Etching is removed the part that does not react in the described two metal layers at least.
Preferably, described two metal layers at least comprises ground floor metal level and second layer metal layer, and the sputtering power of described ground floor metal level is 500 watts to 2500 watts.
Ground floor metal layer thickness in the described two metal layers at least accounts for 5% to 20% of the described gross thickness of two metal layers at least.
The sputtering power of the second layer metal layer in the described two metal layers at least is 3000 watts to 6000 watts.
The thickness of the second layer metal layer in the described two metal layers at least accounts for 80% to 95% of the described gross thickness of two metal layers at least.
The material of each layer metal level of described two metal layers at least is identical, is selected from nickel platinum alloy or Ni-Pd alloy.
The atmosphere of the forming process of described two metal layers at least is argon gas (Ar).
Argon flow amount in the described layer formation process of double layer of metal at least reduces successively with the order that forms each layer metal level.
The flow of argon gas is 25sccm to 100sccm in the forming process of the ground floor metal level in the described two metal layers at least.
The flow of argon gas is 10sccm to 20sccm in the forming process of the second layer metal layer in the described two metal layers at least.
Described annealing process is a step annealing or double annealing.
Described double annealing comprises the first step annealing and second step annealing, and the temperature of first step annealing is 280 degrees centigrade to 350 degrees centigrade, and annealing time is 3 seconds to 60 seconds; The temperature of second annealing is 360 degrees centigrade to 900 degrees centigrade, and annealing time is 3 seconds to 60 seconds.A described step annealing only comprises above-mentioned first step annealing.
In the formation method of above-mentioned disclosed self-aligned metal silicate, divide a plurality of stages to form two metal layers at least, the power that uses in each layer metal level forming process increases successively, avoided the uneven problem of alloying elements distribution in the metal level, prevent the nickel element diffusion intrusion problem of central area, the semiconductor-based end, improved the reliability of device.
Description of drawings
Fig. 1 to Fig. 3 is the cross-sectional view of the self-aligned metal silicate formation method of prior art;
Fig. 4 is the cross-sectional view after the nickel element diffusion in the self-aligned silicide forming process;
Fig. 5 is the vertical view at the semiconductor-based end behind the formation metal level under the prior art;
Fig. 6 is the schematic flow sheet of the self-aligned silicide formation method of one embodiment of the present of invention;
Fig. 7 to Figure 12 is the cross-sectional view of the self-aligned silicide formation method of one embodiment of the present of invention.
Embodiment
The invention provides a kind of formation method of self-aligned metal silicate, this method divides a plurality of stages to form two metal layers at least, the power that uses in each layer metal level forming process increases successively, avoided the uneven problem of alloying elements distribution in the metal level, prevent the nickel element diffusion intrusion problem of central area, the semiconductor-based end, improved the reliability of device.
For method of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The invention provides a kind of formation method of self-aligned metal silicate, comprising: the semiconductor-based end is provided, and described semiconductor-based basal surface has a silicon area at least; Form two metal layers at least on the described semiconductor-based end, the sputtering power of described two metal layers at least increases successively with the order that forms each layer metal level; To carrying out annealing process in the described semiconductor-based end; Etching is removed described two metal layers at least.Described two metal layers at least can be for two-layer, and three layers or more multi-layered metal level are that example is elaborated to the specific embodiment of the present invention below with the two metal layers.
Fig. 6 has provided the schematic flow sheet of the self-aligned silicide formation method of one embodiment of the present of invention.In the present embodiment, be that example is illustrated, should too do not limit protection scope of the present invention at this to form two metal layers.
As shown in Figure 6, execution in step S1 provides the semiconductor-based end, and described semiconductor-based basal surface has a silicon area at least; Execution in step S2 forms the ground floor metal level with first power on the described semiconductor-based end; Execution in step S3 uses second power greater than first power to form the second layer metal layer on the described semiconductor-based end; Execution in step S4, to carrying out annealing process in the described semiconductor-based end, described silicon area and the reaction of described two metal layers at least generate metal silicide; Execution in step S5, etching is removed the part that does not react in the described two metal layers at least.
Fig. 7 to Figure 12 is the cross-sectional view of the formation self-aligned silicide of one embodiment of the present of invention.
With reference to figure 7, the semiconductor-based end 200, be provided, have a silicon area at least on surface, the described semiconductor-based ends 200.The material at the described semiconductor-based end 200 can be a kind of in monocrystalline silicon, the amorphous silicon, the material at the described semiconductor-based end 200 also can be a silicon Germanium compound, the described semiconductor-based end 200 can also be an epitaxial layer structure on silicon-on-insulator (SOI, Silicon On Insulator) structure or the silicon.Be example with the semiconductor-based end 200 that includes MOS (metal-oxide-semiconductor) memory in the present embodiment, described MOS (metal-oxide-semiconductor) memory comprises source electrode 201, drain electrode 202 and grid 203; Described source electrode 201, drain electrode 202 surfaces are silicon materials, and described grid 203 surfaces are polycrystalline silicon material; Below described grid 203 grid oxic horizon 204 is arranged, the material of described grid oxic horizon 204 can be a silica; Be formed with side wall (spacer) 205 in described grid 203 both sides, the material of described side wall can be a kind of or combination in silica, the silicon nitride; Be formed with isolated area 210 in the described semiconductor-based end, the material of isolated area 210 is a kind of or its combination in dielectric such as silica, silicon nitride, the carborundum.
Because the forming process of metal silicide is relatively more responsive to the cleannes of silicon face, before forming metal level, can clean the surface at the described semiconductor-based end 200, remove the pollutant and the oxide of remained on surface, improve the contact resistance of the metal silicide that forms.The use proportioning is 100: 1 H in this enforcement
2O and HF solution clean the surface at the affiliated semiconductor-based end 200.
With reference to figure 8, the use preferable range is 500 watts to 2500 watts first power, forms ground floor metal level 206 on the surface at the described semiconductor-based end 200.
The material of the metal level of ground floor described in the present embodiment 206 is nickel platinum alloy or Ni-Pd alloy, preferred nickel platinum alloy in the present embodiment.The thickness of described ground floor metal level 206 accounts for 5% to 20% of metal level gross thickness, is preferably 10% in the present embodiment.The gross thickness of described metal level can be according to source electrode 201, drain electrode 202, and grid 203 surfaces can be decided for the contact resistance of silicon that consumes and the metal silicide that will form.
The formation method of the metal level of ground floor described in the present embodiment 206 is a physical vapour deposition (PVD).The atmosphere of deposition process is argon gas, the flow of described argon gas be 25sccm (ml/min) to 100sccm, preferred argon flow amount is 30sccm in the present embodiment.
The power that the forming process of described ground floor metal level 206 is used is less, guaranteed that described the first metal layer 206 has resistance consistency and step coverage preferably on the one hand, on the other hand, less sputtering power has avoided that device is sustained damage by ion bombardment in the sputter procedure.
With reference to figure 9, use second power greater than first power, form second layer metal layer 207 on the surface at the described semiconductor-based end 200.
The material of described second layer metal layer 207 is identical with ground floor metal level 206, and the material of second layer metal layer 207 described in the present embodiment is the nickel platinum alloy.Be example with the two metal layers in the present embodiment, therefore, the thickness of described second metal level 207 is 90% of metal level gross thickness.
The formation method of described second layer metal layer 207 is a physical vapour deposition (PVD), and is preferred, and the sputter procedure of described deposition process and formation ground floor metal level 206 is original position (in-situ) deposition in same equipment.The power that forms metal level increases with forming order, and described second power is greater than forming ground floor metal level 206 employed first power, and preferable range is 3000 watts to 6000 watts, and preferred second power is 4000 watts in the present embodiment.The atmosphere of described deposition process is argon gas, argon flow amount reduces with the formation order of metal level, the flow of the argon gas that uses is lower than the flow that forms argon gas in ground floor metal level 206 processes in second layer metal layer 206 forming process, be 10sccm to 20sccm, the flow of preferred argon gas is 15sccm in the present embodiment.
The power that uses in the forming process of described second layer metal layer 207 is bigger, has improved the content of alloying element in the central area metal level of the described semiconductor-based ends 200, reduces thereby avoided the nickel element diffusion to invade the reliability that causes device in the gate oxide 204.
Present embodiment is to be example with the two metal layers, in practice, after described second layer metal layer 207 forms, can add a step or a multistep deposition process again, forms the 3rd layer or more multi-layered metal level.The employed power of subsequent deposition process increases successively, and the argon flow amount in the corresponding deposition process reduces successively.
With reference to Figure 10, after forming described second layer metal layer 207, form protective layer 208 on the surface at the described semiconductor-based end 200.
The material of described protective layer 208 is titanium nitride (TiN), and protective layer 208 can prevent from describedly to comprise ground floor metal level 206 and second layer metal layer 207 ingress of air and oxidized.The formation of described protective layer 208 is optionally, can omit this step in other embodiments.
With reference to Figure 11, to carrying out annealing process in the described semiconductor-based end 200.
Described annealing process is a step annealing or double annealing, is preferably double annealing in the present embodiment.Described double annealing comprises the first step annealing and second step annealing, and the temperature of first step annealing is 280 degrees centigrade to 350 degrees centigrade, and the duration is 3 seconds to 60 seconds, and atmosphere is selected from helium, argon gas, nitrogen, and preferred atmosphere is nitrogen in the present embodiment.
Anneal by the first step, the silicon or the polycrystalline silicon material of metal material nickel in described ground floor metal level 206 and the second layer metal layer 207 and source electrode 201 at the semiconductor-based end 200, drain electrode 202 and grid 203 upper surfaces react, generate metal silicide layer 201a, 202a, 203a respectively, and the side wall 205 at the described semiconductor-based end 200, the silicon nitride in the isolated area 210 or silica material do not react, this makes in follow-up processing procedure, can remove the described metal level that does not react by selective etch.Through above-mentioned annealing, described ground floor metal level 206 and second layer metal layer 207 form metal level 206a.
After described first step annealing, carry out second step annealing again.Temperature when the temperature of described second step annealing is higher than the annealing of the above-mentioned first step is 360 degrees centigrade to 900 degrees centigrade.The duration of described second step annealing is 3 seconds to 60 seconds, and atmosphere is selected from helium, argon gas, nitrogen.Described second step annealing can carry out in same annealing device with first step annealing, also can carry out in distinct device.
After the described first step annealing, the main product of described metal silicide 201a, 202a, 203a is Ni
2Si, resistivity is higher, after second step annealing, Ni
2Si can further be converted into NiSi, and the resistivity of NiSi and Ni
2Si compares low, can further reduce the contact resistance of described metal silicide.
With reference to Figure 12,, the part that does not have among described protective layer 208 and the metal level 206a and silicon materials react is removed carrying out selective etch in the described semiconductor-based end 200.Expose described metal silicide layer 201a, 202a, 203a, finish the forming process of self-aligned metal silicate.
Described etching process is a wet etching, the material of present embodiment metal level 206a is the nickel platinum alloy, in order effectively to remove unreacted platinum, the preferred etching solution of present embodiment is a chloroazotic acid, comprises the nitric acid of about 40% to 80% volume, the hydrochloric acid of about 20% to 60% volume.After etching finishes, the dry then residual etching solution of removing trace of rinsing is carried out at the described semiconductor-based end 200.
In order to check the effect of the disclosed scheme of the present invention, the inventor has carried out the contrast experiment.Semiconductor-based end A and semiconductor-based end B are provided, described semiconductor-based end A are used the disclosed metal silicide of prior art formation method, and described semiconductor-based end B is used the disclosed metal silicide of the foregoing description formation method.The result shows that behind the formation metal level, the fringe region platinum elements atomic percentage of semiconductor-based end A is 6.5%, and the central area is 5.57%, and the content of central area platinum element is obviously on the low side; The fringe region platinum elements atomic percentage of semiconductor-based end B is 6.4%, and the central area is 6.5%, and the platinum element distributes and has higher consistency.And after metal silicide formed, because the defective device count that nickel element diffusion intrusion causes is 28, defective device count then was 0 among the semiconductor-based end B among the semiconductor-based end A.
Be example with the two metal layers among the embodiment that the present invention provides, but in practice, can form the 3rd layer or more multi-layered metal level, at this, the foregoing description should excessively not limit the present invention.
To sum up, the invention provides a kind of formation method of self-aligned metal silicate.Compared with prior art, the present invention divides a plurality of stages to form two metal layers at least, the power that uses in each layer metal level forming process increases successively, avoided the uneven problem of alloying elements distribution in the metal level, prevent the nickel element diffusion intrusion problem of central area, the semiconductor-based end, improved the reliability of device.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (11)
1. the formation method of a self-aligned metal silicate is characterized in that, comprising:
The semiconductor-based end is provided, and described semiconductor-based basal surface has a silicon area at least;
Form two metal layers at least on the described semiconductor-based end, the sputtering power of described two metal layers at least increases successively with the order that forms each layer metal level;
To carrying out annealing process in the described semiconductor-based end, described silicon area and the reaction of described two metal layers at least generate metal silicide;
Etching is removed the part that does not react in the described two metal layers at least.
2. the formation method of self-aligned metal silicate according to claim 1, it is characterized in that: described two metal layers at least comprises ground floor metal level and second layer metal layer, the sputtering power of described ground floor metal level is 500 watts to 2500 watts.
3. according to the formation method of the described self-aligned metal silicate of claim 2, it is characterized in that: the ground floor metal layer thickness in the described two metal layers at least accounts for 5% to 20% of the described gross thickness of two metal layers at least.
4. the formation method of self-aligned metal silicate according to claim 2, it is characterized in that: the sputtering power of the second layer metal layer in the described two metal layers at least is 3000 watts to 6000 watts.
5. according to the formation method of the described self-aligned metal silicate of claim 4, it is characterized in that: the thickness of the second layer metal layer in the described two metal layers at least accounts for 80% to 95% of the described gross thickness of two metal layers at least.
6. according to the formation method of claim 2 or 4 described self-aligned metal silicate, it is characterized in that: the material of each layer metal level of described two metal layers at least is identical, is selected from nickel platinum alloy or Ni-Pd alloy.
7. the formation method of self-aligned metal silicate according to claim 1, it is characterized in that: the atmosphere of the forming process of described two metal layers at least is argon gas.
8. the formation method of self-aligned metal silicate according to claim 7 is characterized in that: the argon flow amount in the described layer formation process of double layer of metal at least reduces successively with the order that forms each layer metal level.
9. the formation method of self-aligned metal silicate according to claim 8, it is characterized in that: the flow of argon gas is 25sccm to 100sccm in the forming process of the ground floor metal level in the described two metal layers at least.
10. the formation method of self-aligned metal silicate according to claim 8, it is characterized in that: the flow of argon gas is 10sccm to 20sccm in the forming process of the second layer metal layer in the described two metal layers at least.
11. self-aligned metal silicate according to claim 1 is characterized in that: described annealing process comprises the first step annealing and second step annealing, and the temperature of first step annealing is 280 degrees centigrade to 350 degrees centigrade, and annealing time is 3 seconds to 60 seconds; The temperature of second annealing is 360 degrees centigrade to 900 degrees centigrade, and annealing time is 3 seconds to 60 seconds.
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| CN200910196203A CN102024690B (en) | 2009-09-23 | 2009-09-23 | Method for forming self-aligned metal silicide |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137462A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
| CN103794480A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN106033721A (en) * | 2015-03-11 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Method for metal silicide formation |
| CN115655384A (en) * | 2022-12-27 | 2023-01-31 | 江苏国嘉导体技术科技有限公司 | Flexible aluminum alloy conductor performance detection and evaluation method and system |
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2009
- 2009-09-23 CN CN200910196203A patent/CN102024690B/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137462A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
| CN103137462B (en) * | 2011-11-25 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | The formation method of self-aligned metal silicate |
| CN103794480A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103794480B (en) * | 2012-10-29 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of a kind of semiconducter device |
| CN106033721A (en) * | 2015-03-11 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Method for metal silicide formation |
| CN106033721B (en) * | 2015-03-11 | 2019-10-25 | 中芯国际集成电路制造(上海)有限公司 | The method for forming metal silicide |
| CN115655384A (en) * | 2022-12-27 | 2023-01-31 | 江苏国嘉导体技术科技有限公司 | Flexible aluminum alloy conductor performance detection and evaluation method and system |
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