CN103794480A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN103794480A CN103794480A CN201210422159.3A CN201210422159A CN103794480A CN 103794480 A CN103794480 A CN 103794480A CN 201210422159 A CN201210422159 A CN 201210422159A CN 103794480 A CN103794480 A CN 103794480A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- mask layer
- grid structure
- semiconductor substrate
- sides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
Abstract
The present invention provides a method for manufacturing a semiconductor device. The method comprises the steps of providing a semiconductor substrate, and forming a grid dielectric layer, a grid material layer and a hard mask layer on the semiconductor substrate orderly; etching the hard mask layer, taking the etched hard mask layer as a mask, and partially etching back the grid material layer; forming first side walls at the two sides of the hard mask layer, etching the grid material layer and the grid dielectric layer by taking the first side walls as the masks, and forming a grid structure on the semiconductor substrate; forming second side walls at the two sides of the grid structure; removing the hard mask layer and the first side walls, and forming grooves at the two sides of the top of the grid structure; forming a self-aligning metal silicide. According to the present invention, by forming the grooves at the two sides of the top of the grid structure, the surface area of the grid structure is increased, and a grid resistance is reduced further.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method that reduces resistance.
Background technology
In Metal-oxide-semicondutor manufacturing process, the resistance that is formed for reducing cmos device of self-aligned metal silicate, and then the speed of service of boost device.
The formation technique of existing self-aligned metal silicate comprises the steps: first, to provide Semiconductor substrate, forms isolation structure and various well structure in described Semiconductor substrate; Then, in described Semiconductor substrate, form the side wall construction of grid structure, grid structure both sides and take described side wall construction as mask, in the Semiconductor substrate of described side wall construction both sides, form source/drain region; Finally, on described source/drain region and the top of described grid structure form self-aligned metal silicate.
Along with constantly dwindling of dimensions of semiconductor devices, the size of the grid of semiconductor device is constantly reduction thereupon also, the most significant variation is the reduction of the length of grid, thereby causes the increase of resistance (such as grid sheet resistance), causes the decline of device performance.Meanwhile, the surface area that increases grid under the prerequisite that does not increase grid length can reduce the sheet resistance of grid effectively.
Therefore, a kind of method that need to propose surface configuration that changes grating of semiconductor element increases the surface area of grid, and then reduces resistance.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, forms successively gate dielectric, gate material layers and hard mask layer; Hard mask layer described in etching, and take through described etched hard mask layer as mask, gate material layers described in part etch-back; Both sides at described hard mask layer form the first side wall; Take described the first side wall as mask, gate material layers and gate dielectric described in etching form grid structure in described Semiconductor substrate; Form the second sidewall in the both sides of described grid structure; Remove described hard mask layer and described the first side wall, form groove in the both sides at described grid structure top; Form self-aligned metal silicate.
Further, the constituent material of described gate dielectric comprises oxide.
Further, the constituent material of described gate material layers comprises polysilicon.
Further, the constituent material of described hard mask layer comprises the combination in any of oxide, nitride, nitrogen oxide, amorphous carbon, boron nitrogen or above material.
Further, the etching process of described hard mask layer comprises the following steps: the photoresist layer that forms patterning on described hard mask layer; Adopt dry method etch technology to remove the hard mask layer not covered by described photoresist layer; Adopt cineration technics to remove described photoresist layer.
Further, after described part etch-back process finishes, the thickness of described hard mask layer is greater than 100 dusts.
The thickness of the gate material layers that further, described part etch-back process is removed is 50-500 dust.
Further, the constituent material of described the first side wall comprises the combination in any of oxide, nitride, nitrogen oxide, amorphous carbon, boron nitrogen or above material.
Further, the constituent material of described the second sidewall comprises the combination in any of oxide, nitride, nitrogen oxide, amorphous carbon, boron nitrogen or above material.
Further, the height of described the second sidewall is greater than or less than the height of described grid structure.
Further, described grid structure is made up of the described gate dielectric stacking gradually and described gate material layers.
Further, before the removal process of described hard mask layer and described the first side wall or afterwards, also comprise the step of carrying out an Implantation, to form source region and drain region in the Semiconductor substrate of described the second sidewall both sides.
Further, adopt self-aligned silicide barrier layer technique to form described self-aligned metal silicate.
According to the present invention, form groove by the both sides at described grid structure top and increase the surface area of described grid structure, and then reduce resistance.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 G is the schematic cross sectional view of each step of the method for the reduction resistance that proposes of the present invention;
Fig. 2 is the flow chart of the method for the reduction resistance that proposes of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the method for the reduction resistance that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
The detailed step of the method for the reduction resistance that the present invention proposes is described with reference to Figure 1A-Fig. 1 G and Fig. 2 below.
With reference to Figure 1A-Fig. 1 G, wherein show the schematic cross sectional view of each step of the method for the reduction resistance of the present invention's proposition.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.As example, in the present embodiment, described Semiconductor substrate 100 selects single crystal silicon material to form.In described Semiconductor substrate 100, be formed with isolation structure 101, described isolation structure 101 is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.In described Semiconductor substrate 100, to be also formed with various traps (well) structure, in order simplifying, in diagram, to be omitted.
Next, in described Semiconductor substrate 100, form successively gate dielectric 102, gate material layers 103 and hard mask layer 104.The constituent material of described gate dielectric 102 can comprise oxide, as silicon dioxide (SiO
2); The constituent material of described gate material layers 103 can comprise polysilicon; The constituent material of described hard mask layer 104 can comprise the combination in any of oxide, nitride, nitrogen oxide, amorphous carbon, boron nitrogen (BN) or above material.Form the various suitable technology that the technique of described gate dielectric 102, described gate material layers 103 and described hard mask layer 104 can adopt those skilled in the art to have the knack of, for example chemical vapor deposition method or physical gas-phase deposition.
Then, as shown in Figure 1B, hard mask layer 104 described in etching, described etching process comprises the following steps: the photoresist layer that forms patterning on described hard mask layer 104; Adopt dry method etch technology to remove the hard mask layer 104 not covered by described photoresist layer; Adopt cineration technics to remove described photoresist layer.
Next, take through described etched hard mask layer 104 as mask, gate material layers 103 described in part etch-back.The thickness of the gate material layers 103 that described part etch-back process is removed is 50-500 dust, and after described part etch-back process finishes, the thickness of described hard mask layer 104 is greater than 100 dusts.Implement the various suitable technology that described etch-back can adopt those skilled in the art to have the knack of, for example dry method etch technology.
Then, as shown in Figure 1 C, form the first side wall 105 in the described both sides through overetched hard mask layer 104.The constituent material of described the first side wall 105 can comprise the combination in any of oxide, nitride, nitrogen oxide, amorphous carbon, boron nitrogen (BN) or above material.Forming described the first side wall 105 comprises the following steps: in described Semiconductor substrate 100, deposit a material layer, then, material layer is to form described the first side wall 105 described in etching.
Then,, as shown in Fig. 1 D, take described the first side wall 105 as mask, gate material layers 103 and gate dielectric 102 described in etching form grid structure in described Semiconductor substrate 100.Implement the various suitable technology that described etching can adopt those skilled in the art to have the knack of, for example dry method etch technology.
Then,, as shown in Fig. 1 E, form the second sidewall 106 in the both sides of described grid structure.The constituent material of described the second sidewall 106 can comprise the combination in any of oxide, nitride, nitrogen oxide, amorphous carbon, boron nitrogen (BN) or above material.Forming described the second sidewall 106 comprises the following steps: in described Semiconductor substrate 100, deposit another material layer, then, another material layer is to form described the second sidewall 106 described in etching.The height of described the second sidewall 106 can be greater than or less than the height of described grid structure.
Then, as shown in Fig. 1 F, remove the hard mask layer 104 and the described the first side wall 105 that are positioned at described grid structure top, form groove 107 in the both sides at described grid structure top.The various suitable technology that adopts those skilled in the art to have the knack of is implemented described removal process, for example dry method etch technology or wet etching process.
Next, carry out an Implantation, to form source region 108 and drain region 109 in the Semiconductor substrate 100 of described the second sidewall 106 both sides.Described Implantation also can be implemented before described removal process.
Then, as shown in Figure 1 G, form self-aligned metal silicate 110 on the surface of described source region 108, described drain region 109 and described grid structure.In the present embodiment, be positioned at the lip-deep self-aligned metal silicate of described grid structure 110 and be positioned at that the lip-deep self-aligned metal silicate 110 in described source region 108, described drain region 109 is formed separately, therefore self-aligned silicide barrier layer (SAB) technique that, adopts those skilled in the art to have the knack of forms described self-aligned metal silicate 110.
So far, completed whole processing steps that method is implemented according to an exemplary embodiment of the present invention, can complete by subsequent technique the making of whole semiconductor device, described subsequent technique is identical with traditional process for fabricating semiconductor device.According to the present invention, form groove by the both sides at described grid structure top and increase the surface area of described grid structure, and then reduce resistance.
With reference to Fig. 2, wherein show the flow chart of the method for the reduction resistance of the present invention's proposition, for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, in described Semiconductor substrate, form successively gate dielectric, gate material layers and hard mask layer;
In step 202, hard mask layer described in etching, and take through described etched hard mask layer as mask, gate material layers described in part etch-back;
In step 203, form the first side wall in the both sides of described hard mask layer;
In step 204, take described the first side wall as mask, gate material layers and gate dielectric described in etching form grid structure in described Semiconductor substrate;
In step 205, form the second sidewall in the both sides of described grid structure;
In step 206, remove described hard mask layer and described the first side wall, form groove in the both sides at described grid structure top;
In step 207, form self-aligned metal silicate.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms successively gate dielectric, gate material layers and hard mask layer;
Hard mask layer described in etching, and take through described etched hard mask layer as mask, gate material layers described in part etch-back;
Both sides at described hard mask layer form the first side wall;
Take described the first side wall as mask, gate material layers and gate dielectric described in etching form grid structure in described Semiconductor substrate;
Form the second sidewall in the both sides of described grid structure;
Remove described hard mask layer and described the first side wall, form groove in the both sides at described grid structure top;
Form self-aligned metal silicate.
2. method according to claim 1, is characterized in that, the constituent material of described gate dielectric comprises oxide.
3. method according to claim 1, is characterized in that, the constituent material of described gate material layers comprises polysilicon.
4. method according to claim 1, is characterized in that, the constituent material of described hard mask layer comprises the combination in any of oxide, nitride, nitrogen oxide, amorphous carbon, boron nitrogen or above material.
5. method according to claim 1, is characterized in that, the etching process of described hard mask layer comprises the following steps: the photoresist layer that forms patterning on described hard mask layer; Adopt dry method etch technology to remove the hard mask layer not covered by described photoresist layer; Adopt cineration technics to remove described photoresist layer.
6. method according to claim 1, is characterized in that, after described part etch-back process finishes, the thickness of described hard mask layer is greater than 100 dusts.
7. method according to claim 1, is characterized in that, the thickness of the gate material layers that described part etch-back process is removed is 50-500 dust.
8. method according to claim 1, is characterized in that, the constituent material of described the first side wall comprises the combination in any of oxide, nitride, nitrogen oxide, amorphous carbon, boron nitrogen or above material.
9. method according to claim 1, is characterized in that, the constituent material of described the second sidewall comprises the combination in any of oxide, nitride, nitrogen oxide, amorphous carbon, boron nitrogen or above material.
10. method according to claim 1, is characterized in that, the height of described the second sidewall is greater than or less than the height of described grid structure.
11. according to the method described in claim 1 or 10, it is characterized in that, described grid structure is made up of the described gate dielectric stacking gradually and described gate material layers.
12. methods according to claim 1, it is characterized in that, before the removal process of described hard mask layer and described the first side wall or afterwards, also comprise the step of carrying out an Implantation, to form source region and drain region in the Semiconductor substrate of described the second sidewall both sides.
13. methods according to claim 1, is characterized in that, adopt self-aligned silicide barrier layer technique to form described self-aligned metal silicate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210422159.3A CN103794480B (en) | 2012-10-29 | 2012-10-29 | The manufacture method of a kind of semiconducter device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210422159.3A CN103794480B (en) | 2012-10-29 | 2012-10-29 | The manufacture method of a kind of semiconducter device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103794480A true CN103794480A (en) | 2014-05-14 |
| CN103794480B CN103794480B (en) | 2016-06-01 |
Family
ID=50670032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210422159.3A Active CN103794480B (en) | 2012-10-29 | 2012-10-29 | The manufacture method of a kind of semiconducter device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103794480B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069032A (en) * | 1999-08-17 | 2000-05-30 | United Silicon Incorporated | Salicide process |
| US6498067B1 (en) * | 2002-05-02 | 2002-12-24 | Taiwan Semiconductor Manufacturing Company | Integrated approach for controlling top dielectric loss during spacer etching |
| KR20030056910A (en) * | 2001-12-28 | 2003-07-04 | 주식회사 하이닉스반도체 | Method for forming salicide of semiconductor device |
| CN1945835A (en) * | 2005-10-05 | 2007-04-11 | 松下电器产业株式会社 | Semicondutor device and method for fabricating the same |
| CN102024690A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
-
2012
- 2012-10-29 CN CN201210422159.3A patent/CN103794480B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069032A (en) * | 1999-08-17 | 2000-05-30 | United Silicon Incorporated | Salicide process |
| KR20030056910A (en) * | 2001-12-28 | 2003-07-04 | 주식회사 하이닉스반도체 | Method for forming salicide of semiconductor device |
| US6498067B1 (en) * | 2002-05-02 | 2002-12-24 | Taiwan Semiconductor Manufacturing Company | Integrated approach for controlling top dielectric loss during spacer etching |
| CN1945835A (en) * | 2005-10-05 | 2007-04-11 | 松下电器产业株式会社 | Semicondutor device and method for fabricating the same |
| CN102024690A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103794480B (en) | 2016-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2010144289A1 (en) | Finfet structures with stress-inducing source/drain-forming spacers and methods for fabricating same | |
| TW200947608A (en) | FinFETs having dielectric punch-through stoppers | |
| WO2012159329A1 (en) | Method for manufacturing surround-gate silicon nanowire transistor with air as sidewall | |
| CN103187277B (en) | A kind of manufacture method of semiconductor device | |
| US20090191688A1 (en) | Shallow Trench Isolation Process Using Two Liners | |
| CN111755333A (en) | Nano-sheet field effect transistor and preparation method thereof | |
| US8269318B2 (en) | MOS device | |
| CN104576501B (en) | A kind of semiconductor devices and its manufacture method | |
| CN103177963B (en) | A kind of manufacture method of FinFET | |
| CN103779211A (en) | Manufacturing method for semiconductor device | |
| CN103855074B (en) | A kind of manufacture method of semiconductor device | |
| CN103855021A (en) | Manufacturing method for FinFET device | |
| CN102856199A (en) | Manufacturing method of semiconductor device | |
| CN103151264A (en) | Manufacturing method of semiconductor device | |
| CN104835738A (en) | Method of forming fins of FinFET device | |
| CN104124156A (en) | Semiconductor device manufacturing method | |
| CN103855019A (en) | Method for manufacturing semiconductor device | |
| CN103794480A (en) | Method for manufacturing semiconductor device | |
| CN104425350A (en) | Semiconductor device and preparation method thereof | |
| CN103137451A (en) | Production method of semiconductor device | |
| CN102956456A (en) | Manufacturing method of semiconductor devices | |
| CN104124145A (en) | Semiconductor device manufacturing method | |
| CN104681445B (en) | The method for making FinFET | |
| CN103579110B (en) | A kind of manufacture method of semiconductor device | |
| CN104752307A (en) | Shallow trench isolation structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |