CN104752307A - Shallow trench isolation structure and manufacturing method thereof - Google Patents
Shallow trench isolation structure and manufacturing method thereof Download PDFInfo
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- CN104752307A CN104752307A CN201310727286.9A CN201310727286A CN104752307A CN 104752307 A CN104752307 A CN 104752307A CN 201310727286 A CN201310727286 A CN 201310727286A CN 104752307 A CN104752307 A CN 104752307A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
Abstract
The invention provides a manufacturing method for a shallow trench isolation structure. The method comprises the following steps: providing a semiconductor substrate, and forming a gasket oxide layer and a hard mask layer on the semiconductor substrate in sequence; etching the hard mask layer, the gasket oxide layer and the semiconductor substrate in sequence to form a first shallow trench; continually etching the side wall and the bottom of the first shallow trench to form a second shallow trench; removing a part of the gasket oxide layer positioned close to the top of the opening of the second shallow trench by etching; etching back the hard mark layer in order to expose the surface of the semiconductor substrate positioned close to the top of the opening of the second shallow trench; and forming silicon epitaxial layers at the bottom and on the side face of the second shallow trench and on the exposed surface of the semiconductor substrate in order to form a third shallow trench. According to the manufacturing method, the reverse narrow width effect caused by continuous reduction in the feature size of a semiconductor device can be restrained effectively, and the isolation performance of the shallow trench isolation structure is enhanced.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of sigma of having type or U-shaped fleet plough groove isolation structure semiconductor device and form the method for this fleet plough groove isolation structure.
Background technology
In semiconductor fabrication process, the shallow trench isolation formed is most important for the electric property of the last semiconductor device formed from the performance of (STI) structure.
The technique of existing formation fleet plough groove isolation structure 101 as shown in Figure 1 generally includes following step: first, on a semiconductor substrate 100 buffer layer and hard mask layer successively, the material preferred oxides of resilient coating, the material preferred nitrogen SiClx of hard mask layer; Patterned hard mask layer, to form the opening being formed the pattern of fleet plough groove isolation structure 101 in hard mask layer, this process comprises: on hard mask layer, form the photoresist layer with the pattern of fleet plough groove isolation structure 101, with described photoresist layer for mask, etching hard mask layer, until expose resilient coating, adopts cineration technics to remove described photoresist layer; With the hard mask layer of patterning for mask, etch the groove for the formation of fleet plough groove isolation structure 101 in the semiconductor substrate; At sidewall and the bottom formation backing layer 101a of described groove, its material is oxide; Depositing isolation material 101b in the trench and on hard mask layer, it typically is oxide; Perform chemical mechanical milling tech to grind isolated material 101b, until expose hard mask layer; Wet etching is adopted to remove hard mask layer and resilient coating.
Along with the continuous reduction of feature sizes of semiconductor devices, for the MOS device that channel length is less than 1 micron, there is the narrow width effect (reverse narrow widtheffect) that reverses significantly in it, namely the threshold voltage of device reduces along with the reduction of the width of the fleet plough groove isolation structure of the different active area of isolating device, and then causes the decline of device performance and reliability.The reason producing above-mentioned phenomenon is, when adopting wet etching to remove hard mask layer and resilient coating, part isolated material 101b and partial liner layer 101a is also removed substantially simultaneously, thus forms groove 102 at the top corner place of fleet plough groove isolation structure 101; Follow-up form gate dielectric and gate material layers (its constituent material comprises polysilicon or other electric conducting material) successively on a semiconductor substrate 100 after, gate material layers will filling groove 102, the gate material layers existed in described groove 102 will induce gate dielectric to produce local field effect, and then causes the reduction of threshold voltage and the rising of leakage current of device.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of fleet plough groove isolation structure, Semiconductor substrate is provided, form pad oxide layer and hard mask layer successively on the semiconductor substrate; Etch described hard mask layer, described pad oxide layer and described Semiconductor substrate successively, to form the first shallow trench; Continue sidewall and the bottom of described first shallow trench of etching, to form the second shallow trench; Etching removes the described pad oxide layer of part be positioned near described second shallow trench open top; Return the described hard mask layer of etching, to expose the described semiconductor substrate surface be positioned near described second shallow trench open top; The bottom of described second shallow trench and side, the described semiconductor substrate surface that exposes form silicon epitaxy layer, to form the 3rd shallow trench.
Preferably, be also included in while forming described silicon epitaxy layer and perform in-situ boron doping to described silicon epitaxy layer, the doping content of the described boron in described silicon epitaxy layer is 1.0 × e
17ion/cubic centimetre to 1.0 × e
20ion/cubic centimetre.
Preferably, in described 3rd shallow trench, fill the step of spacer material layer after being also included in described 3rd shallow trench of formation.
Preferably, the step performing planarization after filling described spacer material layer is also included in described 3rd shallow trench.
Preferably, after being also included in execution planarization, etching removes the step of described hard mask layer.
Preferably, described second shallow trench is ∑ type shallow trench or U-shaped shallow trench.
Preferably, described silicon epitaxy layer be germanium silicon layer, silicon layer, silicon carbide layer or the sandwich construction that is made up of germanium silicon layer, silicon layer and silicon carbide layer.
Preferably, the carbon doping ratio in described silicon carbide layer is 0.01 to 0.05, and the Ge-doped ratio in described germanium silicon layer is 0.1 to 0.5.
Preferably, the thickness range of described silicon epitaxy layer is 5nm to 10nm, and the thickness range of described pad oxide layer is 100 dust to 400 dusts.
Preferably, described spacer material layer comprises oxide skin(coating) and includes high-k dielectric, and the material of described hard mask layer is silicon nitride.
Preferably, adopt dry etch process to form described first shallow trench, adopt wet etching to remove the described pad oxide layer of part be positioned near described second shallow trench open top.
Preferably, be also included in after removing described hard mask layer and perform planarization to form the step of fleet plough groove isolation structure, the thickness of described fleet plough groove isolation structure is 0.2um to 0.33um.
The invention also discloses a kind of semiconductor device, described semiconductor device comprises the fleet plough groove isolation structure adopting said method to manufacture, and described fleet plough groove isolation structure is have the ∑ type fleet plough groove isolation structure of described silicon epitaxy layer or U-shaped fleet plough groove isolation structure.
According to the present invention, effectively can suppress the reversion narrow width effect caused by continuous reduction of feature sizes of semiconductor devices, promote the isolation performance of fleet plough groove isolation structure.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the schematic cross sectional view of the fleet plough groove isolation structure formed according to existing technique;
The schematic cross sectional view of the device that Fig. 2 A-Fig. 2 H obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 3 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention improves the technique making semiconductor device structure to solve the problems of the prior art.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below, describe method according to an exemplary embodiment of the present invention with reference to Fig. 2 A-Fig. 2 H and Fig. 3 and form the detailed step of fleet plough groove isolation structure.
With reference to Fig. 2 A-Fig. 2 H, the schematic cross sectional view of the device that the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively obtains respectively.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, the constituent material of Semiconductor substrate 200 can to adopt on unadulterated monocrystalline silicon, monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), insulator stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate 200 selects monocrystalline silicon.
Next, pad oxide layer 201 and hard mask layer 202 is formed successively on semiconductor substrate 200.Any prior art that the method forming pad oxide layer 201 and hard mask layer 202 can adopt those skilled in the art to have the knack of, preferred chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).Pad oxide layer 201 can discharge the stress between hard mask layer 202 and Semiconductor substrate 200 as resilient coating, and in the present embodiment, the material of pad oxide layer 201 is silicon dioxide, and thickness is 100 ~ 400 dusts.The material preferred nitrogen SiClx of hard mask layer 202.
Then, as shown in Figure 2 B, etch described hard mask layer 202, described pad oxide layer 201 and described Semiconductor substrate 200, to form shallow trench 203, preferably, adopt dry etch process to form described shallow trench 203.The structure of described shallow trench 203 is rectangle.
In one embodiment of this invention, hard mask layer 202 is formed dielectric anti-reflective coating (DARC), its material is silicon oxynitride, the method that chemical gas can be adopted to deposit prepares dielectric anti-reflective coating, the object of deposition formation dielectric anti-reflective coating is the reflectivity in order to reduce silicon nitride layer, and dielectric anti-reflective coating is formed the photoresist layer of bottom antireflective coating and patterning.
According to photoresist etching bottom antireflecting coating, dielectric anti-reflective coating, hard mask layer 202, pad oxide layer 201 and the Semiconductor substrate 200 successively of patterning, to form shallow trench 203.Wherein, etching gas can adopt the gas based on chlorine or the gas based on hydrogen bromide or both mists.Adopt dry etch process, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Dry etching is carried out preferably by one or more RIE step.The range of flow of etching gas can be 0 ~ 200 cc/min (sccm), and reative cell internal pressure can be 5 ~ 20 millis millimetres of mercury (mTorr).Then, remove the photoresist of patterning, bottom antireflective coating and dielectric anti-reflective coating, to form shallow trench 203, described shallow trench 203 is rectangular shallow groove structure.
Then, as shown in Figure 2 C, carry out wet etching or dry etching and form Sigma shape shallow trench or U-shaped shallow trench 204 with etching on the basis of the shallow trench 203 of rectangle.
Exemplarily, dry etch process can be adopted to form U-shaped shallow trench, such as using plasma etching, etching gas can adopt based on oxygen (O
2-based) gas.Concrete, adopt lower radio-frequency (RF) energy also can produce low pressure and highdensity plasma gas to realize dry etching.As an example, the range of flow of the etching gas of using plasma etching can be 50 cc/min (sccm) ~ 150 cc/min (sccm), and reative cell internal pressure can be 5 millitorrs (mTorr) ~ 20 millitorr (mTorr).Wherein, the etching gas of dry etching can be bromize hydrogen gas, carbon tetrafluoride gas or gas of nitrogen trifluoride, can also pass into some and add gas, as nitrogen, helium or oxygen etc.U-shaped shallow trench is formed by control etch rate and etch period.The degree of depth of U-shaped groove 204 can be determined according to the desired degree of depth.Substrate surface can be arranged essentially parallel to bottom " U " connected in star." U " connected in star sidewall can be substantially perpendicular to substrate surface.
Exemplarily, described shallow trench 203 can be etched to form " ∑ " connected in star, or from the sidewall of " U " shape shallow trench, to Semiconductor substrate, there is crystal orientation optionally wet etching.Have crystal orientation optionally wet etching be well known in the art, such as, etching speed on <111> crystal orientation can be less than the etching speed on other crystal orientation.
In a specific embodiment of the present invention, adopt wet etching " U " shape shallow trench, to form " ∑ " shape shallow trench, this wet etching will stop on <111> crystal face and <11-1> crystal face, thus formed " ∑ " connected in star, can adopt Tetramethylammonium hydroxide (TMAH), dilution hydrofluoric acid (DHF) carry out wet etching.
Then, as shown in Figure 2 D, the portions of pads oxide skin(coating) 201 be positioned near Sigma shape shallow trench or U-shaped shallow trench 204 open top of wet etching removal part is adopted, to form pad oxide layer 201 '.
Exemplarily, described wet etching has lower etching selection ratio to pad oxide layer 201, has higher etching selection ratio to hard mask layer 202 and Semiconductor substrate 200.
Wherein, carrying out the etching liquid that wet etching adopts can be acid solution, organic base or inorganic base.Exemplarily, inorganic base can be KOH, NaOH, NH
4oH etc.; Organic base can be TMAH or EDP etc.; Acid solution can be the hydrofluoric acid of dilution and hot phosphoric acid etc.
It should be noted that, the method for above-mentioned execution wet-etching technology is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, not repeat them here.
Then, as shown in Figure 2 E, pull-back technique is carried out to the hard mask layer 202 in Semiconductor substrate 200, to expose the surface of Semiconductor substrate 200, concrete, expose the top of shallow trench 204.
Exemplarily, adopt pull-back PROCESS FOR TREATMENT hard mask layer 202, flush with the sidewall of the sidewall and pad oxide layer 201 ' that make hard mask layer 202 ', or pull-back technique can be adopted to etch and to remove more hard mask layer 202, be greater than A/F in pad oxide layer 201 ' to make the A/F in hard mask layer 202 '.
The hydrofluoric acid of dilution and phosphoric acid can be adopted to perform pull-back technique, in a specific embodiment of the present invention, the hydrofluoric acid of dilution is adopted to implement pull-back technique to nitride layer, the concentration ratio of the hydrofluoric acid of dilution is 2%, the time of reaction is 1 minute, Semiconductor substrate can be immersed in hydrofluoric acid solution.
It should be noted that, the method for above-mentioned execution pull-back PROCESS FOR TREATMENT nitride layer is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, repeat them here.
Then, as shown in Figure 2 F, the top and sidewall of the surface of the Semiconductor substrate 200 exposed, Sigma shape shallow trench or U-shaped shallow trench 204 form silicon epitaxy layer 205, to form shallow trench 206.The thickness range of the silicon epitaxy layer 205 formed is 5nm to 10nm.
Meanwhile, implement in-situ doped, with in silicon epitaxy layer 205 situ doped with boron, the doping content of described boron is 1.0 × e
17ion/cubic centimetre to 1.0 × e
20ion/cubic centimetre.
One in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) that the deposition of described silicon epitaxy layer 205 can select optionally chemical vapor deposition (CVD) method, nonselective chemical vapor deposition (CVD) method physical vapor deposition (PVD) method or ald (ALD) method etc. to be formed.Preferred chemical vapor deposition (CVD) method in the present invention.
In a specific embodiment of the present invention, be SiGe layer at described silicon epitaxy layer 205, when depositing described SiGe layer, pass into unstrpped gas, such as, containing the gas GeH of Ge
4, and select H
2as carrier gas, the flow-rate ratio of wherein reacting gas and carrier gas is 0.01, selects SiH
2cl
2as reacting gas, select H
2as carrier gas, the flow-rate ratio of wherein reacting gas and carrier gas is 0.01, and the temperature of deposition is 500 ~ 950 DEG C, and be preferably 650 ~ 750 DEG C, gas pressure is 10 ~ 100Torr, is preferably 20 ~ 40Torr.
Wherein, described silicon epitaxy layer 205 can be single germanium silicon layer, single silicon layer, single silicon carbide layer or the sandwich construction be combined to form by germanium silicon layer, silicon layer and silicon carbide layer.In described silicon carbide epitaxial layers, the doping ratio of carbon is 0.01 to 0.05, and in described germanium silicon epitaxial layer, the doping ratio of germanium is 0.1 to 0.5.
Then, as shown in Figure 2 G, in shallow trench 206, fill isolated material, isolated material is generally oxide (such as HARP), has the material of high-k or the combination of the two, described in there is the material of high-k dielectric constant be generally more than 3.9.
As preferably, after fill isolated material in shallow trench 206, also comprise the step of planarization further, flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.
In execution planarisation step, after getting rid of unnecessary filling isolated material, form spacer material layer 207 in shallow trench 206, the top of spacer material layer 207 and hard mask layer 202 ' flushes.
Exemplarily, in shallow trench 206, isolated material is filled.First depositing isolation material in Semiconductor substrate 200, to fill shallow trench 206; Perform cmp again until expose hard mask layer 202, to form spacer material layer 207.
Then, as illustrated in figure 2h, wet etching removes hard mask layer 202 ', also etches the filling spacer material layer 207 removing pad oxide layer 201 ' and part, to form spacer material layer 208 in Semiconductor substrate 200 while etching removes hard mask layer 202 '.
So far, complete the processing step that method is according to an exemplary embodiment of the present invention implemented, in Semiconductor substrate 200, form the spacer material layer 208 with Sigma type epitaxial loayer or U-shaped epitaxial loayer as shown in Fig. 2 H, be formed with epitaxial loayer at the intersection of spacer material layer 208 and Semiconductor substrate 200 simultaneously.Next, the part of Semiconductor substrate 200 is exceeded by execution cmp removal spacer material layer 208 and epitaxial loayer, form fleet plough groove isolation structure (STI) in the semiconductor substrate, the thickness range 0.2um to 0.33um of the described fleet plough groove isolation structure after cmp.According to the present invention, effectively can suppress the reversion narrow width effect caused by continuous reduction of feature sizes of semiconductor devices, promote the isolation performance of fleet plough groove isolation structure.
Next, the making of whole semiconductor device can be completed by subsequent technique, comprising: implement well region and inject; Form grid structure on semiconductor substrate 200, exemplarily, grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top, the constituent material of gate dielectric comprises oxide, the constituent material of gate material layers comprise in polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide one or more, the constituent material of grid hard masking layer comprise in oxide, nitride, nitrogen oxide and amorphous carbon one or more; The side wall construction near grid structure is formed in grid structure both sides; Source/drain region etc. is formed in the Semiconductor substrate 200 of grid structure both sides.
With reference to Fig. 3, the flow chart of the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively, for schematically illustrating the flow process of whole manufacturing process.
In step 301, provide Semiconductor substrate, form pad oxide layer and hard mask layer successively on a semiconductor substrate;
In step 302, etch hard mask layer, pad oxide layer and Semiconductor substrate successively, with the first shallow trench;
In step 303, described first shallow trench of etching is continued, to form the second shallow trench;
In step 304, etching removes the described pad oxide layer being positioned at described second shallow trench near top;
In step 305, hard mask layer described in pull-back PROCESS FOR TREATMENT is adopted, to expose described semiconductor substrate surface;
Within step 306, the bottom of described second shallow trench and side, the semiconductor substrate surface that exposes form epitaxial loayer, to form the 3rd shallow trench;
In step 307, in described 3rd shallow trench, fill isolated material, then perform planarization;
In step 308, etching removes described hard mask layer.
Manufacture method according to the present invention also proposed a kind of semiconductor device, described semiconductor device comprises the fleet plough groove isolation structure adopting above-mentioned either method to manufacture, and described fleet plough groove isolation structure is have the ∑ type fleet plough groove isolation structure of described silicon epitaxy layer or U-shaped fleet plough groove isolation structure.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided, forms pad oxide layer and hard mask layer successively on the semiconductor substrate;
Etch described hard mask layer, described pad oxide layer and described Semiconductor substrate successively, to form the first shallow trench;
Continue sidewall and the bottom of described first shallow trench of etching, to form the second shallow trench;
Etching removes the described pad oxide layer of part be positioned near described second shallow trench open top;
Return the described hard mask layer of etching, to expose the described semiconductor substrate surface be positioned near described second shallow trench open top;
The bottom of described second shallow trench and side, the described semiconductor substrate surface that exposes form silicon epitaxy layer, to form the 3rd shallow trench.
2. method according to claim 1, is characterized in that, be also included in while forming described silicon epitaxy layer and perform in-situ boron doping to described silicon epitaxy layer, the doping content of the described boron in described silicon epitaxy layer is 1.0 × e
17ion/cubic centimetre to 1.0 × e
20ion/cubic centimetre.
3. method according to claim 1, is characterized in that, is also included in the step of filling spacer material layer after forming described 3rd shallow trench in described 3rd shallow trench.
4. method according to claim 3, is characterized in that, is also included in described 3rd shallow trench the step performing planarization after filling described spacer material layer.
5. method according to claim 4, is characterized in that, is also included in etching after performing planarization and removes the step of described hard mask layer.
6. method according to claim 1, is characterized in that, described second shallow trench is ∑ type shallow trench or U-shaped shallow trench.
7. method according to claim 1, is characterized in that, described silicon epitaxy layer is germanium silicon layer, silicon layer, silicon carbide layer or the sandwich construction that is made up of germanium silicon layer, silicon layer and silicon carbide layer.
8. method according to claim 7, is characterized in that, the carbon doping ratio in described silicon carbide layer is 0.01 to 0.05, and the Ge-doped ratio in described germanium silicon layer is 0.1 to 0.5.
9. method according to claim 1, is characterized in that, the thickness range of described silicon epitaxy layer is 5nm to 10nm, and the thickness range of described pad oxide layer is 100 dust to 400 dusts.
10. method according to claim 3, is characterized in that, described spacer material layer comprises oxide skin(coating) and includes high-k dielectric, and the material of described hard mask layer is silicon nitride.
11. methods according to claim 1, is characterized in that, adopt dry etch process to form described first shallow trench, adopt wet etching to remove the described pad oxide layer of part be positioned near described second shallow trench open top.
12. methods according to claim 5, is characterized in that, be also included in after removing described hard mask layer and perform planarization to form the step of fleet plough groove isolation structure, the thickness of described fleet plough groove isolation structure is 0.2um to 0.33um.
13. 1 kinds of semiconductor device, it is characterized in that, described semiconductor device comprises the fleet plough groove isolation structure adopted as the either method in claim 1-12 manufactures, and described fleet plough groove isolation structure is have the ∑ type fleet plough groove isolation structure of described silicon epitaxy layer or U-shaped fleet plough groove isolation structure.
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| CN109950148A (en) * | 2017-12-20 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
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| CN104752307B (en) | 2018-03-20 |
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