CN104124156A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN104124156A CN104124156A CN201310151399.9A CN201310151399A CN104124156A CN 104124156 A CN104124156 A CN 104124156A CN 201310151399 A CN201310151399 A CN 201310151399A CN 104124156 A CN104124156 A CN 104124156A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 153
- 238000000034 method Methods 0.000 claims description 41
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000000470 constituent Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 208000034189 Sclerosis Diseases 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000009969 flowable effect Effects 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000006701 autoxidation reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a semiconductor device manufacturing method, which comprises steps of providing a semiconductor substrate with a first region and a second region and forming a dummy gate structure on the semiconductor substrate, wherein the dummy gate structure comprises a high k dielectric layer, a high k dielectric layer protection layer and a sacrificial gate electrode layer which are sequentially stacked from the bottom up, removing the sacrificial gate electrode layer in the dummy gate structure, forming a sacrificial material layer in a trench formed in the semiconductor substrate, removing the sacrificial material layer in the second region, forming a first metal gate electrode structure in the second region, removing the sacrificial material layer in the first region, and forming a second metal gate electrode structure in the first region, wherein the first region is an NFET region, and the second region is a PFET region; or the first region is the PFET region, and the second region is the NFET region. Thus, good interface characteristics can be provided between the metal gate electrode structures respectively formed on the NFET region and the PFET region in the semiconductor substrate, the operation speed and the contact resistance of the semiconductor device are improved, and the performance of the semiconductor device is enhanced.
Description
Technical field
The present invention relates to semiconductor fabrication process, during in particular to rear grid (gate-last) technique of a kind of enforcement, remove the method for the sacrificial gate dielectric layer in dummy gate structure.
Background technology
Along with constantly reducing of feature sizes of semiconductor devices, with high k dielectric layer/metal-gate structures, replace traditional silicon oxynitride or silica medium layer/polysilicon grating structure to be regarded as solving the main or even unique method of the problem that traditional grid structure faces, the problem that traditional grid structure faces mainly comprises grid leak electricity, polysilicon loss and by the caused boron penetration of thin oxide gate silicon dielectric layer.
For having compared with for the transistor arrangement of high technology node, described high k-metal gate process is generally rear grid (gate-last) technique, its typical implementation process comprises: first, in Semiconductor substrate, form dummy gate structure, described dummy gate structure consists of boundary layer from bottom to top, high k dielectric layer, cover layer and sacrificial gate dielectric layer; Then, in the both sides of described dummy gate structure, form grid gap wall structure, remove afterwards the sacrificial gate dielectric layer in described dummy gate structure, between described grid gap wall structure, leave a groove; Then, in described groove, deposit successively workfunction layers (workfunction metal layer), barrier layer (barrier layer) and soakage layer (wetting layer); Finally carry out the filling of metal gate material, to form metal gate structure on described cover layer.
For the semiconductor device structure that forms dummy gate structure as shown in Figure 1A, in NFET district that need be in the separated substrate 100 by fleet plough groove isolation structure 101 and PFET district, form respectively and comprise the metal gate structure with different work functions metal level, therefore described in forming, the technique that, the sacrificial gate dielectric layer 103 in the dummy gate structure forming in NFET district and PFET district is removed respectively in common employing comprises the metal gate structure with different work functions metal level.Because autoxidation easily occurs sacrificial gate dielectric layer 103, for example, as shown in Figure 1B, after removal is positioned at the sacrificial gate dielectric layer 103 in NFET district, be positioned at the sidewall generation autoxidation of the sacrificial gate dielectric layer 103 in PFET district and form oxide layer 104, and follow-uply in NFET district, form metal gate structure successively, removal is arranged in the process of the sacrificial gate dielectric layer 103 in PFET district, this oxide layer 104 can not be removed, therefore, form another metal gate structure in PFET district after, interfacial characteristics variation between the metal gate structure forming respectively in NFET district and PFET district, and then affect the performance of semiconductor device.
Therefore, a kind of method need to be proposed, to address the above problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprise: the Semiconductor substrate with the firstth district and Second Region is provided, in described Semiconductor substrate, be formed with dummy gate structure, described dummy gate structure comprises the high k dielectric layer stacking gradually, protective layer and the sacrificial gate dielectric layer of described high k dielectric layer from bottom to top; Removal is arranged in the sacrificial gate dielectric layer of the dummy gate structure in described Semiconductor substrate; In the groove forming, form sacrificial material layer in described Semiconductor substrate; Removal is positioned at the sacrificial material layer on described Second Region; On described Second Region, form the first metal gate structure; Removal is positioned at the sacrificial material layer in described the firstth district, and forms the second metal gate structure in described the firstth district.
Further, adopt the combination of dry etching, wet etching or dry etching and wet etching to implement the described removal to sacrificial gate dielectric layer.
Further, the constituent material of described sacrificial material layer is the material with flowable.
Further, the processing step of described formation sacrificial material layer comprises: adopt spin coating proceeding in described Semiconductor substrate, to form described sacrificial material layer; Adopt baking process to make described sacrificial material layer sclerosis; Adopt chemical mechanical milling tech to grind described sacrificial material layer, so that the having an even surface of described Semiconductor substrate.
Further, the constituent material of described sacrificial material layer is DUO.
Further, adopt anisotropic etch process to implement the described removal to sacrificial material layer.
Further, described the first metal gate structure and described the second metal gate structure include the stacking workfunction layers forming and metal gate material layer from bottom to top.
Further, between described workfunction layers and described metal gate material layer, also comprise the stacking barrier layer forming and soakage layer from bottom to top.
Further, the workfunction layers in described the first metal gate structure and the workfunction layers in described the second metal gate structure have different work functions.
Further, described the firstth district is NFET district, and described Second Region is PFET district; Or described the firstth district is PFET district, described Second Region is NFET district.
According to the present invention, between the metal gate structure that can make to form respectively in NFET district in Semiconductor substrate and PFET district, there is good interfacial characteristics, improve the speed of service and the contact resistance of semiconductor device, thereby promote the performance of semiconductor device.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A is for adopting prior art to form the schematic cross sectional view of the device after dummy gate structure on substrate;
There is autoxidizable schematic cross sectional view for the sidewall that adopts prior art first to remove the sacrificial gate dielectric layer in the dummy gate structure in PFET district after the sacrificial gate dielectric layer in the dummy gate structure in the NFET district shown in Figure 1A in Figure 1B;
The schematic cross sectional view of the device that Fig. 2 A-Fig. 2 F obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 3 removes the flow chart of the sacrificial gate dielectric layer in dummy gate structure when method is implemented rear grid technology according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, to remove the method for the sacrificial gate dielectric layer in dummy gate structure after the enforcement that explaination the present invention proposes during grid technology.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below, with reference to Fig. 2 A-Fig. 2 F and Fig. 3, the detailed step of removing the sacrificial gate dielectric layer in dummy gate structure when method is implemented rear grid technology is according to an exemplary embodiment of the present invention described.
With reference to Fig. 2 A-Fig. 2 F, wherein show the schematic cross sectional view of the device that method is implemented successively according to an exemplary embodiment of the present invention step obtains respectively.
First, as shown in Figure 2 A, provide Semiconductor substrate 200, the constituent material of Semiconductor substrate 200 can adopt unadulterated monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc.As example, in the present embodiment, Semiconductor substrate 200 is selected single crystal silicon material.In Semiconductor substrate 200, be formed with isolation structure 201, as example, isolation structure 201 be shallow trench isolation from (STI) structure or selective oxidation silicon (LOCOS) isolation structure, isolation structure 201 is divided into NFET district and PFET district by Semiconductor substrate 200.In Semiconductor substrate 200, to be also formed with various traps (well) structure, in order simplifying, in diagram, to be omitted.
In the NFET district of Semiconductor substrate 200 and PFET district, be all formed with dummy gate structure 201 ', as example, dummy gate structure 201 ' comprises high k dielectric layer 202 and the sacrificial gate dielectric layer 203 stacking gradually from bottom to top.The material of high k dielectric layer 202 comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide, zirconia or aluminium oxide.The material of sacrificial gate dielectric layer 203 comprises polysilicon.It should be noted that, in dummy gate structure 201 ', the below of high k dielectric layer 202 can form boundary layer, and the effect that forms boundary layer is the interfacial characteristics improving between high k dielectric layer 202 and Semiconductor substrate 200, and the material of boundary layer comprises Si oxide (SiO
x); The top of high k dielectric layer 202 can form protective layer; the effect that forms protective layer is to suppress metal gate material (being generally aluminium) in the metal gate structure of follow-up formation to the diffusion in high k dielectric layer 202, and the material of protective layer comprises titanium nitride or tantalum nitride.
Because Fig. 2 A and ensuing accompanying drawing are all the device profile maps that obtain of moving towards along the sacrificial gate dielectric layer in element layout, contact etch stop layer and the interlayer dielectric layer of the side wall construction therefore, forming in the both sides of dummy gate structure 201 ' and the described side wall construction of covering forming successively in Semiconductor substrate 200 are all not shown.
Then, as shown in Figure 2 B, remove the sacrificial gate dielectric layer 203 that is arranged in the dummy gate structure 201 ' in Semiconductor substrate 200, in Semiconductor substrate 200, form groove.Adopt the combination of dry etching, wet etching or dry etching and wet etching to implement the described removal to sacrificial gate dielectric layer 203.It should be noted that, because the sacrificial gate dielectric layer 203 in NFET district and PFET district is removed simultaneously, therefore, follow-up while forming metal gate structure respectively in NFET district and PFET district, there will not be sacrificial gate dielectric layer 203 that autoxidizable phenomenon occurs, can not produce the problem that causes being respectively formed at the interfacial characteristics variation between the metal gate structure in NFET district and PFET district due to the existence of the oxide layer 104 shown in Figure 1B.
Then, as shown in Figure 2 C, in the groove forming, form sacrificial material layer 204 in Semiconductor substrate 200, the constituent material of sacrificial material layer 204 is the material with flowable, the DUO of company of preferred Applied Materials, and the composition of DUO is a kind of oxide.The processing step that forms sacrificial material layer 204 comprises: adopt spin coating proceeding in Semiconductor substrate 200, to form sacrificial material layer 205; Adopt baking process so that sacrificial material layer 205 sclerosis; Adopt chemical mechanical milling tech to grind sacrificial material layer 205, so that the having an even surface of Semiconductor substrate 200.
Then, as shown in Figure 2 D, remove and be positioned at the sacrificial material layer 204 in PFET district.The processing step of implementing described removal comprises: in Semiconductor substrate 200, form patterned photoresist layer 205, to cover the sacrificial material layer 204 being positioned in NFET district; The patterned photoresist layer 205 of take is mask, adopts anisotropic etch process to remove and is positioned at the sacrificial material layer 204 in PFET district.The preferred CLK888 of described anisotropic etched etchant.
Then, as shown in Figure 2 E, adopt cineration technics to remove after patterned photoresist layer 205, in PFET district, form the first metal gate structure 208.As example, the first metal gate structure 208 comprises the stacking workfunction layers forming 206 and metal gate material layer 207 from bottom to top, wherein, workfunction layers 206 comprises one or more layers metal or metallic compound, and its constituent material comprises titanium nitride, titanium-aluminium alloy or tungsten nitride; The material of metal gate material layer 207 comprises tungsten or aluminium.Adopt atom layer deposition process or physical gas-phase deposition to form workfunction layers 206, adopt chemical vapor deposition method or physical gas-phase deposition to form metal gate material layer 207.Then, carry out cmp to grind above-mentioned layers of material, described grinding stops when exposing sacrificial material layer 205.It should be noted that, between workfunction layers 206 and metal gate material layer 207, can adopt atom layer deposition process or physical gas-phase deposition to form the stacking barrier layer forming and soakage layer from bottom to top, wherein, the material on barrier layer comprises tantalum nitride or titanium nitride; The material of soakage layer comprises titanium or titanium-aluminium alloy.
Then, as shown in Figure 2 F, remove and be positioned at the sacrificial material layer 204 in NFET district, Bing NFET forms the second metal gate structure 208 ' in district.
Adopt anisotropic etch process to remove and be positioned at the sacrificial material layer 204 in NFET district, the preferred CLK888 of described anisotropic etched etchant.
As example, the second metal gate structure 208 ' comprises stacking another workfunction layers 206 ' and another metal gate material layer 207 ' forming from bottom to top, another workfunction layers 206 ' has different work functions from workfunction layers 206, wherein, another workfunction layers 206 ' comprises one or more layers metal or metallic compound, and its constituent material comprises titanium nitride, titanium-aluminium alloy or tungsten nitride; The material of another metal gate material layer 207 ' comprises tungsten or aluminium.Adopt atom layer deposition process or physical gas-phase deposition to form another workfunction layers 206 ', adopt chemical vapor deposition method or physical gas-phase deposition to form another metal gate material layer 207 '.Then, carry out cmp to grind above-mentioned layers of material, described grinding stops when exposing the first metal gate structure 208.It should be noted that, between another workfunction layers 206 ' and another metal gate material layer 207 ', can adopt atom layer deposition process or physical gas-phase deposition to form the stacking barrier layer forming and soakage layer from bottom to top, wherein, the material on barrier layer comprises tantalum nitride or titanium nitride; The material of soakage layer comprises titanium or titanium-aluminium alloy.
It should be noted that, for the device architecture shown in Fig. 2 C, can also carry out the method for removing the sacrificial gate dielectric layer in dummy gate structure when following process sequences realizes grid technology after the enforcement that the present invention proposes, comprise: remove and be positioned at the sacrificial material layer 204 in NFET district; In NFET district, form the second metal gate structure 208 '; Removal is positioned at the sacrificial material layer 204 in PFET district, forms the first metal gate structure 208 in Bing PFET district.
Next, can complete by subsequent technique the making of whole semiconductor device.According to the present invention, between the metal gate structure that can make to form respectively in NFET district in Semiconductor substrate and PFET district, there is good interfacial characteristics, improve the speed of service and the contact resistance of semiconductor device, thereby promote the performance of semiconductor device.
With reference to Fig. 3, wherein show the flow chart of removing the sacrificial gate dielectric layer in dummy gate structure when method is implemented rear grid technology according to an exemplary embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 301, the Semiconductor substrate with the firstth district and Second Region is provided, in Semiconductor substrate, be formed with and comprise high k dielectric layer, the protective layer of high k dielectric layer and the dummy gate structure of sacrificial gate dielectric layer stacking gradually from bottom to top, wherein, the firstth district is NFET district, and Second Region is PFET district; Or the firstth district is PFET district, Second Region is NFET district;
In step 302, remove the sacrificial gate dielectric layer that is arranged in the dummy gate structure in Semiconductor substrate;
In step 303, in the groove forming, form sacrificial material layer in Semiconductor substrate;
In step 304, remove and be positioned at the sacrificial material layer on Second Region;
In step 305, on Second Region, form the first metal gate structure;
In step 306, remove and be positioned at the sacrificial material layer in the firstth district, and in the firstth district, form the second metal gate structure.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, comprising:
The Semiconductor substrate with the firstth district and Second Region is provided, in described Semiconductor substrate, is formed with dummy gate structure, described dummy gate structure comprises the high k dielectric layer stacking gradually, protective layer and the sacrificial gate dielectric layer of described high k dielectric layer from bottom to top;
Removal is arranged in the sacrificial gate dielectric layer of the dummy gate structure in described Semiconductor substrate;
In the groove forming, form sacrificial material layer in described Semiconductor substrate;
Removal is positioned at the sacrificial material layer on described Second Region;
On described Second Region, form the first metal gate structure;
Removal is positioned at the sacrificial material layer in described the firstth district, and forms the second metal gate structure in described the firstth district.
2. method according to claim 1, is characterized in that, adopts the combination of dry etching, wet etching or dry etching and wet etching to implement the described removal to sacrificial gate dielectric layer.
3. method according to claim 1, is characterized in that, the constituent material of described sacrificial material layer is the material with flowable.
4. method according to claim 3, is characterized in that, the processing step of described formation sacrificial material layer comprises: adopt spin coating proceeding in described Semiconductor substrate, to form described sacrificial material layer; Adopt baking process to make described sacrificial material layer sclerosis; Adopt chemical mechanical milling tech to grind described sacrificial material layer, so that the having an even surface of described Semiconductor substrate.
5. method according to claim 4, is characterized in that, the constituent material of described sacrificial material layer is DUO.
6. method according to claim 1, is characterized in that, adopts anisotropic etch process to implement the described removal to sacrificial material layer.
7. method according to claim 1, is characterized in that, described the first metal gate structure and described the second metal gate structure include the stacking workfunction layers forming and metal gate material layer from bottom to top.
8. method according to claim 7, is characterized in that, also comprises the stacking barrier layer forming and soakage layer from bottom to top between described workfunction layers and described metal gate material layer.
9. method according to claim 7, is characterized in that, the workfunction layers in the workfunction layers in described the first metal gate structure and described the second metal gate structure has different work functions.
10. method according to claim 1, is characterized in that, described the firstth district is NFET district, and described Second Region is PFET district; Or described the firstth district is PFET district, described Second Region is NFET district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310151399.9A CN104124156B (en) | 2013-04-27 | 2013-04-27 | A kind of manufacture method of semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310151399.9A CN104124156B (en) | 2013-04-27 | 2013-04-27 | A kind of manufacture method of semiconductor devices |
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| CN104124156A true CN104124156A (en) | 2014-10-29 |
| CN104124156B CN104124156B (en) | 2018-02-06 |
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| CN110957257A (en) * | 2018-09-26 | 2020-04-03 | 台湾积体电路制造股份有限公司 | Semiconductor-on-insulator substrate, method of forming the same, and integrated circuit |
| WO2023000471A1 (en) * | 2021-07-19 | 2023-01-26 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing semiconductor structure |
| US11894374B2 (en) | 2021-07-19 | 2024-02-06 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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