KR20090026595A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20090026595A KR20090026595A KR1020070091687A KR20070091687A KR20090026595A KR 20090026595 A KR20090026595 A KR 20090026595A KR 1020070091687 A KR1020070091687 A KR 1020070091687A KR 20070091687 A KR20070091687 A KR 20070091687A KR 20090026595 A KR20090026595 A KR 20090026595A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- metal
- metal barrier
- barrier film
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 200
- 239000002184 metal Substances 0.000 claims abstract description 200
- 230000004888 barrier function Effects 0.000 claims abstract description 131
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 51
- 238000004544 sputter deposition Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 3
- 239000002923 metal particle Substances 0.000 claims description 36
- 229910052721 tungsten Inorganic materials 0.000 claims description 33
- 239000010937 tungsten Substances 0.000 claims description 33
- 238000005240 physical vapour deposition Methods 0.000 claims description 21
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 17
- -1 tungsten nitride Chemical class 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 9
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 241
- 239000005300 metallic glass Substances 0.000 description 10
- 238000010406 interfacial reaction Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910008807 WSiN Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A method for manufacturing a semiconductor device is disclosed. A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a gate conductive film on the gate insulating film, and applying a bias power to the semiconductor substrate to form a gate insulating film on the gate conductive film. Forming a metal barrier layer on the metal barrier layer; forming a metal layer on the metal barrier layer; and etching the gate insulating layer, the gate conductive layer, the barrier layer, and the metal layer to form a gate pattern.
Thus, according to the present invention, by forming a metal barrier film on the gate conductive film by a sputtering method while applying a bias power to the semiconductor substrate, the interface reaction between the metal film and the gate conductive film can be suppressed There is.
Description
The present invention relates to a method for manufacturing a semiconductor device.
In general, a gate of a semiconductor device has a laminated film structure of a gate insulating film made of an oxide film and a polysilicon film, and a hard mask film formed on the gate conductive film. This is because the polysilicon film satisfies physical properties required as a gate such as high melting point, ease of thin film formation, ease of line pattern, stability to an oxidizing atmosphere, and formation of a flat surface.
However, as the design rule is reduced in accordance with the recent trend of high integration of semiconductor devices, the gate to which the polysilicon film is applied has a limit in implementing low resistance in a fine line width.
Accordingly, in order to form a gate having a lower resistance, a polyside gate structure including a structure in which a metal silicide film, which is an ohmic layer, is formed on the polysilicon film, and a metal gate structure including a structure in which a metal film is formed on a polysilicon film are developed. There is a bar. In the metal gate structure, a tungsten (W) film is mainly used as the metal gate.
However, in the case of the metal gate to which the tungsten film is applied, a tungsten silicide (WSix) film is formed in a subsequent heat treatment process as the tungsten film and the polysilicon film are in direct contact with each other. Caused by stress.
In order to solve this problem, a tungsten nitride film is interposed between the tungsten film and the polysilicon film as a metal barrier film. However, when a metal barrier film is formed between the tungsten film and the polysilicon film, an interfacial reaction occurs between the tungsten nitride film and the polysilicon film to increase the interface resistance.
In order to solve the above problems, a method of forming a tungsten silicide film, a titanium film (Ti) and / or a titanium nitride film (TiN) between the tungsten nitride film and the polysilicon film has been developed.
However, when the tungsten silicide film is formed on the polysilicon film during subsequent metal gate formation, the resistance of the metal gate may be reduced, but a contact resistance problem may occur. Furthermore, the titanium film and / or the titanium nitride film Is formed on the polysilicon film, the contact resistance problem does not occur, but the grain size of the metal film formed on the tungsten nitride film is reduced due to the crystallization of the tungsten nitride film formed on the titanium film and / or the titanium nitride film. do. As a result, in subsequent formation of the metal gate, the resistance of the metal gate is increased due to the decrease in grain size of the tungsten film.
The present invention relates to a method for manufacturing a semiconductor device capable of reducing the resistance of the metal gate.
A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulating film on a semiconductor substrate, forming a gate conductive film on the gate insulating film, and sputtering while applying a bias power to the semiconductor substrate. Forming a metal barrier film on the gate conductive film by a method, forming a metal film on the metal barrier film, etching the gate insulating film, the gate conductive film, the barrier film, and the metal film to form a gate pattern. Forming a step.
Here, the gate conductive film includes a polysilicon film.
The bias power is 100 to 600 W.
The forming of the metal barrier layer may include removing the metal particles from the metal target facing the semiconductor substrate, and accelerating the metal particles toward the semiconductor substrate by the bias power.
The forming of the metal barrier layer may include forming a first metal barrier layer on the gate conductive layer and forming a second metal barrier layer on the first metal barrier layer.
The forming of the first metal barrier film may include removing first metal particles from a first metal target facing the semiconductor substrate, and accelerating the first metal particles toward the semiconductor substrate by the bias power. It includes.
The forming of the second metal barrier film may include removing the second metal particles from the second metal target facing the semiconductor substrate, and accelerating the second metal particles toward the semiconductor substrate by the bias power. It includes a step.
The second metal barrier film is in an amorphous state.
The second metal barrier film includes a small crystal size in an amorphous state.
After forming the second metal barrier film, forming the third metal barrier film.
The first metal barrier film includes at least one of a titanium film, a tungsten film, and a tungsten silicide film.
The second metal barrier film includes at least one of a titanium nitride film, a tungsten nitride film, and a tungsten silicon nitride film.
The third metal barrier film includes at least one of a tungsten nitride film and a tungsten silicon nitride film.
The metal film is formed by a physical vapor deposition (PVD) method.
The metal film includes a tungsten film.
In addition, according to another embodiment of the present invention, a method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a gate conductive film on the gate insulating film, and forming a first conductive film on the gate conductive film. Forming a metal barrier film, forming a second metal barrier film on the first metal barrier film by sputtering while applying bias power on the semiconductor substrate, and forming a metal film on the second metal barrier film. And forming a gate structure by patterning the gate insulating layer, the gate conductive layer, the first and second metal barrier layers, and the metal layer.
Here, the gate conductive film includes a polysilicon film.
The first metal barrier film is formed by a physical vapor deposition (PVD) method.
The bias power is 100 to 600 W.
The forming of the second metal barrier film includes removing the metal particles from the metal target facing the semiconductor substrate, and accelerating the metal particles toward the semiconductor substrate using the bias power. .
The second metal barrier film is in an amorphous state.
The second metal barrier film includes a small crystal size in an amorphous state.
The first metal barrier film includes at least one of a titanium film, a tungsten film, and a tungsten silicide film.
The second metal barrier film includes at least one of a titanium nitride film, a tungsten nitride film, and a tungsten silicon nitride film.
The method may further include forming the third metal barrier film between the forming of the second metal barrier film and the forming of the metal film.
The third metal barrier film includes at least one of a tungsten nitride film and a tungsten silicon nitride film.
The metal film is formed by a physical vapor deposition (PVD) method.
The metal film includes a tungsten film.
In the present invention, an amorphous metal barrier film is formed between the gate conductive film and the metal film by the sputtering method while applying the bias power. Therefore, when the metal gate is formed, a metal film having large grains can be formed. As a result, the resistance of the metal gate can be reduced, and the interfacial reaction between the metal film and the gate conductive film can be suppressed.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
According to the present invention, a metal barrier film is formed on a gate conductive film by a sputtering method while applying a bias power to a semiconductor substrate during metal gate formation.
The metal barrier film is formed on the gate conductive film by the metal particles accelerated toward the semiconductor substrate by the sputtering method while applying the bias power, and thus, between the gate conductive film and the metal film. It is possible to suppress interfacial reactions that can be caused, thereby reducing the interfacial resistance of the metal gate.
1A through 1F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Referring to FIG. 1A, a
Referring to FIG. 1B, a gate
Referring to FIG. 1C, a first
The first
In this case, some of the first metal particles bounced off the target are ionized in the course of the plasma, and when the bias power is applied to the
Referring to FIG. 1D, after forming the first
The second
Here, the second
In order to form the second
At this time, some of the second metal particles bounced off the target are ionized in the course of the plasma, and when the bias power is applied to the
The first and second
In this case, when the bias power is applied to the
As a result, the amorphous
In an embodiment, the amorphous
Referring to FIG. 1E, a
Here, after forming the second
Referring to FIG. 1F, the
Here, the present invention forms a metal barrier film on the gate conductive film by applying a bias power to the semiconductor substrate.
In this way, the bias power is applied to not only suppress the interfacial reaction that may be caused between the metal film to be subsequently formed on the gate conductive film and the gate conductive film, but also by the bias power. When the metal barrier film is amorphous to form a subsequent metal gate, a metal film with large grains can be formed. Through this, the resistance of the metal gate can be reduced.
2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.
Referring to FIG. 2A, a
Referring to FIG. 2B, a gate
Referring to FIG. 2C, a first
Referring to FIG. 2D, after the first
The second
The second
The second
In this case, a part of the metal particles bounced off the target is ionized in the course of passing the plasma, and when the bias power is applied to the
Here, the present invention can suppress the interfacial reaction with the metal film to be subsequently formed by forming the second
Referring to FIG. 2E, a
Here, after forming the second
Referring to FIG. 2F, the
Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete a semiconductor device according to another embodiment of the present invention.
In the present invention, after the first metal barrier film is formed on the gate conductive film, a bias power is applied to the semiconductor substrate to form a second metal barrier film that is part of an amorphous metal barrier film on the first metal barrier film.
This can suppress the interfacial reaction that can be caused between the metal film to be subsequently formed and the gate conductive film, and thus the same effect as the present invention can be obtained.
3A to 3C are graphs showing a crystal structure according to bias power when a titanium nitride film (TiN) is used as the metal barrier film.
3A is a graph showing a crystal structure of a titanium nitride film formed when a bias power is not applied to a semiconductor substrate, and it can be seen that the titanium nitride film to which the bias power is not applied has a crystal peak.
3B is a graph showing a crystal structure of a titanium nitride film formed when 100 W of bias power is applied to a semiconductor substrate, and the titanium nitride film formed with 100 W of bias power is relatively reduced compared to the peak shown in FIG. 3A. It can be seen that the crystal structure has a peak.
FIG. 3C is a graph showing the crystal structure of a titanium nitride film formed when the bias power is increased to 200 W and applied to the semiconductor substrate. The titanium nitride film formed with the 200 W bias power applied to the peak shown in FIG. It can be seen that the amorphous structure is relatively reduced compared to the peak.
Therefore, when the bias power is increased, the peak size gradually decreases, so that the crystal structure of the titanium nitride film is broken to change from the crystal structure to the amorphous structure.
As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
1A through 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.
3A to 3C are graphs showing the crystal structure according to the bias power.
Claims (28)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070091687A KR20090026595A (en) | 2007-09-10 | 2007-09-10 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070091687A KR20090026595A (en) | 2007-09-10 | 2007-09-10 | Method of manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20090026595A true KR20090026595A (en) | 2009-03-13 |
Family
ID=40694510
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070091687A KR20090026595A (en) | 2007-09-10 | 2007-09-10 | Method of manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20090026595A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10361194B2 (en) | 2015-10-30 | 2019-07-23 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
-
2007
- 2007-09-10 KR KR1020070091687A patent/KR20090026595A/en not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10361194B2 (en) | 2015-10-30 | 2019-07-23 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
US10872888B2 (en) | 2015-10-30 | 2020-12-22 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
US11495597B2 (en) | 2015-10-30 | 2022-11-08 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5491365A (en) | Self-aligned ion implanted transition metal contact diffusion barrier apparatus | |
US10763338B2 (en) | Silicide implants | |
KR20000034928A (en) | Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture | |
CN102956459B (en) | Semiconductor device and manufacture method thereof | |
KR100871920B1 (en) | Semiconductor device and manufacturing method thereof | |
US6103631A (en) | Method of manufacturing semiconductor device | |
KR100299386B1 (en) | Gate electrode formation method of semiconductor device | |
US6686277B1 (en) | Method of manufacturing semiconductor device | |
US7229920B2 (en) | Method of fabricating metal silicide layer | |
JP2006073846A (en) | Manufacturing method of insulated gate field effect transistor | |
KR20090026595A (en) | Method of manufacturing semiconductor device | |
US7005387B2 (en) | Method for preventing an increase in contact hole width during contact formation | |
JP2001250795A (en) | Method for fabricating semiconductor integrated circuit | |
KR100296133B1 (en) | Metal gate electrode formation method of semiconductor device | |
KR100714039B1 (en) | Method for fabrication a semiconductor device | |
KR20090032893A (en) | Method for manufacturing semiconductor device | |
JP3593804B2 (en) | Semiconductor device and manufacturing method thereof | |
KR100642917B1 (en) | Method of forming a metal line in semiconductor device | |
KR100546390B1 (en) | Method of manufacturing metal oxide semiconductor transistor using dual silicidation | |
US20220216113A1 (en) | Method for manufacturing metal oxide semiconductor transistor | |
JP2000133712A (en) | Manufacture of semiconductor device | |
KR100905780B1 (en) | Gate structure and method for manufacturing of the same | |
JP3247100B2 (en) | Method for forming electrode structure and method for manufacturing semiconductor device | |
KR100334866B1 (en) | Transistor Formation Method of Semiconductor Device | |
KR100824132B1 (en) | Method of manufacturing a semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |