KR100296133B1 - Metal gate electrode formation method of semiconductor device - Google Patents
Metal gate electrode formation method of semiconductor device Download PDFInfo
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- KR100296133B1 KR100296133B1 KR1019980025225A KR19980025225A KR100296133B1 KR 100296133 B1 KR100296133 B1 KR 100296133B1 KR 1019980025225 A KR1019980025225 A KR 1019980025225A KR 19980025225 A KR19980025225 A KR 19980025225A KR 100296133 B1 KR100296133 B1 KR 100296133B1
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 10
- 239000002184 metal Substances 0.000 title claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 title abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 24
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 16
- 239000010937 tungsten Substances 0.000 claims abstract description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 230000008021 deposition Effects 0.000 claims abstract description 9
- 238000009832 plasma treatment Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 238000006243 chemical reaction Methods 0.000 abstract description 9
- 239000007772 electrode material Substances 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 238000002844 melting Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 장치의 금속 게이트 전극 형성방법에 관한 것이며, 비저항이 낮은 텅스텐막을 게이트 전극 재료로 사용할 수 있도록 텅스텐과 주변 원소의 반응을 최소화할 수 있는 반도체 장치의 금속 게이트 전극 형성방법을 제공하는데 그 목적이 있다. 본 발명은 게이트 전극 재료로서 폴리실리콘과 더불어 녹는점이 높고 비저항이 낮은 텅스텐을 사용하고, 실리콘과 텅스텐의 반응을 막기 위한 베리어로서 Ti/TiN 막을 사용한다. 대개의 경우 게이트 형성 후에 700℃ 이상의 고온 공정이 수반되므로 Ti/TiN막만으로는 텅스텐과 실리콘의 반응을 막기 힘들며, 400℃ 이상의 온도에서 Ti와 실리콘의 반응이 일어나므로 단순한 증착만으로는 적용이 힘들기 때문에 Ti막 증착후와 TiN막 증착 도중에 산소 플라즈마(oxygen plasma) 처리를 실시한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology, and more particularly, to a method of forming a metal gate electrode of a semiconductor device. The metal gate of a semiconductor device capable of minimizing the reaction between tungsten and surrounding elements so that a low resistivity tungsten film can be used as a gate electrode material. The object is to provide a method for forming an electrode. The present invention uses tungsten with high melting point and low specific resistance as the gate electrode material, and uses a Ti / TiN film as a barrier to prevent the reaction between silicon and tungsten. In most cases, it is difficult to prevent the reaction between tungsten and silicon with Ti / TiN film alone, because the high temperature process is over 700 ℃ after the gate formation.Since Ti and silicon reaction occurs at temperatures above 400 ℃, Ti is difficult to apply. Oxygen plasma treatment is performed after the film deposition and during the TiN film deposition.
Description
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 장치의 금속 게이트 전극 형성방법에 관한 것이다.TECHNICAL FIELD The present invention relates to semiconductor technology, and more particularly, to a method of forming a metal gate electrode of a semiconductor device.
반도체 장치의 고집적화에 따라 전도 라인의 선폭이 줄어들게 되고, 이에 따라 전도 라인의 저항값이 증가하게 되어, 낮은 저항값을 유지하여 신호 전달 속도를 빠르게 유지하는 것이 고집적 반도체 장치 개발의 큰 과제가 되고 있다.As the integration of semiconductor devices increases, the line width of conduction lines decreases. Accordingly, the resistance value of conduction lines increases. Therefore, maintaining a low resistance value and maintaining a high signal transfer rate has become a big problem in the development of highly integrated semiconductor devices. .
첨부된 도면 도 1은 종래의 일반적인 트랜지스터 구조를 도시한 것으로, 도시된 종래의 트랜지스터는 그 게이트 전극 재료로서 도핑된 폴리실리콘막(13)을 사용하였다. 미설명 도면 부호 '10'은 실리콘 기판, '11'은 필드 산화막, '12'는 게이트 산화막, '14'는 측벽 스페이서, '15'는 접합층을 각각 나타낸 것이다.1 shows a conventional general transistor structure, in which the conventional transistor shown uses a doped polysilicon film 13 as its gate electrode material. Reference numeral '10' represents a silicon substrate, '11' represents a field oxide film, '12' represents a gate oxide film, '14' represents a sidewall spacer, and '15' represents a bonding layer.
이러한 종래의 트랜지스터에서 게이트 전극 재료인 도핑된 폴리실리콘막(13)은 그 자체의 저항이 너무 커서 집적화가 가속될수록 낮은 저항을 가지는 물질로의 대체할 필요성이 대두되었다. 그러나, 낮은 저항의 물질들이 게이트로 사용되기에는 많은 문제를 안고 있다. 우선 대부분의 금속이 식각이 어려운 문제를 가지고 있으며, 열적으로 주변 물질과 쉽게 반응하는 특성을 가지고 있고, 자체의 스트레스에 의해 주변층에 손상을 입히는 문제점을 가지고 있다.In such a conventional transistor, the doped polysilicon film 13, which is a gate electrode material, has its own resistance so large that there is a need to replace it with a material having a lower resistance as the integration is accelerated. However, low resistance materials have many problems to be used as gates. First of all, most metals have a problem of being difficult to etch, have a property of easily reacting thermally with surrounding materials, and have a problem of damaging the surrounding layer by their own stress.
이에 따라, 64M DRAM급의 고집적 회로를 구성하는 경우에 간혹 텅스텐 실리사이드(tungsten silicide)와 함께 폴리사이드(polycide) 구조의 게이트 전극을 적용하기도 하나, 텅스텐 실리사이드 역시 비저항이 대단히 높은 물질이므로 그 적용에 한계가 있다.Accordingly, in the case of constructing a 64M DRAM-class integrated circuit, a gate electrode having a polycide structure together with tungsten silicide is sometimes used. However, since tungsten silicide is also a material having a very high resistivity, its application is limited. There is.
본 발명은 비저항이 낮은 텅스텐막을 게이트 전극 재료로 사용할 수 있도록 텅스텐과 주변 원소의 반응을 최소화할 수 있는 반도체 장치의 금속 게이트 전극 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal gate electrode of a semiconductor device capable of minimizing a reaction between tungsten and surrounding elements so that a tungsten film having a low resistivity can be used as a gate electrode material.
도 1은 종래의 일반적인 게이트 전극의 단면 구조도.1 is a cross-sectional structural view of a conventional general gate electrode.
도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 금속 게이트 전극 형성 공정 단면도.2A to 2E are cross-sectional views of a metal gate electrode forming process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20 : 실리콘 기판 21 : 필드 산화막20 silicon substrate 21 field oxide film
22 : 게이트 산화막 23 : 폴리실리콘막22 gate oxide film 23 polysilicon film
24 : Ti막 25: TiN막24: Ti film 25: TiN film
26 : 텅스텐막 27 : ARC TiN막26: tungsten film 27: ARC TiN film
28 : 측벽 스페이서 29 : 접합층28 sidewall spacer 29 bonding layer
상기 목적을 달성하기 위하여 본 발명으로부터 제공되는 특징적인 반도체 장치의 금속 게이트 전극 형성방법은 반도체 장치의 금속 게이트 전극 형성방법에 있어서, 반도체 기판 상에 게이트 절연막을 형성하는 제1 단계; 상기 게이트 절연막 상에 폴리실리콘막을 형성하는 제2 단계; 상기 폴리실리콘막 상에 Ti막을 증착하는 제3 단계; 상기 Ti막을 산소 플라즈마 처리하는 제4 단계; 상기 Ti막 상에 제1 TiN막을 증착하되, 증착 도중 상기 제1 TiN막의 산소 플라즈마 처리를 실시하는 제5 단계; 상기 제1 TiN막 상에 텅스텐막을 형성하는 제6 단계; 및 사진 및 식각 공정을 실시하여 게이트 전극을 패터닝하는 제7 단계를 포함하여 이루어진다.In order to achieve the above object, there is provided a method of forming a metal gate electrode of a semiconductor device, the method comprising: a first step of forming a gate insulating film on a semiconductor substrate; Forming a polysilicon film on the gate insulating film; Depositing a Ti film on the polysilicon film; A fourth step of oxygen plasma treating the Ti film; Depositing a first TiN film on the Ti film, and performing an oxygen plasma treatment of the first TiN film during deposition; A sixth step of forming a tungsten film on the first TiN film; And a seventh step of patterning the gate electrode by performing a photo and etching process.
즉, 본 발명은 게이트 전극 재료로서 폴리실리콘과 더불어 녹는점이 높고 비저항이 낮은 텅스텐을 사용하고, 실리콘과 텅스텐의 반응을 막기 위한 베리어로서 Ti/TiN 막을 사용한다. 대개의 경우 게이트 형성 후에 700℃ 이상의 고온 공정이 수반되므로 Ti/TiN막만으로는 텅스텐과 실리콘의 반응을 막기 힘들며, 400℃ 이상의 온도에서 Ti와 실리콘의 반응이 일어나므로 단순한 증착만으로는 적용이 힘들기 때문에 Ti막 증착후와 TiN막 증착 도중에 산소 플라즈마(oxygen plasma) 처리를 실시한다.That is, the present invention uses tungsten with high melting point and low specific resistance as the gate electrode material, and uses a Ti / TiN film as a barrier for preventing the reaction between silicon and tungsten. In most cases, it is difficult to prevent the reaction between tungsten and silicon with Ti / TiN film alone, because the high temperature process is over 700 ℃ after the gate formation.Since Ti and silicon reaction occurs at temperatures above 400 ℃, Ti is difficult to apply. Oxygen plasma treatment is performed after the film deposition and during the TiN film deposition.
이하, 본 발명의 용이한 실시를 도모하기 위하여 본 발명의 바람직한 실시예를 소개한다.Hereinafter, preferred embodiments of the present invention will be introduced to facilitate easy implementation of the present invention.
첨부된 도면 도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 게이트 전극 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.2A to 2E illustrate a process of forming a gate electrode according to an exemplary embodiment of the present invention. Hereinafter, the process will be described with reference to the drawings.
먼저, 도 2a에 도시된 바와 같이 실리콘 기판(20) 상에 필드 산화막(21)을 형성하고, 게이트 산화막(22)을 성장시킨 다음, 전체구조 상부에 폴리실리콘막(23)을 증착한다. 이때, 폴리실리콘막(23)은 가급적 얇은 두께로 증착하여 500Å 이하의 두께를 유지하도록 한다. 또한 가급적 낮은 저항값을 가지도록 고농도로 도핑시킨다.First, as shown in FIG. 2A, a field oxide film 21 is formed on a silicon substrate 20, a gate oxide film 22 is grown, and a polysilicon film 23 is deposited on the entire structure. At this time, the polysilicon film 23 is deposited as thin as possible to maintain a thickness of less than 500Å. It is also doped at high concentrations to have as low resistance as possible.
다음으로, 도 2b에 도시된 바와 같이 물리기상증착(PVD) 장비 내에서 폴리실리콘막(23) 상부에 Ti막(24)을 100Å 이하의 두께로 증착하여 후속 공정시 실리콘과의 반응이 최소화되도록 하고, 200W 이하의 낮은 RF 및 바이어스 전원을 사용하며, 산소(O2) 플라즈마 처리를 실시한다. 이때, 바이어스는 실리콘 기판(20)을 향하도록 하여 Ti막(24)의 일부 또는 전부를 미세한 불완전 산화막으로 바뀌도록 한다.Next, as illustrated in FIG. 2B, the Ti film 24 is deposited on the polysilicon film 23 to a thickness of 100 μs or less in the physical vapor deposition (PVD) equipment to minimize the reaction with silicon during the subsequent process. Oxygen (O 2 ) plasma treatment is performed using a low RF and bias power supply of 200 W or less. At this time, the bias is directed toward the silicon substrate 20 so that part or all of the Ti film 24 is changed into a fine incomplete oxide film.
계속하여, 도 2c에 도시된 바와 같이 동일 장비 내에서 300Å 이하의 낮은 두께로 TiN막(25)을 증착한다. TiN막(25)이 원자들의 상호 확산을 막는데 불완전하여도 Ti막(24) 상부의 미세 산화막(도시되지 않음)이 이를 막아줄 수 있다. 또한 TiN막(25)의 베리어 특성을 강화하기 위하여 TiN막(25) 증착 도중에 역시 산소 플라즈마 처리를 실시한다. 이러한 Ti/TiN막(24, 25)의 산소 플라즈마 처리는 구조가 불완전한 미세한 산화막에 의하여 원자들의 확산 경로를 막거나 이미 형성된 결정립(grain)의 구조를 변화시켜 원자들의 확산 경로인 결정립계(grain boundary)를 길게 연장하는 효과를 얻는다.Subsequently, as shown in FIG. 2C, the TiN film 25 is deposited to a low thickness of 300 kPa or less in the same equipment. Even if the TiN film 25 is incomplete in preventing the interdiffusion of atoms, a fine oxide film (not shown) on the Ti film 24 may prevent it. In addition, oxygen plasma treatment is also performed during the deposition of the TiN film 25 in order to enhance the barrier property of the TiN film 25. Oxygen plasma treatment of the Ti / TiN films 24 and 25 prevents the diffusion path of atoms by a fine oxide film having an incomplete structure or changes the structure of grains that have already been formed. Get the effect of extending the long.
이어서, 도 2d에 도시된 바와 같이 역시 동일 장비 내에서 전체구조 상부에 텅스텐막(26)을 800Å 이하의 두께로 증착하고, 그 상부에 반사 방지막(ARC)인 TiN막(27)을 300Å 이하의 두께로 설정하여 증착한다. 이상의 Ti막(24)부터 ARC TiN막(27)까지의 증착은 모두 물리기상증착 장비 내에서 챔버만 이동하면서 수행되며, 특히 Ti막(24) 및 TiN막(25)의 증착 및 산소 플라즈마 처리는 동일 챔버에서 진행할 수 있다.Subsequently, as shown in FIG. 2D, a tungsten film 26 is deposited to a thickness of 800 kPa or less on the entire structure in the same equipment, and a TiN film 27, which is an anti-reflective film (ARC), is 300 kPa or less. Set to thickness and deposit. The deposition from the Ti film 24 to the ARC TiN film 27 is performed while only moving the chamber in the physical vapor deposition apparatus. In particular, the deposition and oxygen plasma treatment of the Ti film 24 and the TiN film 25 are performed. Can proceed in the same chamber.
끝으로, 도 2e에 도시된 바와 같이 사진 및 식각 공정을 실시하여 게이트 전극을 형성한다. 도면 부호 '28'은 측벽 스페이서, '29'는 접합층을 나타낸 것이다.Finally, as shown in FIG. 2E, a photo electrode and an etching process are performed to form a gate electrode. Reference numeral '28' denotes a sidewall spacer and '29' denotes a bonding layer.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
이상에서와 같이 본 발명은 게이트 전극 재료로서 텅스텐막을 사용하는 것을 가능하게 하여 게이트 전극의 선저항을 크게 감소시키는 효과가 있으며, 이로 인하여 반도체 장치의 특성 열화를 방지하는 효과가 있다. 또한 반도체 장치의 고집적화를 용이하게 하여 웨이퍼당 소자(net die)수를 증가시켜 생산 단가를 감소시키는 경제적인 효과가 있다.As described above, the present invention makes it possible to use a tungsten film as the gate electrode material, thereby greatly reducing the line resistance of the gate electrode, thereby preventing the deterioration of characteristics of the semiconductor device. In addition, there is an economic effect of facilitating high integration of semiconductor devices to increase the number of net dies per wafer, thereby reducing the production cost.
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