KR100338106B1 - Method for forming meta wiring in semiconductor device - Google Patents

Method for forming meta wiring in semiconductor device Download PDF

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Publication number
KR100338106B1
KR100338106B1 KR1019950052525A KR19950052525A KR100338106B1 KR 100338106 B1 KR100338106 B1 KR 100338106B1 KR 1019950052525 A KR1019950052525 A KR 1019950052525A KR 19950052525 A KR19950052525 A KR 19950052525A KR 100338106 B1 KR100338106 B1 KR 100338106B1
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South Korea
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film
titanium
forming
titanium film
metal wiring
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KR1019950052525A
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Korean (ko)
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KR970052303A (en
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홍상희
이원규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a metal wiring in a semiconductor device is provided to reduce contact resistance and simplify manufacturing processes by forming a barrier metal film using a single deposition and annealing processing. CONSTITUTION: An insulating layer(16) is formed on a silicon substrate(11) including a polysilicon gate electrode(14), a source region(15A) and a drain region(15B). A contact hole is formed to expose the source and drain region(15A,15B) by selectively etching the insulating layer. A titanium film is deposited and annealed at nitrogen atmosphere, thereby forming a titanium silicide layer(18C) at the interface between the titanium film and the silicon substrate, a titanium nitride layer(18A) on the surface of the titanium film and a remaining titanium film(18A). A metal wiring is then formed by depositing aluminum and patterning.

Description

반도체 소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 금속배선의 장벽 금속층을 단순공정을 통해 형성함과 동시에 콘택부에 실리 사이드막이 형성되도록하여 콘택저항을 개선할 수 있는 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device. In particular, a metal wiring of a semiconductor device capable of improving contact resistance by forming a barrier metal layer of a metal wiring through a simple process and simultaneously forming a silicide layer in a contact portion It relates to a formation method.

일반적으로, 반도체 소자의 금속배선을 형성시 들뜸현상에 의한 누설전류를 방지하기 위해 점착층으로 티타늄을 증착하고, 알루미늄이온이 실리콘 기판으로 확산되는 것을 방지하기 위해 확산방지층으로 티타늄 나이트라이드를 증착하여 금속배선의 장벽 금속층으로 사용하고 있다.In general, when forming a metal wiring of the semiconductor device to deposit a titanium to the adhesion layer to prevent the leakage current caused by the lifting phenomenon, and to prevent the diffusion of aluminum ions to the silicon substrate by depositing titanium nitride as a diffusion barrier layer It is used as a barrier metal layer for metal wiring.

제 1A 및 1B 도는 트랜지스터에 종래의 방법으로 금속배선 형성을 형성할 경우를 도시한 소자의 단면도이다.1A and 1B are cross-sectional views of devices showing the case where metal wiring formation is formed in a transistor by a conventional method.

제 1A 도를 참조하면, 일반적인 공정에 따라 실리콘 기판(1)에 필드 산화막(2)을 형성하여 액티브 영역을 확정하고, 액티브 영역상에 게이트 전극(4), 소오스 영역(5A) 및 드레인 영역(5B)을 형성하여 트랜지스터가 구성된다. 게이트 전극(4)과 실리콘 기판(1)사이에는 게이트 산화막(3)이 형성된다. 트랜지스터를 포함한 실리콘 기판(1)의 전체구조상에 절연막(6)을 형성하고, 트랜지스터를 외부와 전기적으로 연결하기 위한 금속배선공정을 위해 절연막(6)의 일부분을 식각하여 게이트 전극(4), 소오스 영역(5A) 및 드레인 영역(5B)각각에 대응되는 콘택홀(7)을 형성한다.Referring to FIG. 1A, a field oxide film 2 is formed on a silicon substrate 1 according to a general process to determine an active region, and a gate electrode 4, a source region 5A, and a drain region (on the active region) are formed. 5B) is formed to constitute a transistor. A gate oxide film 3 is formed between the gate electrode 4 and the silicon substrate 1. The insulating film 6 is formed on the entire structure of the silicon substrate 1 including the transistor, and a portion of the insulating film 6 is etched for the metal wiring process for electrically connecting the transistor to the outside, thereby forming the gate electrode 4 and the source. A contact hole 7 corresponding to each of the region 5A and the drain region 5B is formed.

제 1B 도를 참조하면, 다수의 콘택홀(7)을 포함한 절연막(6)상에 티타늄막(8) 및 티타늄 나이트라이드막(9)이 순차적으로 형성된다. 이후, 약 450℃의 온도에서 30분동안 어닐링을 실시한다. 그런데, 게이트 상부의 실리사이드의 후속공정에 의한 열적 훼손과 플라즈마 훼손을 초래하였고, 여러 공정단계에 의해 장벽 금속층이 형성된다.Referring to FIG. 1B, a titanium film 8 and a titanium nitride film 9 are sequentially formed on an insulating film 6 including a plurality of contact holes 7. Thereafter, annealing is performed at a temperature of about 450 ° C. for 30 minutes. However, thermal damage and plasma damage are caused by a subsequent process of silicide on the gate, and a barrier metal layer is formed by various process steps.

따라서, 본 발명은 금속배선의 장벽 금속층을 단순공정을 통해 형성함과 동시에 콘택부에 실리사이드막이 형성되도록하여 콘택저항을 개선할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of improving the contact resistance by forming a barrier metal layer of the metal wiring through a simple process and simultaneously forming a silicide film on the contact portion.

이러한 목적을 달성하기 위한 본 발명의 금속배선 형성방법은 트랜지스터가 형성된 실리콘 기판이 제공되고, 상기 트랜지스터를 포함한 상기 실리콘 기판의 전체구조상에 절연막을 형성하고, 상기 절연막의 일부분을 식각하여 상기 트랜지스터의 구성요소인 폴리실리콘 게이트 전극, 소오스 영역 및 드레인 영역 각각에 대응되는 콘택홀을 형성하는 단계; 상기 다수의 콘택홀을 포함한 상기 절연막상에 티타늄막을 형성하는 단계; 및 상기 티타늄막을 질소가스 분위기에서 급속 열처리한 후, 알루미늄 증착 및 패턴닝공정으로 금속배선을 형성하는 단계로 이루어지는 것을 특징으로 한다.The metallization method of the present invention for achieving the above object is provided with a silicon substrate having a transistor formed, forming an insulating film on the entire structure of the silicon substrate including the transistor, and etching a portion of the insulating film to configure the transistor Forming a contact hole corresponding to each of the element polysilicon gate electrode, the source region and the drain region; Forming a titanium film on the insulating film including the plurality of contact holes; And rapidly forming the titanium film in a nitrogen gas atmosphere, and then forming a metal wiring by aluminum deposition and patterning.

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제 2A 내지 2C 도는 본 발명의 실시예에 의한 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 트랜지스터의 단면도이다.2A to 2C are cross-sectional views of transistors for explaining a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.

제 2A 도를 참조하면, 일반적인 공정에 따라 실리콘 기판(11)에 필드 산화막(12)을 형성하여 액티브 영역을 확정하고, 액티브 영역상에 폴리실리콘 게이트 전극(14), 소오스 영역(15A) 및 드레인 영역(15B)을 형성하여 트랜지스터가 구성된다. 게이트 전극(14)과 실리콘 기판(11)사이에는 게이트 산화막(13)이 형성된다. 트랜지스터를 포함한 실리콘 기판(11)의 전체 구조상에 절연막(16)을 형성하고, 트랜지스터를 외부와 전기 적으로 연결하기 위한 금속배선공정을 위해 절연막(16)의 일부분을 식각하여 폴리실리콘 게이트 전극(14), 소오스 영역(15A) 및 드레인 영역(15B)각각에 대응되는 콘택 홀( 17)을 형성한다.Referring to FIG. 2A, a field oxide film 12 is formed on a silicon substrate 11 in accordance with a general process to determine an active region, and a polysilicon gate electrode 14, a source region 15A, and a drain are formed on the active region. The transistor is formed by forming the region 15B. A gate oxide film 13 is formed between the gate electrode 14 and the silicon substrate 11. The insulating film 16 is formed on the entire structure of the silicon substrate 11 including the transistor, and a portion of the insulating film 16 is etched for the metal wiring process for electrically connecting the transistor to the outside. ) And contact holes 17 corresponding to the source region 15A and the drain region 15B, respectively.

제 2B도는 다수의 콘택홀(17)을 포함한 절연막(16)상에 티타늄 500 내지 1000Å의 두께 즉, 일반적인 장벽 금속층의 두께정도로 증착시켜 티타늄막(18)을 형성한 것이 도시된다.FIG. 2B shows that the titanium film 18 is formed on the insulating film 16 including the plurality of contact holes 17 by depositing titanium at a thickness of 500 to 1000 즉, that is, the thickness of a general barrier metal layer.

제 2C 도는 600 내지 700℃의 온도에서 20 내지 30 초동안 질소(N2)가스 분위기에서 급속 열처리하므로 이로인하여 티타늄막(18)과 접촉된 폴리실리콘 게이트 전극(14), 소오스 영역(15A) 및 드레인 영역(15B) 각각의 표면에는 티타늄막(18)의 티타늄이온이 실리콘이온과 반응하여 티타늄 실리사이드막(18C)이 생성되고, 티타늄막(18)의 표면부는 질소가스에 의해 티타늄 나이트라이드막(18A)이 되고, 티타늄막(18)의 중간부분은 질소 및 실리콘과 미반응되어 잔여 티타늄막(18A)이 된다. 이후 알루미늄 증착공정 및 패턴닝 공정으로 금속배선이 형성된다.2C is a rapid heat treatment in a nitrogen (N 2 ) gas atmosphere at a temperature of 600 to 700 ° C. for 20 to 30 seconds, thereby resulting in the polysilicon gate electrode 14, the source region 15A and the contact with the titanium film 18. Titanium ions of the titanium film 18 react with silicon ions on the surface of each of the drain regions 15B to form a titanium silicide film 18C, and the surface of the titanium film 18 is formed of a titanium nitride film (nitrogen gas) by nitrogen gas. 18A), and the middle portion of the titanium film 18 is unreacted with nitrogen and silicon to become the remaining titanium film 18A. After that, metal wiring is formed by an aluminum deposition process and a patterning process.

상술한 바와같이 본 발명은 알루미늄 금속배선을 형성하기 전에 티타늄막을 형성하고, 질소가스 분위기에서 급속 열처리함에 의해 티타늄막을 티타늄 나이트라이트막과 잔여 티타늄막으로 되게하여 장벽 금속층이 형성되게 하고, 이때 티타늄막과 접촉된 실리콘 기판이나 폴리실리콘 패턴의 표면에 티타늄 실리사이드막이 형성된다. 즉, 티타늄막을 질소가스 분위기에서 급속 열처리함에 의해 티타늄막은 티타늄 나이트라이드막, 잔여 티타늄막 및 티타늄 실리사이드막의 3중 구조로 된다.As described above, the present invention forms a titanium film before the aluminum metal wiring is formed, and the titanium film is formed into a titanium nitrite film and a remaining titanium film by rapid heat treatment in a nitrogen gas atmosphere, thereby forming a barrier metal layer. A titanium silicide film is formed on the surface of the silicon substrate or polysilicon pattern in contact with the surface of the silicon substrate. That is, by rapidly heat-treating the titanium film in a nitrogen gas atmosphere, the titanium film has a triple structure of a titanium nitride film, a residual titanium film and a titanium silicide film.

따라서, 본 발명은 티타늄막과 티타늄 나이트라이드막으로 된 장벽 금속층을 한번의 증착공정 및 열처리공정에 의해 형성하므로 공정을 단축시켜 생산성 향상 및 생산단가를 줄일 수 있으며, 또한 장벽 금속층이 형성되는 동안에 콘택부분에 티타늄 실리사이드막이 형성되므로 콘택저항을 감소시켜 소자의 신뢰성을 향상시킬 수 있다.Therefore, the present invention forms a barrier metal layer made of a titanium film and a titanium nitride film by one deposition process and a heat treatment process, thereby shortening the process, thereby improving productivity and reducing production costs, and also making contact during the formation of the barrier metal layer. Since the titanium silicide film is formed in the portion, it is possible to reduce the contact resistance to improve the reliability of the device.

제 1A 및 1B 도는 종래 반도체 소자의 금속배선 형성 방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a metal wiring formation method of a conventional semiconductor device.

제 2A 내지 2C도는 본 발명의 실시예에 의한 반도체 소자의 금속 배선 형성방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1, 11: 실리콘 기판 2,12: 필드 산화막1, 11: silicon substrate 2, 12: field oxide film

3,13: 게이트 산화막 4,14: 게이트 전극3,13: gate oxide film 4,14: gate electrode

5A,15A 소오스 영역 5B, 15B: 드레인 영역5A, 15A source region 5B, 15B: drain region

6, 16 : 절연막 7, 17: 콘택홀6, 16: insulating film 7, 17: contact hole

8, 18; 티타늄 막 18A: 잔여 티타늄막8, 18; Titanium Film 18A: Residual Titanium Film

9,18B : 티타늄 나이트라이드막 18C: 티타늄 실리사이드막9,18B: titanium nitride film 18C: titanium silicide film

Claims (3)

반도체 소자의 금속배선 형성방법에 있어서,In the metal wiring formation method of a semiconductor element, 소정 영역에 폴리실리콘 게이트 전극, 소오스 영역 및 드레인 영역이 형성된 실리콘 기판 상부에 절연막을 형성하는 단계와,Forming an insulating film on the silicon substrate on which the polysilicon gate electrode, the source region, and the drain region are formed in a predetermined region; 상기 절연막의 소정 영역을 식각하여 상기 게이트 전극, 소오스 영역 및 드레인 영역을 각각 노출시키는 콘택홀을 형성하는 단계와,Etching a predetermined region of the insulating layer to form a contact hole exposing the gate electrode, the source region, and the drain region, respectively; 상기 다수의 콘택홀을 포함한 상기 절연막상에 티타늄막을 형성하는 단계와,Forming a titanium film on the insulating film including the plurality of contact holes; 질소 가스 분위기에서 급속 열처리 공정을 실시하여 상기 티타늄막과 상기 실리콘 기판의 접촉면에는 티타늄 실리사이드막이 형성되고, 상기 티타늄막이 표면에는 질소 가스와 티타늄막이 반응하여 티타늄 실리사이드막이 형성되며, 질소 및 실리콘과 반응하지 않는 티타늄막이 잔류하는 단계와,A rapid heat treatment process is performed in a nitrogen gas atmosphere to form a titanium silicide film on the contact surface of the titanium film and the silicon substrate, and a titanium silicide film is formed on the surface of the titanium film by reacting nitrogen gas with the titanium film. Do not leave a titanium film, 전체 구조 상부에 알루미늄을 증착한 후 패터닝 공정을 실시하여 금속배선을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Forming a metal wiring by depositing aluminum on top of the entire structure and then performing a patterning process. 제 1 항에 있어서,The method of claim 1, 상기 티타늄막은 500 내지 1000Å의 두께로 형성되는 것을 특정으로 하는 반도체 소자의 금속배선 형성방법.And the titanium film is formed to a thickness of 500 to 1000 kW. 제 1 항에 있어서,The method of claim 1, 상기 급속 열처리 공정은 600 내지 700℃의 온도에서 20 내지 30 초동안 실시되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The rapid heat treatment process is a metal wiring forming method of a semiconductor device, characterized in that carried out for 20 to 30 seconds at a temperature of 600 to 700 ℃.
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