CN102044422A - Method for forming self-aligned metallic silicide - Google Patents
Method for forming self-aligned metallic silicide Download PDFInfo
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- CN102044422A CN102044422A CN2009101973680A CN200910197368A CN102044422A CN 102044422 A CN102044422 A CN 102044422A CN 2009101973680 A CN2009101973680 A CN 2009101973680A CN 200910197368 A CN200910197368 A CN 200910197368A CN 102044422 A CN102044422 A CN 102044422A
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Abstract
The invention provides a method for forming self-aligned metallic silicide. The method is characterized by comprising the following steps: providing a semiconductor base, wherein the surface of semiconductor base is provided with at least one silicon zone; forming a first metal layer at the surface of the semiconductor base; carrying out primary rapid annealing to form a first metallic silicide layer; etching the parts, which do not react, in the first metal layer; depositing a growing layer on the first metallic silicide layer; forming a second metal layer at the surface of the semiconductor base; carrying out secondary rapid annealing to form a second metallic silicide layer; and etching the parts, which do not react, in the second metal layer. The method has the following advantages: the quick diffusion of nickel-platinum alloy in the process of annealing can be prevented, thereby preventing leakage current which is caused by the problem of bridging in the contact surface of a drain-source and the semiconductor base and greatly influences the hold capacity of the integrated circuit.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of self-aligned metal silicate.
Background technology
In semiconductor fabrication, metal silicide is widely used in source/drain contact and contacts with grid and reduce contact resistance owing to having lower resistivity and having good adhesiveness with other materials.High-melting point metal and silicon react and fuse the formation metal silicide, can form the metal silicide of low-resistivity by a step or multistep annealing process.Along with the raising of semiconductor process technology, particularly at 90nm and following technology node thereof, in order to obtain lower contact resistance, nickel and nickel platinum alloy become the main material that forms metal silicide.
Silicide autoregistration (Salicide) technology is the formation technology of the at present common metal silicide of integrated circuit manufacturing, Salicide refers to and finishes after grid etching and the source leakage injection, mode deposit layer of metal layer on polysilicon with sputter (is generally Ti, Co or Ni) carry out the quick high-temp annealing first time then, polysilicon surface and metals deposited are reacted, form metal silicide.Set according to annealing temperature, make on other insulating barrier (Nitride or Oxide) depositing metal can not with the insulating barrier reaction produce do not wish silicide, be a kind of self aligned process therefore.And then remove unwanted metal illuvium with the very strong wet etching of a kind of selectivity, stay grid and other need be the Salicide of silicide.
Shown in Figure 1A, the semiconductor-based end 100, at first be provided, be formed with a plurality of MOS transistor (being example only among Fig. 1) at described the semiconductor-based end 100, be formed with isolated area 110 between the adjacent MOS transistor, be filled with insulating material in the described isolated area 110 with a MOS transistor; Described MOS transistor comprises: be formed on the gate oxide 104 at the semiconductor-based end 100, the grid 103 that on described gate oxide 104, forms, the side wall 105 that forms in the both sides of described grid 103 and gate oxide 104, source electrode 101 that described grid 103 both sides form at semiconductor-based the end 100 and drain electrode 102.
Shown in Figure 1B, form metal level 106 on the surface at the described semiconductor-based end 100, described metal level 106 covers described source electrode 101, drain electrode 102, grid 103 and side wall 105, and the material of described metal level 106 is the nickel platinum alloy.
Shown in Fig. 1 C, to carrying out annealing process in the described semiconductor-based end 100, by annealing, described source electrode 101, drain electrode 102, grid 103 lip-deep metal level 106 materials and described source electrode 101, drain 102 and grid 103 in the silicon materials generation metal silicide layer that reacts, be respectively 101a, 102a, 103a.
Shown in Fig. 1 D, the metal level 106 that will not react by selective etch is removed afterwards, makes metal silicide layer 101a, the 102a, the 103a that form be exposed to the surface at the described semiconductor-based end 100.
Shown in Fig. 1 E, in order to form the metal silicide of low-resistivity, need carry out annealing process once more for the semiconductor-based end 100, but along with the integrated circuit characteristic size is constantly dwindled, and the too fast phenomenon of diffusion can appear in the nickel platinum alloy that adopts at present in annealing process, spreading too fast phenomenon can cause drain-source and contact-making surface of the semiconductor-based end bridge knot problem to occur and produce leakage current, have a strong impact on the integrated circuit hold capacity, further, the junction depth at the described semiconductor-based end is more and more shallow, and the silicon that causes can be used for metal silicide is fewer and feweri.
Summary of the invention
The problem that the present invention solves is to prevent that the nickel platinum alloy from the too fast phenomenon of diffusion can occur in annealing process, spreading too fast phenomenon can cause drain-source and contact-making surface of the semiconductor-based end bridge knot problem to occur and produce leakage current, have a strong impact on the integrated circuit hold capacity, further, the junction depth at the semiconductor-based end is more and more shallow, and the silicon that causes can be used for metal silicide is fewer and feweri.
The invention provides a kind of formation method of self-aligned metal silicate, comprising: the semiconductor-based end is provided, and described semiconductor-based basal surface has a silicon area at least; Surface at the semiconductor-based end forms the first metal layer; Short annealing for the first time forms first metal silicide layer; Etching is removed the part that does not react in the first metal layer; Deposition forms grown layer on first metal silicide layer; Form second metal level on the surface at the described semiconductor-based end; Short annealing for the second time forms second metal silicide layer.
Preferably, described the first metal layer account for described the first metal layer and described second metal level the metal level gross thickness 5%～20%, thickness is at 10 dusts～50 dusts.
Preferably, the material of described the first metal layer is selected from the nickel platinum alloy, and platinum shared part by weight in described nickel platinum alloy is 2%～20%.
Preferably, the thickness in described second metal level accounts for 80% to 95% of described metal level gross thickness, and thickness is at 50 dusts～200 dusts.
Preferably, the material of described second metal level is selected from the nickel metal.
Preferably, described formation the first metal layer and described second metal level all are adopted as physical vapour deposition (PVD).The carrier gas of deposition process is an argon gas, and the flow of described argon gas is 10sccm to 60sccm, and the power that the forming process of described the first metal layer and described second metal level is used is 500～5000 watts.
Preferably, described formation grown layer adopts chemical vapour deposition (CVD), selects silane as intermediate compound, and the thickness that forms grown layer is 40～160 dusts, and reaction temperature is 400 degrees centigrade to 700 degrees centigrade, and the force value of reaction chamber is that 1 holder is to 5 holders.
Preferably, 250 degrees centigrade to 450 degrees centigrade of the temperature of the described short annealing first time, the duration is 3 seconds to 5 seconds, and carrier gas is selected from a kind of in helium, argon gas, the nitrogen, and the present invention selects argon gas for use.
Preferably, 400 degrees centigrade to 650 degrees centigrade of the temperature of the described short annealing second time, the duration is 3 seconds to 30 seconds, and carrier gas is selected from a kind of in helium, argon gas, the nitrogen, and the present invention selects argon gas for use.
Owing to adopted technique scheme, compared with prior art, the present invention has the following advantages:
1, prevents that the nickel platinum alloy from the too fast phenomenon of diffusion can occur in annealing process, substep repeatedly forms metal silicide layer and makes the top diffusion of metal silicide dispersal direction towards the semiconductor-based end, avoid drain-source and contact-making surface of the semiconductor-based end bridge to occur and tie problem and produce leakage current, have a strong impact on the integrated circuit hold capacity.
2, avoided because the junction depth at the semiconductor-based end is more and more shallow, the silicon that causes can be used for metal silicide is fewer and feweri.
Description of drawings
Figure 1A to 1E is the cross-sectional view of the self-aligned metal silicate formation method of prior art;
The cross-sectional view of the self-aligned silicide formation method of Fig. 2 A to 2H one embodiment of the present of invention;
Fig. 3 is the schematic flow sheet of the self-aligned silicide formation method of one embodiment of the present of invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
The invention provides a kind of formation method of self-aligned metal silicate, comprise step: S201, the semiconductor-based end, be provided, described semiconductor-based basal surface has a silicon area at least; S202 forms the first metal layer on the surface at the semiconductor-based end; S203, short annealing for the first time forms first metal silicide layer; S204, etching is removed the part that does not react in the first metal layer; S205, deposition forms grown layer on first metal silicide layer; S206 forms second metal level on the surface at the described semiconductor-based end; S207, short annealing for the second time forms second metal silicide layer; S208, etching is removed the part that does not react in second metal level.
S201 provides the semiconductor-based end, and described semiconductor-based basal surface has a silicon area at least;
With reference to figure 2A, the semiconductor-based end 200, be provided, have a silicon area at least on surface, the described semiconductor-based ends 200.The material at the described semiconductor-based end 200 can be a kind of in monocrystalline silicon, the amorphous silicon.Be example with the semiconductor-based end 200 that includes MOS (metal-oxide-semiconductor) memory in the present embodiment, described MOS (metal-oxide-semiconductor) memory comprises source electrode 201, drain electrode 202 and grid 203; Described source electrode 201, drain electrode 202 surfaces are silicon materials, and described grid 203 surfaces are polycrystalline silicon material; Below described grid 203 grid oxic horizon 204 is arranged, the material of described grid oxic horizon 204 can be a silicon dioxide; Be formed with side wall (spacer) 205 in described grid 203 both sides, the material of described side wall can be a kind of or combination in silica, the silicon nitride; Be formed with isolated area 210 in the described semiconductor-based end, the material of isolated area 210 is a kind of or its combination in dielectric such as silica, silicon nitride, the carborundum.
S202 forms the first metal layer on the surface at the semiconductor-based end.
With reference to figure 2B, the material of the first metal layer described in the present embodiment 206 is nickel platinum alloy or Ni-Pd alloy, preferred nickel platinum alloy in the present embodiment, and the platinum element is 2%～20% at nickel platinum alloy proportion.The thickness of described the first metal layer 206 is 10～50 dusts, and the first metal layer 206 accounts for 5% to 20% of metal level gross thickness, is preferably 10% in the present embodiment.The gross thickness of described metal level can be according to source electrode 201, drain electrode 202, and grid 203 surfaces can be decided for the contact resistance of silicon that consumes and the metal silicide that will form.
The formation method of the first metal layer described in the present embodiment 206 is a physical vapour deposition (PVD).The carrier gas of deposition process is an argon gas, the flow of described argon gas be 10sccm (standard ml/min) to 60sccm, preferred argon flow amount is 30sccm in the present embodiment.The power that the forming process of described the first metal layer 206 is used is 500～5000 watts.
S203, short annealing for the first time forms first metal silicide layer;
The temperature of carrying out short annealing for the first time is 250 degrees centigrade to 450 degrees centigrade, and the duration is 3 seconds to 5 seconds, and carrier gas is selected from helium, argon gas, nitrogen, and preferred carrier gas is a nitrogen in the present embodiment.
With reference to figure 2C, by the short annealing first time, the silicon or the polycrystalline silicon material of the metal material nickel platinum alloy of described the first metal layer 206 and source electrode 201 at the semiconductor-based end 200, drain electrode 202 and grid 203 upper surfaces react, generate the first metal silicide layer 201a, 202a, 203a respectively, and silicon nitride in the side wall 205 at the described semiconductor-based end 200 or silica material do not react, this makes in follow-up processing procedure, can remove the described metal level that does not react by selective etch.
S204, etching is removed the part that does not react in the first metal layer.
With reference to figure 2D, described etching process is a wet etching, the material of present embodiment the first metal layer 206 is the nickel platinum alloy, in order effectively to remove unreacted nickel platinum alloy, the preferred etching solution of present embodiment is the mixture of sulfuric acid and hydrogenperoxide steam generator, comprises the sulfuric acid of about 50% to 80% volume, the hydrogen peroxide of about 20 to 50% volumes.After etching is removed the first metal layer 206 end, the dry then residual etching solution of removing trace of rinsing is carried out at the described semiconductor-based end 200.
S205, deposition forms grown layer on first metal silicide layer.
With reference to figure 2E, in reaction chamber, use chemical vapour deposition (CVD) on the semiconductor-based end 200, to deposit silane, silane is that intermediate compound passes through the grown layer that the reaction generation is made up of polysilicon, generates grown layer 201b, 202b, 203b respectively on the first metal silicide layer 201a, 202a, 203a.The thickness of described grown layer 201b, 202b, 203b is 40～160 dusts, and the temperature of chemical vapour deposition (CVD) is 200 degrees centigrade to 400 degrees centigrade, the flow of silane be 400sccm (standard ml/min) to 700sccm, the force value of required reaction chamber be 1 the holder to 5 the holder.The side wall (spacer) because silane only reacts with metal silicide or metal thus 205 no characterization of adsorptions can't generate.
S206 forms second metal level on the surface at the described semiconductor-based end.
With reference to figure 2F, the material of second metal level 207 described in the present embodiment is nickel platinum alloy or nickel metal, preferred nickel metal in the present embodiment.The thickness of described second metal level 207 is 50～200 dusts,
The formation method of second metal level 207 is a physical vapour deposition (PVD) described in the present embodiment.The carrier gas of deposition process is an argon gas, the flow of described argon gas be 10sccm (standard ml/min) to 60sccm, preferred argon flow amount is 30sccm in the present embodiment.The power that the forming process of described second metal level 207 is used is 500～5000 watts.
S207, short annealing for the second time forms second metal silicide layer.
The temperature of carrying out the second step short annealing is 400 degrees centigrade to 650 degrees centigrade, and the duration is 3 seconds to 30 seconds, and carrier gas is selected from helium, argon gas, nitrogen, and preferred carrier gas is a nitrogen in the present embodiment.
With reference to figure 2G, by the short annealing second time, the metal material nickel metal of described second metal level 207 and grown layer 201b, the 202b at the semiconductor-based end 200,203b take place to send out and should form the second metal silicide layer 201c, 202c, 203c, and silicon nitride in the side wall 205 at the described semiconductor-based end 200 or silica material do not react, this makes in follow-up processing procedure, can remove the described metal level that does not react by selective etch.
S208, etching is removed the part that does not react in second metal level.
With reference to figure 2H, described etching process is a wet etching, the material of present embodiment second metal level 207 is a nickel alloy, in order effectively to remove unreacted nickel metal, the preferred etching solution of present embodiment is the mixture of sulfuric acid and hydrogenperoxide steam generator, the hydrogen peroxide that comprises the sulfuric acid of about 50% to 80% volume, about 20 to 50% volumes carries out the dry then residual etching solution of removing trace of rinsing with the described semiconductor-based end 200 after etching is removed 207 end of second metal level.
To sum up, the invention provides a kind of formation method of self-aligned metal silicate.Compared with prior art, the present invention divides a plurality of stages to form two metal layers and one deck grown layer at least, make that the metal silicide dispersal direction is toward the top diffusion of the semiconductor-based end, the nickel element diffusion intrusion that has prevented central area, the semiconductor-based end causes bridge knot problem, has also avoided because the reliability that has improved device is leaked in the integrated circuit source.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. the formation method of a self-aligned metal silicate is characterized in that, comprising:
The semiconductor-based end is provided, and described semiconductor-based basal surface has a silicon area at least;
Surface at the semiconductor-based end forms the first metal layer;
Short annealing for the first time forms first metal silicide layer;
Etching is removed the part that does not react in the first metal layer;
Deposition forms grown layer on first metal silicide layer;
Form second metal level on the surface at the described semiconductor-based end;
Short annealing for the second time forms second metal silicide layer;
Etching is removed the part that does not react in second metal level.
2. the formation method of self-aligned metal silicate according to claim 1 is characterized in that: described the first metal layer account for described the first metal layer and described second metal level the metal level gross thickness 5%～20%.
3. the formation method of self-aligned metal silicate according to claim 2, it is characterized in that: the material of described the first metal layer is selected from the nickel platinum alloy, and platinum shared part by weight in described nickel platinum alloy is 2%～20%.
4. according to the formation method of the described self-aligned metal silicate of claim 2, it is characterized in that: the thickness in described second metal level accounts for 80% to 95% of described metal level gross thickness.
5. according to the formation method of claim 2 or 4 described self-aligned metal silicate, it is characterized in that: the material of described second metal level is selected from the nickel metal.
6. the formation method of self-aligned metal silicate according to claim 1, it is characterized in that: described formation the first metal layer and described second metal level all are adopted as physical vapour deposition (PVD), the carrier gas of deposition process is an argon gas, the flow of described argon gas is 10sccm to 60sccm, and the power that the forming process of described the first metal layer and described second metal level is used is 500～5000 watts.
7. the formation method of self-aligned metal silicate according to claim 1, it is characterized in that: described formation grown layer adopts chemical vapour deposition (CVD), select silane as intermediate compound, the thickness that forms grown layer is 40～160 dusts, reaction temperature is 400 degrees centigrade to 700 degrees centigrade, and the force value of reaction chamber is that 1 holder is to 5 holders.
8. the formation method of self-aligned metal silicate according to claim 1 is characterized in that: 250 degrees centigrade to 450 degrees centigrade of the temperature of the described short annealing first time, and the duration is 3 seconds to 5 seconds, carrier gas is selected from a kind of in helium, argon gas, the nitrogen.
9. the formation method of self-aligned metal silicate according to claim 1 is characterized in that: 400 degrees centigrade to 650 degrees centigrade of the temperature of the described short annealing second time, and the duration is 3 seconds to 30 seconds, carrier gas is selected from a kind of in helium, argon gas, the nitrogen.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013075349A1 (en) * | 2011-11-23 | 2013-05-30 | 中国科学院微电子研究所 | Semiconductor structure and method for manufacturing same |
| CN103137462A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
| US9478468B1 (en) | 2015-07-09 | 2016-10-25 | International Business Machines Corporation | Dual metal contact scheme for CMOS devices |
| CN109087862A (en) * | 2017-06-14 | 2018-12-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7208414B2 (en) * | 2004-09-14 | 2007-04-24 | International Business Machines Corporation | Method for enhanced uni-directional diffusion of metal and subsequent silicide formation |
| CN1889239A (en) * | 2005-06-29 | 2007-01-03 | 上海华虹Nec电子有限公司 | Method for forming Titanium silicide |
| CN101447421B (en) * | 2007-11-28 | 2010-09-22 | 中国科学院微电子研究所 | Method for preparing metal grid electrode |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013075349A1 (en) * | 2011-11-23 | 2013-05-30 | 中国科学院微电子研究所 | Semiconductor structure and method for manufacturing same |
| US9209269B2 (en) | 2011-11-23 | 2015-12-08 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor structure and method for manufacturing the same |
| CN103137462A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
| CN103137462B (en) * | 2011-11-25 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | The formation method of self-aligned metal silicate |
| US9478468B1 (en) | 2015-07-09 | 2016-10-25 | International Business Machines Corporation | Dual metal contact scheme for CMOS devices |
| CN109087862A (en) * | 2017-06-14 | 2018-12-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109087862B (en) * | 2017-06-14 | 2021-06-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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