JP5745974B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using silicon carbide and a manufacturing method thereof.

  A semiconductor device using a silicon carbide (SiC) semiconductor is superior in high voltage, large current, and high temperature operation as compared with a semiconductor device formed using a silicon (Si) semiconductor. Accordingly, semiconductor devices using silicon carbide semiconductors are being developed as next-generation power semiconductor devices.

  2. Description of the Related Art A power vertical MOSFET (Metal Oxide Field Effect Transistor) for realizing an operation under a large current has an element structure in which a large number of MOSFET unit cells (unit cells) are connected in parallel.

  In the conventional semiconductor device, in order to make contact with the source region and the p + contact region and the external output source electrode, a first contact hole (source contact hole) is formed on these regions.

  In the first contact hole, a metal silicide film for forming an ohmic contact is formed between the source region and the contact region and the external output source electrode. A second contact hole (gate contact hole) is formed on the gate electrode in order to make contact between the gate electrode made of the polycrystalline (poly) silicon film and the external output gate electrode.

  To realize a high-power semiconductor device with reduced on-resistance, contact resistance between the source region and p + contact region made of silicon carbide (SiC) and the external output source electrode is obtained by ohmic contact. It is important to lower it enough.

  Naturally, it is necessary to sufficiently reduce the contact resistance between the gate electrode of the second contact hole (gate contact hole) and the external output gate electrode.

  Conventionally, in order to obtain ohmic contact with silicon carbide, after forming a metal film, the above-described metal silicide film is formed by annealing. For example, a nickel (Ni) film is used as the metal film, and for example, a NiSi film is used as the metal silicide film.

  In order to obtain an ohmic contact having a low resistance using a metal silicide film, a high temperature annealing process of about 1000 ° C. is required. In a conventional manufacturing method for forming a contact of a semiconductor device, first, a resist opening is formed in a portion of a first contact hole (source contact hole) by photolithography. Then, using a resist as a mask, an interlayer oxide film made of a silicon oxide film or the like is etched by a reactive plasma ion etching (RIE) apparatus that generates gas plasma that reacts with the oxide film. By this RIE etching, a first contact hole that opens the interlayer oxide film and the gate oxide film is formed.

  Then, after forming a metal film such as a nickel (Ni) film in the first contact hole (source contact hole), a metal silicide film such as a NiSi film is formed by high-temperature annealing at about 1000 ° C.

  Thereafter, a second contact hole (gate contact hole) is formed by a method similar to the method for forming the first contact hole.

  Then, by forming a metal film, for example, an aluminum (Al) film in the first and second contact holes, and patterning the aluminum (Al) film by etching, an external output source electrode and an external output gate are formed. And an electrode.

  Here, the reason why the first and second contact holes are formed separately will be described.

  If the first and second contact holes are formed at the same time, the nickel (Ni) film for forming the metal silicide film is formed in the first contact hole. A film is also formed in the contact hole.

  When a high temperature annealing process at 1000 ° C. is performed in this state, nickel (Ni) diffuses into the gate electrode below the second contact hole (gate contact hole) and further reaches the insulating film below it. As a result, there is a problem that defects such as leakage to the substrate and a decrease in breakdown voltage occur. In particular, since silicon (Si) and nickel (Ni) are likely to react, when a high temperature annealing process at 1000 ° C. is performed, the surface shape becomes uneven and nickel (Ni) diffuses.

  On the other hand, in order to obtain a low-resistance ohmic contact with silicon carbide (SiC), a high-temperature annealing process at 1000 ° C. is necessary. Therefore, in the conventional manufacturing method, as described above, the first and second contact holes are separately formed, and the NiSi film (metal silicide film) is formed only on the silicon carbide (SiC).

  However, in order to form the first and second contact holes separately as in the conventional manufacturing method, it is necessary to perform the photoengraving process and the oxide film RIE etching process twice. That is, in the case of the conventional manufacturing method, the manufacturing process becomes complicated and there is a problem that the manufacturing process takes a long time.

  On the other hand, if the first and second contact holes are formed at the same time in order to reduce the number of processes, there is a problem that the metal such as nickel (Ni) as described above diffuses into the gate electrode.

  Furthermore, in a conventional silicon carbide semiconductor device, a polycrystalline silicon film (referred to as a doped polysilicon film) doped with a large amount of phosphorus (P) has been used as a gate electrode. However, the resistance of the doped polysilicon film is higher than that of the metal film, and there is a problem that the switching loss increases when the switching speed of the power vertical MOSFET is improved.

  As a prior art for solving the above problem, there is a technique according to Patent Document 1.

  In the technique according to Patent Document 1, the gate electrode has a stacked structure of a doped polysilicon film and a metal silicide film, thereby reducing the resistance of the gate electrode. Further, by utilizing the fact that the ratio of the etching rate between the metal silicide film and the interlayer insulating film, that is, the selectivity (interlayer insulating film etching rate / metal silicide film etching rate) is large, the source region and the gate electrode are formed. The contact holes are simultaneously formed in the insulating films having different thicknesses.

  Thereafter, a nickel (Ni) film is formed and subjected to high temperature annealing at 800 to 1100 ° C. to form a NiSi film on the silicon carbide (SiC). At this time, a NiSi film is formed on the gate electrode in the second contact hole. The RIE etching necessary for forming the first and second contact holes is only once.

  Therefore, in the technique according to Patent Document 1, the manufacturing cost can be suppressed and the resistance of the gate electrode can be reduced as compared with the method of separately forming the first and second contact holes.

International Publication No. 2009/19837

  In the semiconductor device related to Patent Document 1, the metal silicide film of the gate electrode is formed as follows.

That is, after doped polysilicon is patterned in the photolithography process, titanium (Ti) is deposited on the doped polysilicon film, and doped with titanium (Ti) in a low temperature annealing process at 800 ° C. or lower. The TiSi ₂ film was formed by reacting with the polysilicon film.

At this time, the TiSi ₂ film is formed on the side wall of the doped polysilicon film of the gate electrode, so that the gate length is prevented from becoming long, so that the gate electrode is doped by covering the side wall of the gate electrode with an insulating film. The side wall of the polysilicon film is protected.

Here, in the second contact hole (gate contact hole), the NiSi film exists at the interface between the TiSi ₂ film and the external output gate electrode (Al). Since the NiSi film has a larger specific resistance than a metal film such as aluminum (Al), there is a problem that the gate contact resistance is increased.

  The present invention has been made to solve these problems, and it is an object of the present invention to provide a semiconductor device and a method of manufacturing the semiconductor device in which the manufacturing cost is reduced and the resistance of the gate electrode and the gate contact is reduced.

The semiconductor device according to the present invention, a silicon carbide semiconductor substrate, formed in said silicon carbide semiconductor substrate, a first conductivity type drift layer made of silicon carbide semiconductor, selectively formed in a plurality of numbers in the drift layer surface A region that surrounds the cell placement region in which the well region is disposed in plan view, and a second conductivity type well region and a first conductivity type source region that is selectively formed on each well region surface layer. The peripheral region is formed on the drift layer via the first insulating film sandwiched between the well regions, and the drift region via the second insulating film is formed in the peripheral region. A gate electrode formed on the layer; an interlayer insulating film formed selectively covering the gate electrode; and a first metal silicide film formed over the interlayer insulating film in the cell arrangement region. An external output source electrode connected to the source region; and an external output gate electrode formed to cover the interlayer insulating film in the peripheral region and connected to the gate electrode. At least the upper layer is made of a second metal silicide film, and the bond energy between the first metal contained in the first metal silicide film and silicon is the bond between the second metal contained in the second metal silicide film and silicon. It is smaller than energy, and x is 1.5 or more and less than 2.0 in the composition MSix (M represents the second metal) of the second metal silicide film.

A method for manufacturing a semiconductor device according to the present invention includes: (a) a step of forming a drift layer of a first conductivity type made of a silicon carbide semiconductor on a silicon carbide semiconductor substrate; and (b) a step of forming a drift layer on the surface of the drift layer. A step of selectively forming a plurality of two conductivity type well regions; (c) a step of selectively forming a first conductivity type source region on the surface of the well region; and (d) the well region being disposed. A region surrounding the cell placement region in plan view is a peripheral region, and in the cell placement region, a gate electrode sandwiched between the well regions is formed on the drift layer via a first insulating film, In the peripheral region, a step of forming the gate electrode on the drift layer via a second insulating film, (e) a step of forming an interlayer insulating film covering the gate electrode, and (f) the source Region and said gate power And (g) forming a first metal in each contact hole and heat-treating the first metal, thereby forming a first metal silicide film on the source region. And (h) covering the interlayer insulating film in the cell arrangement region, covering a source electrode connected to the source region through the first metal silicide film, and covering the interlayer insulating film in the peripheral region. Forming an external output gate electrode connected to the gate electrode, wherein at least an upper layer of the gate electrode is made of a second metal silicide film, and the first metal silicide film includes the first metal silicide film. The bond energy between silicon and silicon is the bond energy between silicon and the second metal contained in the second metal silicide film. Is small, the composition MSix of the second metal silicide film (M represents the second metal), wherein the x is less than 2.0 1.5 or more.

According to the semiconductor device of the present invention, a silicon carbide semiconductor substrate, a first conductivity type drift layer made of a silicon carbide semiconductor formed on the silicon carbide semiconductor substrate, and a plurality of selectively on the drift layer surface layer. A well region of the second conductivity type formed and a source region of the first conductivity type selectively formed on each surface layer of the well region, and surrounding the cell placement region in which the well region is disposed in plan view A region is defined as a peripheral region, and in the cell arrangement region, the region is formed on the drift layer via a first insulating film sandwiched between the well regions, and in the peripheral region, a second insulating film is interposed. A gate electrode formed on the drift layer; an interlayer insulating film formed so as to selectively cover the gate electrode; and a first metal silicide layer formed over the interlayer insulating film in the cell arrangement region. An external output source electrode connected to the source region through a film; and an external output gate electrode formed to cover the interlayer insulating film in the peripheral region and connected to the gate electrode. At least the upper layer of the electrode is made of a second metal silicide film, and the bond energy between the first metal contained in the first metal silicide film and silicon is silicon with the second metal contained in the second metal silicide film. In the composition MSix (M represents the second metal) of the second metal silicide film, x is 1.5 or more and less than 2.0, thereby reducing the manufacturing cost. The resistance of the gate electrode and the gate contact can be reduced.

According to the method for manufacturing a semiconductor device of the present invention, (a) a step of forming a drift layer of a first conductivity type made of a silicon carbide semiconductor on a silicon carbide semiconductor substrate; and (b) a surface layer of the drift layer. A step of selectively forming a plurality of second conductivity type well regions; (c) a step of selectively forming a first conductivity type source region on the surface of the well region; and (d) the well region comprising: A region surrounding the arranged cell arrangement region in plan view is defined as a peripheral region, and in the cell arrangement region, a gate electrode sandwiched between the well regions is formed on the drift layer via a first insulating film. And, in the peripheral region, a step of forming the gate electrode on the drift layer via a second insulating film, (e) a step of forming an interlayer insulating film covering the gate electrode, and (f) The source region and the gate And (g) forming a first metal in each contact hole and heat-treating the first metal to form a first metal silicide on the source region. Forming a film; and (h) a source electrode that covers the interlayer insulating film in the cell arrangement region and is connected to the source region through the first metal silicide film; and the interlayer insulating film in the peripheral region And forming an external output gate electrode connected to the gate electrode, wherein at least an upper layer of the gate electrode is made of a second metal silicide film, and is included in the first metal silicide film. The bond energy between one metal and silicon is a bond energy between silicon and the second metal contained in the second metal silicide film. Is smaller than −, and in the composition MSix (M represents the second metal) of the second metal silicide film, x is 1.5 or more and less than 2.0. In addition, the resistance of the gate contact can be reduced.

3 is a top view of the silicon carbide semiconductor device in the first embodiment. FIG. 3 is a top view of the inside of the chip of the silicon carbide semiconductor device in the first embodiment. FIG. 1 is a cross sectional view of an element end surface of a silicon carbide semiconductor device in a first embodiment. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. 5 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the first embodiment. FIG. FIG. 11 is a cross sectional view on an element end face of a modification of the silicon carbide semiconductor device in the first embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view for each process showing the method for manufacturing the silicon carbide semiconductor device in the second embodiment. It is a relationship figure showing the specific resistance of a metal silicide film corresponding to the ratio of the number of atoms of silicon (Si) and a metal. It is a figure which shows the binding energy of various metals and silicon (Si).

  In the following description, regarding the conductivity type of impurities, n-type is generally defined as “first conductivity type” and p-type is defined as “second conductivity type”, but the opposite definition may be used.

<A. Embodiment 1>
<A-1. Configuration>
FIG. 1 schematically shows a top surface configuration of a silicon carbide semiconductor device as a semiconductor device according to the first embodiment, specifically, a silicon carbide MOSFET having a switching element having a MOS structure having a cell structure. It is the top view shown. In the following embodiments, a semiconductor device including silicon carbide will be described, but the present invention is not limited to the case where silicon carbide is used.

  An external output gate electrode 15 to which a gate voltage is applied from an external control circuit (not shown) is formed at the center of the upper end of one of the four side surfaces (upper drawing) of silicon carbide semiconductor device 40. Yes.

  Further, an external output source electrode 10 in which the source electrodes of the unit cells are connected in parallel is formed in a cell arrangement region 20 in which a plurality of unit cells, which are the minimum unit structure of the MOSFET, are arranged in parallel.

  A gate wiring 73 is formed around the external output source electrode 10 so as to be connected to the external output gate electrode 15. A gate voltage applied to the external output gate electrode 15 is supplied to the gate electrode (not shown) of each unit cell through the external output gate electrode 15 and the gate wiring 73.

  In normal products, electrodes for temperature sensors and current sensors are often formed on semiconductor elements, but the presence or absence of these electrodes has any effect on the effect of the element described later. is not. In addition, the position and number of the external output gate electrodes 15, the shape of the gate wiring 73, and the shape and number of the external output source electrodes 10 may have various cases depending on the MOSFET. Similar to the electrodes and the like, it does not affect the effects of the device described later.

  2 is a top view schematically showing the vicinity of the outermost surface inside the silicon carbide of the silicon carbide MOSFET according to the first embodiment, and is a top view in the vicinity of the A-A ′ line in FIG. 1.

  A cell arrangement region 20 in which a plurality of unit cells, which are the minimum unit structure of the MOSFET, are arranged in parallel, and a peripheral region 21 (external output gate electrode region).

  Here, the cell arrangement region 20 is a region where a plurality of transistor cells (vertical MOSFET unit cells) are arranged in a matrix. In the unit cell, the source region 3 and further the base region 4 are formed surrounding the p + contact region 5 in plan view, and the source contact hole 12 is formed so as to surround the region where the p + contact region 5 is formed. ing.

  On the other hand, the peripheral region 21 is a region where a transistor cell is not formed. A plurality of gate contact holes 13 are arranged and formed.

  In FIG. 2, in the cell arrangement region 20, the transistor cells are arranged by 3 × 3 on the left and right and up and down in the drawing. However, the arrangement is not limited to this, and more transistor cells are actually arranged.

3 is a cross-sectional view taken along the line BB ′ of FIG. As shown in FIGS. 2 and 3, the silicon carbide MOSFET includes a first conductivity type silicon carbide (SiC) semiconductor substrate 1 and a first conductivity type drift layer 2 formed on the silicon carbide (SiC) semiconductor substrate 1. A base region 4 as a second conductivity type well region selectively formed on the surface layer of the drift layer 2, a first conductivity type source region 3 selectively formed on the surface layer of the base region 4, and a source P + contact region 5 formed in region 3, gate oxide film 6 as a first insulating film selectively formed on drift layer 2, and second region formed on drift layer 2 in peripheral region 21. An oxide film 14 as an insulating film, a gate electrode formed on the gate oxide film 6 across the drift layer 2 and the base region 4 in the cell arrangement region 20, and formed on the oxide film 14 in the peripheral region 21. A junction field effect transistor (JFET) region 16 surrounded by the base region 4, an interlayer insulating film 8 formed so as to cover the gate electrode 7, and a cell placement region 20 formed on the interlayer insulating film 8; An external output source electrode 10 connected to a part of the p + contact region 5 and the source region 3 through a NiSi ₂ film 18 as a single metal silicide film, and a gate electrode formed on the interlayer insulating film 8 in the peripheral region 21 7, an external output gate electrode 15 connected to 7, a drain electrode 9 formed on the lower surface of the silicon carbide (SiC) semiconductor substrate 1, and a back connection electrode 11 formed on the lower surface of the drain electrode 9.

Here, the region where the external output source electrode 10 and the p + contact region 5 are connected via the NiSi ₂ film 18 is the source contact hole 12, and the region where the external output gate electrode 15 and the gate electrode 7 are connected is the gate. Contact hole 13 is used. A configuration including the gate oxide film 6 and the oxide film 14 is referred to as an “insulating film”.

  The silicon carbide (SiC) semiconductor substrate 1 is, for example, a high-concentration n-type (hereinafter sometimes simply referred to as n +) semiconductor substrate. Silicon carbide (SiC) semiconductor substrate 1 is a semiconductor substrate made of silicon carbide and having a wider band gap than silicon. In the present embodiment, the n-type is the first conductivity type.

  On silicon carbide (SiC) semiconductor substrate 1, drift layer 2, which is a low concentration n-type (hereinafter sometimes simply referred to as n−) semiconductor layer, is formed. Drift layer 2 is formed, for example, by epitaxial growth on silicon carbide (SiC) semiconductor substrate 1.

  Focusing on the cell arrangement region 20, predetermined regions in the surface of the drift layer 2 include an n + -type source region 3 (current output region), a p-type base region 4 (well region), and a high concentration. A p-type (sometimes simply referred to as p +) p + contact region 5 is formed. Here, in the present embodiment, the p-type is the second conductivity type.

  The p-type base region 4 is selectively formed in the surface of the drift layer 2 and surrounds the source region 3 in plan view. The depth from the surface of the base region 4 is formed deeper than the depth from the surface of the source region 3.

  The n + type source region 3 is selectively formed in the surface of the base region 4 and surrounds the p + contact region 5 in plan view. Specifically, p + contact region 5 is formed in the center of source region 3 in plan view. The p + contact region 5 is provided to make electrical contact between the external output source electrode 10 and the p-type base region 4.

  In the cell arrangement region 20, the gate oxide film 6 is selectively formed on the drift layer 2. In the peripheral region 21, an oxide film 14 thicker than the gate oxide film 6 is formed on the drift layer 2.

  Further, a doped polysilicon film 71 and a second metal silicide formed on the doped polysilicon film 71 are formed on the gate oxide film 6 and the oxide film 14 (which can be grasped as the above-described insulating film). A gate electrode 7 made of a laminated film with tungsten silicide (WSix film 72) as a film is formed. That is, the gate electrode 7 extends from the cell arrangement region 20 to the periphery as shown in FIG.

In the first embodiment, the composition of the WSix film 72 constituting the gate electrode 7 is formed such that tungsten (W) as the second metal is larger than the chemical equivalent WSi ₂ of WSi. That is, the value of x is, for example, 1.95.

  Hereinafter, for the sake of simplicity, a region composed of the source region 3 and the p + contact region 5 may be referred to as SiC regions 3 to 5.

An interlayer insulating film 8 made of, for example, an oxide film (SiO ₂ ) is formed so as to cover the gate electrode 7. In the cell arrangement region 20, a source contact hole 12 is opened to make contact between the SiC regions 3 to 5 and the external output source electrode 10. On the other hand, in the peripheral region 21, a gate contact hole 13 is opened to make contact between the gate electrode 7 and the external output gate electrode 15.

  In the cell arrangement region 20, an external output source electrode 10 made of, for example, an aluminum (Al) film is formed on the interlayer insulating film 8 so as to fill the source contact hole 12.

The source contact hole 12 inside, between the external output source electrode 10 and the n + -type source region 3 and the p + contact region 5, NiSi ₂ film 18 made of NiSi ₂ (first metal silicide layer) is formed .

  The external output source electrode 10 is electrically connected to the n + type source region 3 and the p + contact region 5 in the source contact hole 12.

  In contrast, an external output gate electrode 15 made of, for example, an aluminum (Al) film is formed on the interlayer insulating film 8 so as to fill the gate contact hole 13 in the peripheral region 21. The external output gate electrode 15 is electrically connected to the gate electrode 7 in the gate contact hole 13.

On the back surface of the silicon carbide (SiC) semiconductor substrate 1, a drain electrode 9 having a laminated structure made of a metal film and a metal silicide film is formed (in FIG. 3, it is illustrated as a single layer structure for simplification). ing). In the first embodiment, the metal film of the drain electrode 9 is a nickel (Ni) film, and the metal silicide film of the drain electrode 9 is a NiSi ₂ film.

  On the drain electrode 9 (on the lower side in FIG. 3), a back connection electrode 11 made of, for example, a Ni / Au laminated film is formed (in FIG. 3, it is illustrated as a single layer structure for the sake of simplicity). ing).

  Even if a high voltage is applied between the external output source electrode 10 and the back surface connection electrode 11, if no voltage is applied to the gate electrode 7, no channel is formed in the base region 4 immediately below the gate electrode 7. . That is, in the voltage application situation, the MOSFET is in an off state where electrons do not flow.

  In contrast, a high voltage is applied between the external output source electrode 10 and the back surface connection electrode 11, and a positive voltage is further applied to the gate electrode 7. Then, a channel is formed above the base region 4, and electrons flow from the source region 3 through the channel region (base region 4), the drift layer 2, the silicon carbide (SiC) semiconductor substrate 1, and the drain electrode 9. That is, in the voltage application situation, the MOSFET is turned on so that electrons flow. Thus, the on / off state of the current can be controlled by the gate voltage applied to the gate electrode 7.

<A-2. Manufacturing method>
Next, the manufacturing method of the semiconductor device according to the first embodiment will be described with reference to cross-sectional views according to processes shown in FIGS.

  First, a process until the structure of FIG. 4 is formed is demonstrated. For example, n type drift layer 2 is formed on n + type silicon carbide (SiC) semiconductor substrate 1 by epitaxial growth on silicon carbide (SiC) semiconductor substrate 1. The drift layer 2 is a semiconductor layer made of silicon carbide (SiC).

  In the cell arrangement region 20, a p-type base region 4 is selectively formed in the surface of the drift layer 2. Further, in the surface of the base region 4, an n + type source region 3 and a p + contact region 5 which is a p type base contact region are selectively formed.

  Here, the n-type region is formed by implanting, for example, nitrogen (N) ions, and the p-type region is formed by implanting, for example, aluminum (Al) ions. The n-type region and the p-type region are activated by performing high-temperature annealing at 1500 ° C. or higher.

Next, an oxide film (SiO ₂ ) having a thickness of about 1 μm is formed on the drift layer 2 by, eg, CVD (Chemical Vapor Deposition). Thereafter, the oxide film on the cell arrangement region 20 side is removed by photolithography and etching. As a result, an oxide film 14 is formed on the drift layer 2 in the peripheral region 21.

After that, as shown in FIG. 5, the upper portions of the SiC regions 2 to 5 in the cell arrangement region 20 are oxidized at a temperature of about 1000 ° C. in an atmosphere containing oxygen and water vapor. Thereby, a gate oxide film 6 of a thermal oxide film (SiO ₂ ) is formed on the SiC regions 2 to 5 in the cell arrangement region 20. The thickness of the gate oxide film is, for example, 50 nm. The step of forming the oxide film 14 and the gate oxide film 6 is a step of forming an “insulating film” on the upper surface of the drift layer 2 in the cell arrangement region 20 and the peripheral region 21.

  In the present embodiment, the gate oxide film 6 is described as a thermal oxide film, but the present invention is not limited to this. The gate oxide film 6 may be an oxide film formed by a CVD method or a laminated film of an oxide film formed by a CVD method with a thermal oxide film.

Next, a doped polysilicon film 71 constituting a gate electrode is formed on the gate oxide film 6 and the oxide film 14 by a CVD method. Further, while maintaining the cleanliness of the surface, that is, after removing the natural oxide film (SiO ₂ ) formed on the doped polysilicon film 71 with diluted hydrofluoric acid (HF), the doped polysilicon is formed by sputtering. On the film 71, a WSix film 72 as a second metal silicide film that forms a gate electrode is formed. A gate electrode 7 is constituted by a laminated film of the doped polysilicon film 71 and the WSix film 72.

  Here, x representing the composition of the WSix film 72 is, for example, 1.95. The composition of WSix can be adjusted by changing the mixing ratio of tungsten (W) and silicon (Si) in the target of the sputtering apparatus. The doped polysilicon film 71 has a thickness of 200 nm, the WSix film 72 has a thickness of 400 nm, and the WSix film 72 has a large thickness.

  Through the above steps, the structure shown in FIG. 5 is formed.

  Next, photolithography and etching are performed on the gate electrode 7. Thereby, as shown in FIG. 6, the gate electrode 7 existing above the source region 3 and the p + contact region 5 is removed, and the gate electrode 7 is formed in the base region 4, the JFET region 16 and the periphery.

  Next, an oxide film having a thickness of 1 μm is formed on the entire surface of the substrate by a CVD method to form an interlayer insulating film 8 (see FIG. 7). Subsequently, as shown in FIG. 8, the source contact hole 12 is formed in a part of the source region 3 of the cell arrangement region 20 and the upper portion of the p + contact region 5 by photolithography and RIE (Reactive Ion Etching) etching. Gate contact holes 13 are respectively formed on the gate electrode 7 in the peripheral region 21.

  The source contact hole 12 and the gate contact hole 13 are formed simultaneously. By this etching, a part of the source region 4 and the p + contact region 5 are exposed from the bottom surface of the source contact hole 12. Further, the gate electrode 7 is exposed from the bottom surface of the gate contact hole 13.

  The source contact hole 12 and the gate contact hole 13 need to be surely opened. For this reason, in the first embodiment, the etching including the over-etching process is performed in a time longer than 1.2 times the etching time required to open the source contact hole 12 and the gate contact hole 13.

  Note that over-etching is performed to completely open the source contact hole 12 and the gate contact hole 13. In order to prevent the base region 4, the source region 3, and the WSix film 72 from disappearing due to this overetching, the etching rate of the interlayer insulating film 8 and the gate oxide film 6 is changed to the silicon carbide (SiC) and the WSix film constituting the SiC regions 3 to 5. The etching rate is sufficiently larger than the etching rate of 72.

  Next, as shown in FIG. 9, a nickel (Ni) film 17 that is a first metal film is formed on the entire surface of the substrate. Further, the nickel (Ni) film 17 is formed by, for example, a sputtering method. The film thickness of the nickel (Ni) film 17 is, for example, about 50 nm.

Thereafter, a first annealing process is performed on the structure shown in FIG. Thus, as shown in FIG. 10, the first metal silicide film (NiSi ₂ film 18 in the first embodiment) is formed on the source region 3 and p + contact region 5 exposed from the bottom surface of the source contact hole 12. Form. The first annealing treatment is performed at a temperature of 300 to 800 ° C. by, for example, an RTA (Rapid Thermal Annealing) method. By heating at the temperature, nickel (Ni) of the nickel (Ni) film 17 reacts with silicon carbide (SiC) constituting the SiC regions 3 to 5 in contact therewith to form the NiSi ₂ film 18.

After the NiSi ₂ film 18 as the first metal silicide film is formed, the structure in which the NiSi ₂ film 18 is formed is cleaned with an acid chemical solution containing sulfuric acid or hydrochloric acid, for example. By the cleaning, the nickel (Ni) film 17 which has not been reacted in the silicidation reaction is removed. FIG. 11 shows the state after the unreacted nickel (Ni) film 17 is removed. Since the NiSi ₂ film is not formed on the WSix film 72, the gate contact hole 13 has no NiSi ₂ film.

  Thereafter, drain electrode 9 is formed on the back surface of silicon carbide (SiC) semiconductor substrate 1 (see FIG. 12). The drain electrode 9 is formed by the following procedure.

  First, a sputtering method is performed on the back surface of the silicon carbide (SiC) semiconductor substrate 1 to form a nickel (Ni) film having a thickness of 300 nm. Next, for example, a second annealing process at about 1000 ° C. is performed by the RTA method.

  As described above, in the first embodiment, after the unreacted nickel (Ni) film 17 is removed, the second annealing process that is higher than the temperature of the first annealing process (300 to 800 ° C.) is performed. Do. For reasons to be described later, it is preferable that the second annealing time is short. In the first embodiment, it is performed in 30 seconds.

Thereby, the contact resistance of the NiSi ₂ film 18 in the source contact hole 12 can be further reduced. Further, the nickel (Ni) film formed on the back surface of the silicon carbide (SiC) semiconductor substrate 1 reacts with the back surface of the silicon carbide (SiC) semiconductor substrate 1 to form a NiSi ₂ film at the same time. Low resistance ohmic contact is realized. Thus, a drain electrode 9 made of a nickel (Ni) film and a NiSi ₂ film is formed on the back surface of the silicon carbide (SiC) semiconductor substrate 1 (see FIG. 12).

  Next, an electrode film is formed on the interlayer insulating film 8 so as to fill the source contact hole 12 and the gate contact hole 13. As the electrode film, for example, an aluminum (Al) film having a film thickness of 3 μm can be adopted, and formed by, for example, a sputtering method.

  Thereafter, photolithography and etching are performed on the electrode film. Thereby, the electrode film is patterned, and the external output source electrode 10 and the external output gate electrode 15 are formed as shown in FIG. Here, the external output source electrode 10 and the external output gate electrode 15 are electrically separated by the patterning.

The external output source electrode 10 is formed in the cell arrangement region 20 and is electrically connected to the upper portion of the source region 3 and the upper portion of the p + contact region 5 through the NiSi ₂ film 18. In contrast, the external output gate electrode 15 is formed in the peripheral region 21 and is electrically connected to the gate electrode 7.

  Finally, as shown in FIG. 14, the back connection electrode 11 is formed on the drain electrode 9 by sputtering or the like. For example, a gold (Au) film having a thickness of 150 nm can be used as the back connection electrode 11.

As described above, in the silicon carbide semiconductor device according to the first embodiment, the NiSi ₂ film 18 as the first metal silicide film is formed in the source contact hole 12, and the silicon (Si ), A WSix film 72 (x = 1.95) is used as the second metal silicide film having a higher tungsten (W) content.

Further, the bond energy between silicon (Si) and nickel (Ni) as the first metal is smaller than the bond energy between silicon (Si) and tungsten (W) as the second metal. Therefore, even when the source contact hole 12 and the gate contact hole 13 are opened at the same time and nickel (Ni) is formed in the process after the hole opening (see FIG. 9), the NiSi ₂ film is formed on the WSix film 72. There is no. Therefore, the resistance of gate electrode 7 and the gate contact resistance can be reduced, and a silicon carbide semiconductor device with reduced manufacturing costs can be obtained.

Hereinafter, the reason why the NiSi ₂ film is not formed on the WSix film 72 will be described.

FIG. 31 shows binding energies between various metals and silicon (Si). As shown in FIG. 31, since the binding energy (0.89 eV) of nickel (Ni) to silicon (Si) is smaller than the binding energy (0.96 eV) of tungsten (W) to silicon (Si), holes Nickel (Ni) deposited on the WSix film 72 in the process after the opening does not dissociate silicon (Si) from tungsten (W), and a NiSi ₂ film is not formed.

Further, x representing the composition of the WSix film 72 is, for example, 1.95, and the WSix film 72 is a film in which tungsten (W) atoms are excessively present with respect to silicon (Si) atoms. Therefore, since there are no silicon (Si) atoms that are not bonded to tungsten (W), nickel (Ni) deposited on the WSix film 72 is bonded to excess silicon (Si) in the WSix and NiSi _2. No film is formed.

For the above two reasons, a NiSi ₂ film having a higher resistivity than aluminum (Al) is not formed in the gate contact hole 13, so that an increase in gate contact resistance can be suppressed.

  Next, the composition of WSix will be described. FIG. 30 is a relationship diagram showing the relationship between the silicide composition and the specific resistance.

  The metal silicide film is deposited on the doped polysilicon film, and the specific resistance is a value obtained by synthesizing both silicide and polysilicon resistances. The horizontal axis represents the ratio of the number of atoms between silicon (Si) and metal, and the specific resistance represents a value after heat treatment at 1000 ° C. for 20 minutes. The vertical axis represents the resistivity (μΩcm). In FIG. 30, in addition to the value of WSix (solid line), the value of TiSix is also shown (the left vertical axis corresponds to WSix and the right vertical axis corresponds to TiSix).

  From FIG. 30, it can be seen that the specific resistance of WSix (solid line) is small when the value of x is approximately 1.5 to 2.3, but the specific resistance increases at other values of x.

  In general, the specific resistance of metal silicide is minimized when the value of x is approximately 1 to 3.0, and the specific resistance is substantially constant in this range. Outside this range, even if the value of x is large (excess silicon) or small (excess metal), the specific resistance increases (see TiSix (dotted line) in FIG. 30).

  In view of this point, it is desirable that the composition of the metal silicide film has a value of x of 1.5 or more from the viewpoint of low resistance. Further, as described above, the value of x needs to be less than 2.0 in order to realize a film state in which the metal is excessive. In the first embodiment, the value of x is set to 1.95 from the viewpoint of variation in composition at the time of manufacturing the sputtering method or the CVD method.

In Patent Document 1, there is a problem that a NiSi film is formed between the gate electrode 7 and the external output gate electrode 15 to increase the gate contact resistance. This is because titanium silicide is formed on the gate electrode by depositing Ti as the first metal on the doped polysilicon film (under the gate electrode) and reacting with the doped polysilicon film by heat treatment. This is because the silicide film (TiSi ₂ film) is used.

Since silicon (Si) atoms easily diffuse in the TiSi ₂ film, nickel (Ni) is deposited on the source contact portion and reacted with silicon carbide (SiC) to form a NiSi film during the annealing process. It is inevitable that silicon (Si) of the polysilicon film diffuses into the TiSi ₂ film and reacts with nickel (Ni) deposited on the gate contact portion to form a NiSi film. This is called the thinning effect.

Since the TiSi ₂ film is a film in which Ti does not exist excessively, it cannot prevent silicon (Si) of the doped polysilicon film from diffusing up to the surface of the TiSi ₂ film.

<A-3. Modification>
In the first embodiment, nickel (Ni) is shown as the metal used as the first metal silicide. However, the first metal silicide is not limited to the one using nickel (Ni), and silicon carbide (SiC). And the bonding energy with silicon (Si) should be smaller than the bonding energy between the metal constituting the second metal silicide and silicon (Si).

  For example, platinum (Pt) can be set as the metal used for the first metal silicide, and cobalt (Co) can be set as the metal used for the second metal silicide.

  The composition constituting the second metal silicide needs to have an excess of metal in comparison with the chemical equivalent of the metal and silicon (Si).

  Furthermore, it is preferable that the second annealing process in the step of forming the drain electrode 9 on the back surface of the silicon carbide (SiC) semiconductor substrate 1 is short as described above. This is because when the time of the second annealing process becomes longer, silicon (Si) atoms in the doped polysilicon film 71 diffuse into, for example, WSix of the WSix film 72, and silicon (Si) atoms become tungsten (W) atoms. It is because it will be in an excessive state compared with.

  In order to avoid this phenomenon, the WSix film 72 can be formed thicker than the doped polysilicon film 71 so that silicon (Si) atoms do not diffuse to the surface of the WSix film 72.

  Further, there is no problem even if a doped polysilicon film is not used for the gate electrode. As shown in FIG. 15, a MOSFET including a gate electrode 74 made only of WSix (second metal silicide film) may be manufactured.

  In the structure of FIG. 15, if the threshold voltage (Vth) of the MOSFET is adjusted, the resistance of the gate electrode can be further reduced as compared with the two-layer gate electrode 7 of the first embodiment.

Also in this modified example, the value of x of WSix of the gate electrode 74 is 1.95, and since tungsten (W) is excessive, the NiSi ₂ film is not formed in the gate contact hole 13 and the gate contact resistance is reduced. In addition, the manufacturing cost can be reduced.

<A-4. Effect>
According to the embodiment of the present invention, a semiconductor device is selectively used as a first conductivity type semiconductor substrate 1, a first conductivity type drift layer 2 formed on the semiconductor substrate 1, and a drift layer 2 surface layer. A plurality of base regions 4 as second conductivity type well regions, and first conductivity type source regions 3 selectively formed on the surface layer of each base region 4.

  An area surrounding the cell arrangement area 20 in which the base area 4 is arranged in plan view is a peripheral area 21. In the cell arrangement area 20, a gate oxide film as a first insulating film sandwiched between the base areas 4. 6, the peripheral region 21 further includes a gate electrode 7 formed on the drift layer 2 via an oxide film 14 as a second insulating film.

In addition, the interlayer insulating film 8 formed so as to selectively cover the gate electrode 7 and the interlayer insulating film 8 formed so as to cover the interlayer insulating film 8 in the cell arrangement region 20 and the source through the NiSi ₂ film 18 as the first metal silicide film. The external output source electrode 10 connected to the region 3 and the external output gate electrode 15 formed to cover the interlayer insulating film 8 in the peripheral region 21 and connected to the gate electrode 7 are further provided.

At least the upper layer of the gate electrode 7 is composed of a WSix film 72 as a second metal silicide film, and the bond energy between the first metal (Ni) and silicon contained in the NiSi ₂ film 18 as the first metal silicide film is WSix. It is smaller than the binding energy of the second metal (W) contained in the film 72 with silicon, and in the composition MSix of the WSix film 72 (M represents the second metal), x is 1.5 or more and less than 2.0. As a result, the resistance of the gate electrode is reduced by including a metal silicide film in the gate electrode, the resistance of the gate contact is reduced by not forming another metal silicide film on the gate electrode, and the source contact and the gate The manufacturing cost can be reduced by forming the contact at the same time.

  Further, according to the embodiment of the present invention, in the semiconductor device, the composition of the second metal silicide film is WSix, so that the thinning effect does not occur and the gate length can be reduced.

  In addition, according to the embodiment of the present invention, in the semiconductor device, since the entire layer of the gate electrode 74 is made of the second metal silicide film, the resistance of the gate electrode can be further reduced.

  In addition, according to the embodiment of the present invention, a method for manufacturing a semiconductor device includes: (a) forming a first conductivity type drift layer 2 on a first conductivity type semiconductor substrate 1; (B) a step of selectively forming a plurality of base regions 4 as well regions of the second conductivity type on the surface layer of the drift layer 2; and (c) a source region 3 of the first conductivity type on the surface layer of the base region 4. Selectively forming.

  Further, (d) a region surrounding the cell placement region 20 in which the base region 4 is placed in plan view is a peripheral region 21, and the cell placement region 20 is sandwiched between the base regions 4 on the drift layer 2. The gate electrode 7 is formed via the gate oxide film 6 as the first insulating film, and the gate electrode 7 is formed on the drift layer 2 via the oxide film 14 as the second insulating film in the peripheral region 21. And (e) forming an interlayer insulating film 8 that covers the gate electrode 7.

Further, (f) a step of simultaneously forming the source contact hole 12 and the gate contact hole 13 connected to the source region 3 and the gate electrode 7, respectively, and (g) a first metal (in the source contact hole 12 and the gate contact hole 13). Forming a NiSi ₂ film 18 as a first metal silicide film on the source region 3 by forming Ni) and heat-treating the first metal (Ni), and (h) an interlayer in the cell arrangement region 20 An external output source electrode 10 covering the insulating film 8 and connected to the source region 3 via the NiSi ₂ film 18 as an external output gate covering the interlayer insulating film 8 in the peripheral region 21 and connected to the gate electrode 7 Forming the electrode 15.

At least the upper layer of the gate electrode 7 is composed of a WSix film 72 as a second metal silicide film, and the binding energy between the first metal (Ni) and silicon contained in the NiSi ₂ film 18 is contained in the WSix film 72. It is smaller than the binding energy of the metal (W) with silicon, and in the composition MSix of the WSix film 72 (M represents the second metal), x is 1.5 or more and less than 2.0. Lowering the resistance of the gate electrode by including metal silicide, lowering the resistance of the gate contact by not forming another metal silicide film on the gate electrode, and manufacturing by being able to form the source contact and the gate contact at the same time Cost reduction can be realized.

  Further, according to the embodiment of the present invention, in the method of manufacturing a semiconductor device, the composition of the second metal silicide film on the gate electrode 7 formed in the cell arrangement region 20 and the peripheral region 21 is WSix. Thus, the thinning effect does not occur and the gate length can be reduced. In the case of a trench structure as shown in the second embodiment to be described later, the trench depth can be miniaturized.

  Moreover, according to the embodiment of the present invention, in the method for manufacturing a semiconductor device, the entire layer of the gate electrode 74 formed in the cell arrangement region 20 and the peripheral region 21 is made of the second metal silicide film. Furthermore, the resistance of the gate electrode can be lowered.

<B. Second Embodiment>
In the MOSFET using the silicon carbide (SiC) of the first embodiment as the substrate, the drain current flows from the source region 3 through the channel portion (portion immediately below the gate electrode 7 of the base region 4 in FIG. 3) and the JFET region 16. (Represents the flow of electrons).

  Since the impurity concentration of the JFET region 16 is low, the resistance is high. In order to reduce this on-resistance, that is, to increase the drain current, there is a so-called trench structure MOSFET in which the JFET region 16 has a gate electrode structure.

<B-1. Manufacturing method>
In the second embodiment, a method for manufacturing a silicon carbide semiconductor device using a trench structure as a gate electrode will be described. In the second embodiment, the same or equivalent parts as in the first embodiment are not described for the sake of brevity.

  First, the structure shown in FIG. 4 of the first embodiment is manufactured by the same process as that of the first embodiment.

  Next, as shown in FIG. 16, drift layer 2 between base regions 4 (portion corresponding to JFET region 16 in FIG. 3 in the first embodiment) is removed by photolithography and etching, and trench region 19 Form.

  The depth of the trench region 19 is set to be deeper than the base region 4. The width of the trench region 19 (the length indicated by D in FIG. 16) is, for example, 1.0 μm.

Next, as shown in FIG. 17, the surface of the cell arrangement region 20 is oxidized at a temperature of about 1000 ° C. in an atmosphere containing oxygen and water vapor. Thereby, a gate oxide film 6 of a thermal oxide film (SiO ₂ ) is formed on the bottom and side walls of the base region 4, the source region 3, the p + contact region 5 and the trench region 19 in the cell arrangement region 20. The film thickness of the gate oxide film 6 is, for example, 50 nm.

  Subsequently, as shown in FIG. 18, a doped polysilicon film 77 is formed on the gate oxide film 6 and the oxide film 14 by the CVD method. The thickness of the doped polysilicon film 77 is, for example, 200 nm (= 0.2 μm).

  In this case, since the width D of the trench region 19 is, for example, 1.0 μm, the trench region 19 is not completely filled with the doped polysilicon film 77, and a 0.6 μm gap exists in the center. .

  Further, the WSix film 75 is formed on the doped polysilicon film 77 by the CVD method while maintaining the cleanliness of the surface (see FIG. 19). A gate electrode 76 is constituted by a laminated film of the doped polysilicon film 77 and the WSix film 75. Here, the value of x representing the composition of the WSix film 75 is 1.95.

The composition of WSix can be adjusted by changing the flow ratio of tungsten hexafluoride (WF ₆ ) and silane (SiH ₄ ), which are gases introduced into the CVD apparatus. In addition to WF ₆ and SiH ₄ gas, H ₂ or N ₂ may be added as a carrier gas. The temperature during film formation is 450 ° C., for example. The film thickness is set to be equal to or greater than the film thickness that completely fills the trench region 19. In Embodiment 2, it is set to 400 nm (0.4 μm).

  Thereby, as shown in FIG. 19, trench region 19 is completely filled with doped polysilicon film 77 and WSix film 75. Since the metal of the metal silicide film (WSix film 75) of the gate electrode is sufficiently embedded in the trench region 19, a SiC-MOSFET having a trench gate electrode structure capable of further reducing the resistance of the gate electrode can be manufactured at low cost.

  A sputtering method may be used as a method of forming the WSix film 75. However, the CVD method has better step coverage (step coverage), and thus the CVD method is used in the second embodiment.

  Next, as shown in FIG. 20, a resist 30 is formed on the peripheral region 21 by photolithography. Thereafter, the WSix film 75 and the doped polysilicon film 77 on the cell arrangement region 20 are removed by etching. By this step, the WSix film 75 and the doped polysilicon film 77 other than the trench region 19 are removed.

  FIG. 21 shows a structure in which the trench region 19 is filled with the WSix film 75 and the doped polysilicon film 77 to form the gate electrode 76.

  After this step, a MOSFET is manufactured by the same steps as in the first embodiment.

  An interlayer insulating film 8 is formed on the entire surface of the substrate (FIG. 22), and a source is formed on part of the source region 3 in the cell arrangement region 20 and on the upper portion of the p + contact region 5 by photolithography and RIE (Reactive Ion Etching) etching. The contact hole 12 and the gate contact hole 13 are formed on the gate electrode 76 in the peripheral region 21.

  The source contact hole 12 and the gate contact hole 13 are formed simultaneously. By this etching, a part of the source region 4 and the p + contact region 5 are exposed from the bottom surface of the source contact hole 12. Further, the gate electrode 76 is exposed from the bottom surface of the gate contact hole 13 (FIG. 23).

  Next, as shown in FIG. 24, a nickel (Ni) film 17 which is a first metal film is formed on the entire surface of the substrate by sputtering. The thickness of the nickel (Ni) film 17 is, for example, 50 nm. Thereafter, a first annealing process is performed on the structure shown in FIG.

As a result, as shown in FIG. 25, a NiSi ₂ film 18 is formed on the source region 3 and the p + contact region 5 exposed from the bottom surface of the source contact hole 12.

The first annealing treatment is performed at a temperature of 300 to 800 ° C. by, for example, the RTA method. By the first annealing treatment, nickel (Ni) of the nickel (Ni) film 17 reacts with silicon carbide (SiC) constituting the p + contact region 5 and the source region 3 in contact with the NiSi ₂ film 18. Is formed.

After the NiSi ₂ film 18 as the first metal silicide film is formed, the structure in which the NiSi ₂ film 18 is formed is cleaned with an acid chemical solution containing sulfuric acid or hydrochloric acid, for example. By the cleaning, the nickel (Ni) film 17 which has not been reacted in the silicidation reaction is removed. FIG. 26 shows the state after the unreacted nickel (Ni) film 17 is removed. Since the NiSi ₂ film is not formed on the WSix film 75, the gate contact hole 13 has no NiSi ₂ film.

  Thereafter, drain electrode 9 is formed on the back surface of silicon carbide (SiC) semiconductor substrate 1 (see FIG. 27). The drain electrode 9 is formed by the following procedure.

First, a sputtering method is performed on the back surface of the silicon carbide (SiC) semiconductor substrate 1 to form a nickel (Ni) film having a thickness of 300 nm. Next, for example, a second annealing process at about 1000 ° C. is performed by the RTA method. For the reason described above, it is preferable that the second annealing treatment time is short. Thereby, the contact resistance of the NiSi ₂ film 18 in the source contact hole 12 can be further reduced.

Further, the nickel (Ni) film formed on the back surface of the silicon carbide (SiC) semiconductor substrate 1 reacts with the back surface of the silicon carbide (SiC) semiconductor substrate 1 to form a NiSi ₂ film at the same time. Low resistance ohmic contact is realized. Thus, the drain electrode 9 composed of the nickel (Ni) film and the NiSi ₂ film is formed on the back surface of the silicon carbide (SiC) semiconductor substrate 1 (see FIG. 27).

  Next, an aluminum (Al) film having a thickness of 3 μm is formed on the interlayer insulating film 8 so as to fill the source contact hole 12 and the gate contact hole 13. Thereafter, photolithography and etching are performed on the aluminum (Al) film. As a result, the electrode film is patterned, and the external output source electrode 10 and the external output gate electrode 15 are formed as shown in FIG.

Here, the external output source electrode 10 and the external output gate electrode 15 are electrically separated by the patterning. The external output source electrode 10 is formed in the cell arrangement region 20 and is electrically connected to the upper portion of the source region 3 and the upper portion of the p + contact region 5 through the NiSi ₂ film 18. On the other hand, the external output gate electrode 15 is formed in the periphery and is electrically connected to the gate electrode 76.

  Finally, as shown in FIG. 29, a gold (Au) film having a film thickness of 150 nm is formed on the drain electrode 9 by sputtering to form the back connection electrode 11. Through these steps, a trench structure MOSFET is manufactured.

As described above, in the silicon carbide semiconductor device according to the second embodiment, similarly to the silicon carbide semiconductor device according to the first embodiment, the NiSi ₂ film 18 is formed in the source contact hole 12, and the doped poly A WSix film 75 (x = 1.95) as a second metal silicide film having a tungsten (W) content higher than that of silicon (Si) is used as an upper layer of the silicon film 77.

  That is, the trench region 19 is filled not only with a doped polysilicon film having a high resistivity but also with a WSix film having a low resistivity. For this reason, the resistance of the gate electrode 76 can be reduced.

The bond energy between silicon (Si) and nickel (Ni) is smaller than the bond energy between silicon (Si) and tungsten (W). For this reason, even if the source contact hole 12 and the gate contact hole 13 are opened simultaneously, the NiSi ₂ film is not formed on the WSix film 75, and the gate contact resistance can be reduced.

  Since the source contact hole 12 and the gate contact hole 13 are opened simultaneously as in the first embodiment, a silicon carbide semiconductor device with reduced manufacturing costs can be obtained.

  In the second embodiment, since the portion of the JFET region 16 of the first embodiment is changed to the gate electrode 76 having the trench structure, the resistance of the JFET region 16 of the first embodiment is eliminated. Therefore, in the second embodiment, the drain current can be improved, that is, the on-resistance can be reduced as compared with the first embodiment.

  Further, according to the embodiment of the present invention, in the method of manufacturing a semiconductor device, the gate electrode 7 formed in the cell arrangement region 20 and the peripheral region 21 is a step of forming by the CVD method, so that the step coverage is achieved. (Step coverage) becomes better.

<B-2. Modification>
In the first and second embodiments, the doped polysilicon film uses polysilicon doped with the first conductivity type impurity, but it goes without saying that the doped impurity has the same effect even when the second conductivity type is used. . The conductivity type of the doped polysilicon film may be selected so that the threshold voltage (Vth) of the MOSFET becomes a desired value.

  In the present invention, the case where the semiconductor element is a vertical MOSFET is disclosed. For example, the conductivity type of the silicon carbide (SiC) semiconductor substrate 1 shown in FIG. 3, FIG. 15, or FIG. Even if a semiconductor element having an IGBT (Insulated Gate Bipolar Transistor) cell region of a type (P type) is configured, the above-described effects of the present invention are similarly obtained. Therefore, it can be said that the scope of the present invention is a semiconductor element as a switching element having a MOS structure such as MOSFET or IGBT.

  In the present invention, the semiconductor element itself having the MOS structure described in the first and second embodiments is defined as a “semiconductor device” in a narrow sense. For example, the semiconductor element is Application by incorporating the semiconductor element, such as an inverter module that is mounted on a lead frame and sealed together with a freewheel diode connected in antiparallel and a control circuit that generates / applies the gate voltage of the semiconductor element. The power module itself is also defined as “semiconductor device” in a broad sense.

<B-3. Effect>
According to the embodiment of the present invention, in the method of manufacturing a semiconductor device, (i) after the step of selectively forming the first conductivity type source region 3 on the surface layer of each base region 4 as a well region, A step of forming a trench region 19 deeper than the base region 4 in the surface layer of the drift layer 2 between the base regions 4 is further provided, and the step (d) includes a gate oxide film as a first insulating film in the trench region 19. 6, the drain current can be improved, that is, the on-resistance can be reduced as compared with the structure in the first embodiment.

  Further, according to the embodiment of the present invention, in the semiconductor device, the gate electrode 76 in the cell arrangement region 20 is formed in the trench region 19 on the drift layer 2, so that the structure in the first embodiment is improved. The drain current can be improved, that is, the on-resistance can be reduced.

  The present invention is suitable for application to a power converter such as an inverter.

1 semiconductor substrate, 2 drift layer, 3 source region, 4 base region, 5 p + contact region, 6 gate oxide film, 7, 74, 76 gate electrode, 8 interlayer insulating film, 9 drain electrode, 10 external output source electrode, 11 Back connection electrode, 12 source contact hole, 13 gate contact hole, 14 oxide film, 15 external output gate electrode, 16 JFET region, 17 nickel (Ni) film, 18 NiSi ₂ film, 19 trench region, 20 cell placement region, 21 Peripheral region, 30 resist, 71, 77 doped polysilicon film, 72, 75 WSix film, 73 gate wiring.

Claims (9)

A silicon carbide semiconductor substrate;
The formed silicon carbide semiconductor substrate, a drift layer of a first conductivity type made of silicon carbide semiconductor,
A plurality of second conductivity type well regions selectively formed on the surface layer of the drift layer;
A first conductivity type source region selectively formed on each well region surface layer,
An area surrounding the cell arrangement area where the well area is arranged in plan view is a peripheral area,
The cell arrangement region is formed on the drift layer via a first insulating film sandwiched between the well regions, and the peripheral region is formed on the drift layer via a second insulating film. A gate electrode;
An interlayer insulating film formed to selectively cover the gate electrode;
An external output source electrode formed over the interlayer insulating film in the cell arrangement region and connected to the source region via a first metal silicide film;
An external output gate electrode formed to cover the interlayer insulating film in the peripheral region and connected to the gate electrode;
At least the upper layer of the gate electrode is made of a second metal silicide film,
The bond energy between the first metal contained in the first metal silicide film and silicon is smaller than the bond energy between the silicon and the second metal contained in the second metal silicide film;
In the composition MSix of the second metal silicide film (M represents the second metal), x is 1.5 or more and less than 2.0,
Semiconductor device. The composition of the second metal silicide film is WSix,
The semiconductor device according to claim 1. The gate electrode in the cell arrangement region is formed in a trench region on the drift layer,
The semiconductor device according to claim 1 or 2. The whole layer of the gate electrode is made of the second metal silicide film,
The semiconductor device according to any one of claims 1 to 3. (A) forming a drift layer of a first conductivity type made of a silicon carbide semiconductor on a silicon carbide semiconductor substrate;
(B) selectively forming a plurality of second conductivity type well regions on the surface of the drift layer;
(C) selectively forming a first conductivity type source region on the surface of the well region;
(D) A region surrounding the cell arrangement region in which the well region is arranged in plan view is defined as a peripheral region, and in the cell arrangement region, a gate electrode sandwiched between the well regions is formed on the drift layer. Forming the gate electrode on the drift layer via the second insulating film in the peripheral region; and
(E) forming an interlayer insulating film covering the gate electrode;
(F) simultaneously forming contact holes connected to the source region and the gate electrode,
(G) forming a first metal in each contact hole, and heat-treating the first metal to form a first metal silicide film on the source region;
(H) an external output source electrode that covers the interlayer insulating film in the cell arrangement region and is connected to the source region via the first metal silicide film; and the interlayer insulating film in the peripheral region; Forming an external output gate electrode connected to the electrode,
At least the upper layer of the gate electrode is made of a second metal silicide film,
The bond energy between the first metal contained in the first metal silicide film and silicon is smaller than the bond energy between silicon and the second metal contained in the second metal silicide film;
In the composition MSix of the second metal silicide film (M represents the second metal), x is 1.5 or more and less than 2.0,
A method for manufacturing a semiconductor device. The composition of the second metal silicide film on the gate electrode upper layer formed in the step (d) is WSix,
A method for manufacturing a semiconductor device according to claim 5 . The step (d) is a step of forming the gate electrode by a CVD method.
A method for manufacturing a semiconductor device according to claim 5 . (I) after the step (c), further comprising a step of forming a trench region deeper than the well region in the surface layer of the drift layer between the well regions;
The step (d) is a step of forming a gate electrode in the trench region via the first insulating film,
The method of manufacturing a semiconductor device according to any one of claims 7 claims 5. The whole layer of the gate electrode formed in the step (d) is composed of the second metal silicide film,
The method of manufacturing a semiconductor device according to item 1 any of claims 8 claims 5.

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