JP2002231944A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reliable power semiconductor device which is hardly influenced by movable ions or the like and can have a stabilized high breakdown voltage. SOLUTION: A p-body region 23 is formed on one principal plane 21A of an n-type drift region 22, and an n-source region 24 is formed inside the body region 23, with the body region 23 surrounded by the drift region 22. P-type fourth semiconductor regions(FLR) 25A, 25B, and 25C are formed concentrically, being separated from each other, on the outside of the body region 23 at a distance from the body region 23. On the FLRs 25A, 25B, and 25C, first annular conductive films 27A, 27B, 27C, and 27D are formed via a first insulation film 26. The first conductive film suppresses the movement of movable ions in the insulation film such as the first insulation film 26, preventing the influence of the movable ions on a depletion layer extended in the drift region between the FLRs 25A, 25B, and 25C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device and, more particularly, to a technique for terminating a power semiconductor device having a high withstand voltage.

[0002]

2. Description of the Related Art A power insulated gate field effect transistor 1 as shown in FIG. 4 is conventionally known. This conventional insulated gate field effect transistor for power (hereinafter, referred to as
It is called "conventional field effect transistor." 1) is sequentially formed on one main surface of a semiconductor substrate made of silicon, for example.
High impurity density n-type semiconductor region (drain region) 2, n
Semiconductor region (drift region) 3, a plurality of p-type semiconductor regions (body regions) 4 with a high impurity density, and an n-type semiconductor region (source region) 5 with a high impurity density formed inside the plurality of body regions 4 It is comprised including. Furthermore,
A drain electrode 6 formed in contact with the drain region 2, a gate insulating film 7 formed in contact with the surface of the body region 4,
A gate electrode 8 on the gate insulating film 7 and a source electrode 9 formed in contact with the surface of the source region 5 are provided.

In addition, in such a conventional field effect transistor 1, a field-limited ring (FL) surrounds a plurality of body regions 4 in plan view.
R) 10 is formed in a ring shape. In addition, these FLR1
0, an equipotential ring (EQ) composed of an n-type semiconductor region 11 having a high impurity density and a metal film 12 connected to the n-type semiconductor region 11 is provided outside the outermost FLR 10.
R) 13 are formed annularly apart from each other.

[0004] In the conventional field effect transistor 1 shown in FIG.
This is the state of F. The plurality of FLRs 10 are provided for the purpose of improving the breakdown voltage in the OFF state. That is, if a voltage (reverse bias voltage) for increasing the potential on the drain electrode 6 side is applied between the drain electrode 6 and the source electrode 9, the body region 4 and the source electrode 9 are short-circuited. The pn junction between 4 and drift region 3 is reverse biased. Along with this, a depletion layer spreads mainly from the pn junction to the drift region 3 having a low impurity density. Further, if the reverse voltage is increased, this pn
The depletion layer extending from the junction sequentially reaches from the innermost FLR 10 to the outermost FLR 10. When the depletion layer sequentially reaches the outer FLR 10 from the innermost FLR 10,
The body region 4 and the plurality of FLRs 10 are as if one p
It can be regarded as a type semiconductor region. Therefore, the corner portion (curved portion) of the body region 4 where the electric field concentration is most likely to occur.
Is located on the center side of the p-type semiconductor region, and the electric field concentration at the corners of the body region 4 is reduced.

The corner of the FLR 10 has a larger curvature than the corner of the body region 4.
Since the electric field on the outer peripheral side of 0 is smaller than the corner portion of the body region 4, the electric field concentration on the outer peripheral part of the FLR 10 can be satisfactorily prevented by appropriately setting the interval between the FLRs 10. Therefore, if the reverse bias voltage is increased to such an extent that breakdown occurs, a voltage breakdown occurs at the corner portion of the body region 4, but the voltage value can be increased as compared with a structure in which the FLR 10 is not formed.

[0006]

However, in the conventional field-effect transistor 1 shown in FIG.
A field insulating film 7A covering the upper surface of R10 (the other main surface side of the silicon substrate), an interlayer insulating film (or passivation film) 14 covering the field insulating film 7A,
Further, the resin sealing body (not shown) covering the interlayer insulating film 14 contains a large number of mobile ions, and has a problem that the mobile ions are affected by the mobile ions.

That is, the mobile ions move in the field insulating film 7A, the interlayer insulating film 14, and the like under the influence of the potential distribution and the ambient temperature accompanying the operation of the power semiconductor device. Here, when the negative movable ions are accumulated in the field insulating film 7A, the interlayer insulating film 14, the resin sealing body, and the like covering the upper surface of the FLR 10, the drift region 3 formed between the plurality of FLRs 10 Under the influence of negative mobile ions, the carrier density on the surface decreases. Along with this,
P formed at the interface between drift region 3 and body region 4
Since the depletion layer extending from the n-junction easily spreads, the depletion layer spreads to the outer FLR 10 due to the relatively low reverse bias voltage, and as a result, the breakdown voltage decreases.
In some cases, a p-type channel is formed on the surface of drift region 3 under the influence of the negative mobile ions,
A leak current flows between the LRs 10 and between the FLR 10 and the body region 4. As described above, since the expansion of the depletion layer is affected by mobile ions, the withstand voltage of the power semiconductor device fluctuates due to the movement and distribution of mobile ions. Such a problem is caused by the conventional field effect transistor 1
However, the present invention is not limited to this, and similarly occurs in various power semiconductor devices such as a conventional power bipolar transistor and a power diode provided with an FLR, and improvement is desired.

The present invention has been made to solve the above problems. Therefore, an object of the present invention is to provide a highly reliable power semiconductor device which is hardly affected by mobile ions and the like, and which can obtain a stable breakdown voltage.

It is another object of the present invention to provide a highly reliable power semiconductor device whose withstand voltage is not affected by environmental temperature, operating temperature, operating voltage, etc., and whose variation with time is small.

[0010]

In order to solve the above-mentioned problems, the present invention is characterized by a first semiconductor region of a first conductivity type and a first semiconductor region on one main surface side of the first semiconductor region. The second semiconductor region of the second conductivity type and the third semiconductor region of the first conductivity type disposed inside the second semiconductor region, and the second semiconductor region arranged in an annular shape surrounding the second and third semiconductor regions on one main surface side. The gist is to provide a power semiconductor device including a conductive fourth semiconductor region, an insulating film formed on one main surface, and a first conductive film disposed on the insulating film. However, the “first conductive film” is formed from the second semiconductor region to the fourth conductive film.
It is arranged above the insulating film in a region extending over the semiconductor region. The fourth semiconductor region corresponds to “FLR” described at the beginning. The "power semiconductor device" of the present invention has a withstand voltage of 50.
V class, 600V class, 800V class, 1.2k
Various devices such as V class, 4 kV class, and 10 kV class are included. Note that the “annular” does not always need to be a completely continuous (closed) ring, and may be a continuous ring through a minute gap smaller than the diffusion length of a carrier in a certain case. This is because if the gap is shorter than the carrier diffusion length, the depletion layer is pinched off by the gap, so that the spread of the depletion layer is not significantly affected.

In the power semiconductor device according to the present invention, when a voltage having a reverse bias voltage is applied to a pn junction formed by the first semiconductor region and the second semiconductor region, the voltage becomes p.
A depletion layer spreads from the n-junction. If the impurity density of the first semiconductor region is sufficiently lower than the impurity density of the second semiconductor region, the depletion layer spreads mainly toward the first semiconductor region. When the reverse bias voltage is gradually increased, the depletion layer extending from the pn junction interface expands toward the annular fourth semiconductor region and reaches the fourth semiconductor region. Thereby, the electric field concentration at the corner portion (curved portion) of the second semiconductor region is reduced, and the withstand voltage (reverse blocking withstand voltage) of the power semiconductor device can be improved. At this time, the influence of mobile ions included in the insulating film is reduced by the first conductive film formed on the insulating film. In other words, the mobile ions move in the insulating film under the influence of the potential distribution and the ambient temperature accompanying the operation of the power semiconductor device, and the first conductive film formed above the first semiconductor region forms a so-called “ It functions as an "equipotential ring" to suppress the movement of mobile ions. As a result, the effect of the mobile ions contained in the insulating film on the depletion layer is prevented. For this reason, in the first semiconductor region near the fourth semiconductor region, the carrier density on the surface thereof is prevented from changing due to the movement of the mobile ions. Thus, the first
By forming the conductive film, it is possible to prevent the spread of the depletion layer extending from the pn junction from becoming constant without being affected by the movement of mobile ions contained in the insulating film, thereby preventing the junction withstand voltage from fluctuating. Therefore, in the power semiconductor device according to the features of the present invention, the withstand voltage is not affected by the environmental temperature, the operating temperature, the operating voltage, and the like, and the change with time is reduced. Therefore, a highly reliable power semiconductor device can be realized.

In the power semiconductor device according to the present invention,
On one main surface, a fifth of the first conductivity type, which is arranged in an annular shape surrounding the fourth semiconductor region on the outer peripheral side of the fourth semiconductor region.
It is preferable that the semiconductor device further includes a second conductive film which is disposed over the semiconductor region and the insulating film and is connected to the fifth semiconductor region at an opening of the insulating film.

In the power semiconductor device according to the present invention,
The fourth semiconductor region is preferably arranged as a plurality of concentric rings separated from each other. The “concentric ring” does not need to be circular, and may be a rectangular or polygonal concentric ring. By arranging the plurality of fourth semiconductor regions in a concentric annular shape spaced apart from each other, a depletion layer extending from the pn junction sequentially fills the first semiconductor regions formed between the adjacent fourth semiconductor regions. Because it spreads, the electric field concentration can be further reduced. In this case, it is preferable that a plurality of first conductive films spatially separated from each other above the fourth semiconductor region are arranged above the first semiconductor region located between the plurality of concentric rings. Each first conductive film corresponds to a gate electrode of a MOSFET having two adjacent fourth semiconductor regions as source / drain regions. Multiple first
Although the conductive films are spatially separated as a planar pattern, they may be electrically connected to each other and configured to have the same potential.

If the first conductive film is used in an electrically floating state, the circuit structure is not complicated, and the first conductive film is affected by the movement of mobile ions contained in the insulating film, and the surface of the first semiconductor region is not affected. Can be prevented from changing. There is also a disadvantage that the circuit configuration becomes complicated,
A configuration in which a constant bias is applied to the first conductive film may be used.
This constant bias may be determined in consideration of the polarity of the mobile ions existing in the insulating film and the conductivity type of the first semiconductor region. As described above, if a constant bias is applied to the first conductive film in consideration of the polarity, the carrier density on the surface of the first semiconductor region is more effectively affected by the movement of mobile ions contained in the insulating film. Can be prevented.

In the power semiconductor device according to the present invention,
The third semiconductor region is a first main electrode region arranged inside the second semiconductor region, and a sixth semiconductor region serving as a second main electrode region on the other main surface of the first semiconductor region facing one main surface. Insulated gate bipolar transistor (IGBT), power insulated gate field effect transistor (power IGFET), power insulated gate electrostatic induction transistor (power IGSIT), power bipolar transistor (power BJT) And a power semiconductor device such as a GTO thyristor. The third semiconductor region is
It is not necessary to be arranged inside all the second semiconductor regions. For example, when a plurality of second semiconductor regions are arranged in an island shape, the third semiconductor region inside the outermost second semiconductor region may be omitted. Power FET
, The sixth semiconductor region is of the first conductivity type,
In T, power BJT and GTO thyristors, the sixth semiconductor region is of the second conductivity type. Here, the “first main electrode region”
Means one of the emitter region and the collector region in the IGBT and the power BJT, one of the source region and the drain region in the power IGFET and the power IGSIT, and one of the anode region and the cathode region in the GTO thyristor It means a semiconductor region. The “second main electrode region” is defined as I
In a GBT, one of the emitter region and the collector region, which is not the first main electrode region, and the power IG
In a FET and a power IGSIT, one of a source region and a drain region that does not become the first main electrode region, and in a GTO thyristor, one of an anode region and a cathode region that does not become the first main electrode region Means area. In addition, IGBT,
In the power IGFET and the power IGSIT, the second semiconductor region functions as a body region. A gate insulating film is disposed on the surface of the second semiconductor region (body region) between the third semiconductor region and the first semiconductor region, and a gate electrode is further provided above the gate insulating film. Of course. Power IGSIT is Power I
It can be interpreted as a transistor in the limit of shortening the channel of the GFET. That is, it can be defined as a device in which the channel is made short enough to cause punching-through between the source region and the drain region of the power IGFET, and in which a potential barrier which can be controlled by the drain voltage and the gate voltage exists in the channel. Specifically, this is a power semiconductor device in which the height of the potential, which is the saddle point in a two-dimensional space of the source-drain potential and the potential in the channel due to the gate voltage, is controlled by the drain voltage and the gate voltage. Therefore, the current-voltage characteristics of the power IGSIT show characteristics according to the same exponential function law as the triode characteristics of the vacuum tube. In a power BJT and a GTO thyristor, the second semiconductor region is a base region.

On the other hand, in the power semiconductor device according to the present invention, a plurality of second semiconductor regions are arranged as a pair facing each other, and a third semiconductor region is arranged between the paired second semiconductor regions. If one sixth main electrode region is provided and a sixth semiconductor region serving as a second main electrode region is further disposed on the other main surface of the first semiconductor region opposed to one main surface, a power junction gate type field effect transistor (power JFET), power junction gate type static induction transistor (power JSIT),
A power semiconductor device such as an electrostatic induction thyristor (SI thyristor) can be configured. Power JFET and Power JSI
In the case of T, the sixth semiconductor region has the first conductivity type, and in the SI thyristor, the sixth semiconductor region has the second conductivity type. Here, the “first main electrode region” means one of a source region and a drain region in the power JFET and the power JSIT, and one of an anode region and a cathode region in the SI thyristor. The “second main electrode region” is one of a source region and a drain region that does not become the first main electrode region in the power JFET and the power JSIT, and an anode that does not become the first main electrode region in the SI thyristor. Means either the region or the cathode region. Power JSIT
Can be interpreted as a transistor in the limit of the short channel of the power JFET. The second semiconductor region becomes a gate region of the power JFET, the power JSIT, and the SI thyristor.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a power semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
However, it should be noted that the drawings are schematic, and the thickness of each layer and the ratio of the thickness are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it is needless to say that dimensional relationships and ratios are different between drawings.

A power insulated gate field effect transistor (hereinafter referred to as “power MOSFET”) according to an embodiment of the present invention.
T ". 1) a first conductivity type first semiconductor region 22 as shown in FIG. 1, and a second conductivity type first semiconductor region 22 disposed inside the first semiconductor region 22 on one main surface side of the first semiconductor region 22. The second semiconductor region 23 and the third of the first conductivity type
The semiconductor region 24, the second conductivity type fourth semiconductor regions 25A, 25B, 25C arranged in an annular shape surrounding the second and third semiconductor regions 24 on one main surface side, on one main surface. First insulating film (field insulating film) formed
26, and first conductive films 27A, 27B, 27C, and 27D disposed on the first insulating film 26. The first conductivity type and the second conductivity type are opposite to each other. In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the reverse is also possible.

The first semiconductor region 22 has an impurity density (5 × 10 ¹² cm ^{−3 to} 5 × 1) of the silicon substrate 21 as a base material.
( ^{Approximately} 0 ¹⁶ cm ⁻³ ). The first semiconductor region 22 has a thickness of 150 μm which is close to the substrate thickness of a silicon substrate (silicon wafer) 21 as a base material.
It has a thickness of up to 600 μm, and is a main region constituting the semiconductor substrate 21. The impurity density and thickness of the first semiconductor region 22 may be determined in consideration of the rated withstand voltage, switching speed, on-resistance, and the like. The first semiconductor region 22 functions as a drift region of the power MOSFET 20.

The second semiconductor region 23 has a thickness of 2 μm to 15 μm at the center of the element forming region on one main surface 21 A of the semiconductor substrate 21.
It is formed at a depth of μm and has a higher impurity density than the first semiconductor region (drift region) 22, for example, 5 × 10 ¹⁵ cm ^−3.
It is doped to about 5 × 10 ¹⁷ cm ⁻³ . Second
Semiconductor region 23 functions as a body region of power MOSFET 20. Fourth semiconductor regions 25A, 25B, 25
C is also formed as a region having an impurity density of about 5 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ^{−3 at} a depth of 2 μm to ¹⁵ μm similarly to the body region 23. However, the fourth semiconductor regions 25A, 25B, 25C need not be at the same depth as the body region 23. For example, the fourth semiconductor region 25A,
If the diffusion depths of 25B and 25C are gradually reduced as they approach the outer peripheral portion of the chip, the effective curvature as a whole can be reduced, and a higher breakdown voltage can be achieved. Also, it is effective to gradually lower the impurity density of the fourth semiconductor regions 25A, 25B, 25C as approaching the outer peripheral portion of the chip, which is effective for relaxing the electric field, and it is possible to increase the breakdown voltage. Become. As shown in FIG. 2, a plurality of (three in this embodiment) fourth semiconductor regions 25A, 25B, and 25C are spaced apart from body region 23 along one main surface 21A of semiconductor base 21. It is formed so as to form a rectangular ring.

The third semiconductor region 24 is a first main electrode region (source region) disposed inside the body region 23. The source region 24 is formed at a depth of about 0.5 m to 5 m, the impurity concentration is 2 × 10 ¹⁸ cm ^-3 ~1 ×
It is about 10 ²¹ cm ^-3 . A sixth semiconductor region 28 serving as a second main electrode region (drain region) is further arranged on the other main surface of drift region 22 facing one main surface of drift region 22. The drain region 28 has an impurity density of 2 ×
The semiconductor region has a low specific resistance of about 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The drain region 28 is filled with a donor impurity from the other main surface 21B side of the silicon substrate 21 to a depth of 15 μm.
It is a region formed by doping to a depth of about m to 80 μm. The drain region 28 is formed on the silicon substrate 21
May be formed on the other main surface 21B by epitaxial growth. On the other main surface 21B on which the drain region 28 is formed, a drain electrode 29 made of a metal thin film is formed so as to make ohmic contact with the drain region 28.

A gate insulating film 31 is provided on the surface of the body region 23 between the source region 24 and the drift region 22, and a gate electrode 32 is further disposed on the gate insulating film 31.

First conductive films 27A, 27B, 27C, 27
D is the distance from the body region 23 to the fourth semiconductor regions 25A, 25A.
B and 25C are disposed above the first insulating film 26 in a region extending over 25C. Fourth semiconductor regions 25A, 25B, 25
C functions as the FLR of the power MOSFET 20. FLRs 25A, 25B, and 25C are arranged as a plurality of concentric rings separated from each other.

Further, as shown in FIG.
FLR25A, 25B, 25
A fifth semiconductor region of the first conductivity type (hereinafter, referred to as a ring) surrounding the FLRs 25A, 25B, and 25C on the outer peripheral side of C.
It is called “EQR diffusion area”. ) 30 is formed.
The EQR diffusion region 30 has a depth of about 0.5 μm to 5 μm similar to the source region 24 and an impurity density of 2 × 10 ¹⁸ cm ^−3.
It is a semiconductor region of about 1 × 10 ²¹ cm ⁻³ . And
A second conductive film (EQ) connected to the EQR diffusion region 30 at the opening of the first insulating film 26 is provided above the first insulating film 26.
(R wiring film) 36 is further disposed.

As shown in FIG. 2 and FIG. 3, on one main surface 21A side of the silicon substrate 21, a square is divided into nine at substantially the center of an element forming region and separated from each other to form a planar rectangular shape. 9 body regions 23 are formed. Each body region 23 has a structure in which the periphery is surrounded by drift region 22 except for one main surface 21A of silicon substrate 21, and the interface with drift region 22 is pn.
It is joined.

The source region 24 is formed shallower than the body region 23 at a position inside the outer periphery of the body region 23 by a predetermined distance. In other words, the structure is such that the body region 23 is interposed between the drift region 22 and the source region 24. As described above, the vicinity of the surface of the body region 23 between the drift region 22 and the source region 24 becomes a channel formation region of the power MOSFET 20 as described later.

In FIG. 3, the body region located at the center of the nine body regions 23 is denoted by 23 (C), and the source region formed in the body region 23 (C) is denoted by 24 (C). As shown. In the body region 23 (C) located at the center, as shown by hatching in FIG. 3, the source region 24 (C) follows the plane contour of the body region 23 (C) and is inwardly rectangular by a predetermined dimension a from the plane contour. It is formed so as to draw a ring shape. The source region 24
The band width of the orbiting ring in (C) is set to a predetermined size b. Therefore, on one main surface 21A of the silicon substrate 21, the inside and outside of the source region 24 (C) are
The body region 23 is exposed.

On the other hand, source region 2 formed in body region 23 located around central body region 23 (C).
4 are formed along the inside by a predetermined dimension a of the side (planar outline) facing each of the four sides of the central body region 23 (C), and are adjacent to each other except for the central body region 23 (C). The body regions 23 are formed along the inner side by a predetermined dimension a from opposing sides (planar contours) of the body regions 23. The band width of these source regions 24 is also set to have a predetermined size b. As a result, the central body region 23
In the body region 23 excluding (c), depending on the location, there are a planar L-shape and a planar U-shape.

Outside the group of body regions 23, FLR 25A doped with an acceptor impurity at a high concentration from one main surface 21A of silicon substrate 21 to a predetermined depth, as shown in FIGS. 25B and 25C are formed in a rectangular ring shape. These FLR25A, 25
B and 25C are arranged concentrically apart from each other. That is, the drift region 22 is interposed between the FLRs 25A, 25B, and 25C. The drift region 22 is also provided between the innermost FLR 25A and the body region 23. These FLRs 25A, 25B, 25C are:
It may be formed in the same impurity diffusion step as the body region 23 described above, or may be formed in a diffusion step separate from the body region 23. In this impurity diffusion step, a predetermined window is formed on the oxide film formed on one main surface 21A by using a photolithography technique and an etching technique.
An impurity-added thin film containing a dopant such as boron (B), which is an acceptor impurity, for example, a boron glass (BSG) film or the like is deposited from above the oxide film, and heat-treated at a predetermined temperature and for a predetermined time to perform selective diffusion. Thereafter, the impurity-added thin film may be removed.

Further, as shown in FIGS. 1 and 2, the outermost F on one main surface 21A of the silicon substrate 21 is formed.
Outside the LR25C, an EQ with a high impurity density and a predetermined depth
The R diffusion region 30 is formed in a rectangular ring shape. In addition,
This EQR diffusion region 30 may be formed in the same impurity diffusion step as the source region 24 described above.
4 may be formed in a diffusion step separate from that of FIG. An EQR wiring film 36 made of a conductive material such as a metal is electrically connected to the upper surface of the EQR diffusion region 30. In the impurity diffusion step, a predetermined window is formed on the oxide film formed on one main surface 21A by using a photolithography technique and an etching technique, and then phosphorus (phosphor) as a donor impurity is formed on the oxide film. P), an impurity-added thin film containing a dopant such as arsenic (As), for example, a phosphorus glass (PSG) film or an arsenic glass (AsSG) film is deposited, and subjected to a heat treatment at a predetermined temperature and for a predetermined time to perform selective diffusion. An n-type semiconductor region is formed with a high impurity density. After that, the impurity-added thin film is removed. Note that, without using the impurity-added thin film as described above, phosphorus oxychloride (POC
For example, a gas phase diffusion method using a liquid source such as l ₃ ) may be performed. Alternatively, impurity ions such as ³¹ P ⁺ and ⁷⁵ As ⁺ may be implanted at a predetermined dose by an ion implantation method, and then drive-in (heat treatment) may be performed to a desired depth.

Also, one main surface 21A of the silicon substrate 21
The gate insulating film 31 formed thereon is disposed on the upper surface of the drift region 22 formed between the body regions 23 adjacent to each other, as shown in FIG. It extends so as to extend over the upper surface of the body region 23) and reach the source region 24.
On the upper surface of the gate insulating film 31, a gate electrode 32 made of a conductive film such as, for example, doped polysilicon (doped polysilicon) is formed. Instead of doped polysilicon, refractory metals such as tungsten (W), titanium (Ti), molybdenum (Mo), and silicides thereof (WSi ₂ , TiSi ₂ , MoS)
i ₂ ) or the like, or the polycide using these silicides may be used to form the gate electrode 32. The gate electrode 32 is integrally formed so as to face the channel forming region (body region 23) in all the body regions 23 and the drift region 22 between the body regions 23 adjacent to each other, as indicated by a chain line in FIG. Is formed. The gate electrode 32 is formed of a second insulating film (interlayer insulating film) 33.
It is covered with. In FIG. 1, the gate insulating film 31 is formed to have a uniform thickness, but only the portion corresponding to the upper surface of the drift region 22 formed between the adjacent body regions 23 is selectively formed to be thick. You may.

Openings (contact holes) are formed in the second insulating film 33 so as to correspond to the central portions of the respective body regions 23. Body region 2 through this opening
3 and the source region 24 include, for example, aluminum (A
l) or aluminum alloy (Al-Si, Al-
A source electrode 34 made of a wiring material such as Cu-Si) is electrically connected. Source electrode 34 shorts body region 23 and source region 24, and maintains body region 23 at the potential of source electrode 34. This source electrode 34
Are electrically separated from the gate electrode 32 via the second insulating film 33. As shown in FIG. 1, the upper surface of the source electrode 34 is covered with a protective film (passivation film) 35 made of, for example, SiO ₂ or a resin sealing body (not shown). The protective film 35 is formed on the source electrode 34.
And so on, for example, a low-temperature CV
It is formed by an insulating film forming method under a low temperature condition such as a method D.

In particular, the power MOS according to this embodiment
In the FET 20, as described above, the present invention is applied to
Drift region 2 between LR25A, 25B, 25C
2 so as to face the upper surface (one main surface 21A) of the first
Through the insulating film 26, the first annular conductive films 27A, 27B,
27C and 27D are formed. As shown in FIG.
Outside the group of body regions 23, three rectangular annular FLRs 25A, 25B, and 25C formed apart from each other are formed concentrically. And the silicon substrate 2
1 on one main surface 21A, between the innermost FLR 25A and the body region 23, between the innermost FLR 25A and the second FLR 25B, between the second FLR 25B and the outermost FLR 25C, and Outer FLR25C and EQ
Drift regions 22 are annularly exposed between R diffusion regions 30. The upper surface of the annularly exposed drift region 22 and the upper surfaces of the FLRs 25A, 25B, and 25C, and the outer peripheral side of the body region 23 and the inner peripheral side of the EQR diffusion region 30 are covered with a first insulating film 26. The first insulating film 26 is, for example, a silicon oxide film formed by well-known thermal oxidation, and is a film from which mobile ions cannot be completely removed.

In this embodiment, the first insulating film 2
6, four first conductive films 2 spaced apart from each other
7A, 27B, 27C and 27D are made of the same conductive material as the gate electrode 32, doped polysilicon, refractory metal, silicide (WSi ₂ , TiSi ₂ , MoS) of refractory metal.
i ₂₎ it is formed like the like, or polycide. The four first conductive films 27A, 27B, 27C, and 27D may be used in an electrically floating state. Four first
If the conductive films 27A, 27B, 27C, 27D are electrically connected to each other, they function as floating equipotential electrodes. However, the four first conductive films 27A, 27B, 2
7C and 27D may be electrically independent of each other so as to have an independent floating potential. EQR
The wiring film 36 may be configured to be operable in a floating state.

Although there is a disadvantage that the circuit configuration becomes complicated,
The four first conductive films 27A, 27B, 27C, 27 are formed by using an independent power source or a power source obtained by dividing the operating power source by resistance.
A configuration in which a constant bias is applied to D may be used. This constant bias is caused by whether there are negative movable ions or positive movable ions in the first insulating film 26, or whether the drift region 22
The polarity may be selected in consideration of the type or the n-type. Further, the first conductive films 27A, 27B, 27
Different biases may be applied so as to increase or decrease sequentially from inside to outside of C and 27D. A configuration in which a constant bias is applied to the EQR wiring film 36 can also be adopted.

The innermost first conductive film 27A is
A band-shaped conductive film formed in a ring shape so as to face the ring-shaped drift region 22 exposed between the body region 23 and the innermost FLR 25A with the first insulating film 26 interposed therebetween.
The inner peripheral edge and the outer peripheral edge of the first conductive film 27A are extended until they face the body region 23 and the innermost FLR 25A, respectively.

The second innermost first conductive film 27B is opposed to the annular drift region 22 exposed between the innermost FLR 25A and the second FLR 25B via the first insulating film 26. This is a strip-shaped conductive film formed on the substrate. The inner peripheral edge and the outer peripheral edge of the first conductive film 27B are extended until they face the innermost FLR 25A and the second FLR 25B, respectively.

The third inner conductive film 27C is formed in an annular shape so as to face the annular drift region 22 exposed between the second FLR 25B and the outermost FLR 25C via the first insulating film 26. It is a formed strip-shaped conductive film.
The inner peripheral edge and the outer peripheral edge of the first conductive film 27C are extended until they face the second FLR 25B and the outermost FLR 25C.

The outermost first conductive film 27D is connected to the outermost F
A band-shaped conductive film is formed in a ring shape so as to face the ring-shaped drift region 22 exposed between the LR 25C and the EQR diffusion region 30 with the first insulating film 26 interposed therebetween. This first
The inner peripheral edge of the conductive film 27D extends to the outermost FLR 25C. However, the outer peripheral side edge of the first conductive film 27D is terminated at a portion opposed to substantially the center of the drift region 22 exposed between the outermost FLR 25C and the EQR diffusion region 30, and is electrically connected to the EQR diffusion region 30. Are separated from the EQR wiring film connected to the second wiring.

These first conductive films 27A, 27B, 27
C and 27D are covered with the second insulating film 33 as shown in FIG. The second insulating film 33 is a film in which mobile ions cannot be completely removed like the first insulating film 26. Further, the second insulating film 33 is covered with the protective film 35 covering the source electrode 34 described above. The protective film 35 is also formed of the first and second insulating films 26, 3
As in the case of No. 3, it is a film from which mobile ions cannot be completely removed.

Power MOSF according to an embodiment of the present invention
In the ET 20, the power semiconductor device is turned off without applying a positive voltage to the gate electrode 32, and a voltage (reverse bias voltage) for increasing the potential on the drain electrode side between the drain electrode 29 and the source electrode 34. Is applied, pn formed at the interface between the body region 23 and the drift region 22
The junction is biased in the reverse direction. From this pn junction,
The depletion layer spreads mainly on the drift region 22 side with a low impurity density. Here, the depletion layer that increases from the pn junction, which increases the reverse voltage, gradually expands toward the outside of the element formation region of the silicon substrate 21, and the innermost FLR2.
From 5A, it sequentially reaches the outermost FLR 25C. That is,
The depletion layer extends to the outer peripheral side of the element formation region so as to fill the drift region 22 formed between the adjacent FLRs 25A, 25B, 25C. Thereby, the body region 23
The electric field concentration in the corner portion (curved portion) is reduced, and the breakdown voltage between the gate and the drain and the breakdown voltage between the source and the drain can be improved. At this time, FLR25A, 25
B, 25C, the first insulating film 26 and the first insulating film 2
The movement of mobile ions contained in various insulating films such as a second insulating film 33 that covers the protective film 6, a protective film 35, and a resin sealing body (not shown) that covers the protective film 35 is prevented by the first insulating film. The first conductive films 27A, 27B formed on the film 26,
It can be suppressed by 27C and 27D. That is,
The movable ions move in the insulating film under the influence of the potential distribution and the ambient temperature accompanying the operation of the power semiconductor device, but the first conductive film 27 </ b> A formed on the upper surface of the drift region 22.
27B, 27C and 27D function as so-called "equipotential rings", and their movements are clamped. As a result, the effect of the mobile ions contained in the insulating film on the depletion layer can be prevented by the first conductive films 27A, 27B, 27C, and 27D. Therefore, a plurality of FLRs 25A, 2
The drift region 22 formed between 5B and 25C can be prevented from being changed in carrier density on the surface due to the movement of the mobile ions contained in the insulating film.

The first conductive films 27A, 27B, 27C,
27D has an effect of preventing ions from entering from the outside. As a result, the expansion of the depletion layer extending from the pn junction becomes constant without being affected by the movement of mobile ions, and the gate-drain breakdown voltage and the operating voltage (junction temperature), operating voltage, etc. Variations in the source-drain breakdown voltage can be prevented.

(Other Embodiments) The embodiments of the present invention have been described above. However, it should be understood that the description and drawings constituting a part of the disclosure of the above embodiments limit the present invention. Should not be. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, in the above embodiment, a double diffusion type MOSFET (DMOS) is exemplified as a power semiconductor device, but a gate insulating film and a gate electrode are buried in U-grooves and V-grooves such as UMOS and VMOS. The structure may be sufficient. Further, a silicon oxide film (SiO ₂ ) is used for the gate insulating film.
Instead of silicon nitride (Si ₃ N ₄ ) monolayer or S
A power IGFET having a composite film of iO ₂ and Si ₃ N ₄ may be used. Further, in addition to power IGFETs such as power MOSFETs, IGBTs and power MOSSIs
T, power JFET, power JSIT, power BJT,
The present invention can be applied to various power semiconductor devices such as a GTO thyristor, an SI thyristor, an emitter switched thyristor (EST), a MOS control thyristor (MCT), and a base resistance control thyristor (BRT).

Also, in the above embodiment, as shown in FIG. 2, 3 × 3 = 9 body regions 23 have been described. However, in the embodiment, 4 × 4 = 16.5 × 5. = 2
... 10 × 10 = 100,... Also, 4
An anisotropic array such as × 8, 10 × 30 may be used. Also,
The source region 24 inside the body region 23 close to (adjacent to) the innermost FLR 25A may be omitted. Furthermore,
Of course, the number of the body regions 23 may be less than nine. The body region 23 does not have to have a substantially flat lower surface as shown in FIG. 1, but may have a so-called deep base structure in which a lower central portion is selectively formed deep. In the above embodiment, the top surface of the body region 23 is formed in a square island shape, but may be formed in a stripe shape or a lattice shape in addition to a rectangular, hexagonal, octagonal, or circular island shape.

Further, in the above embodiment, the FLR 25
Although A, 25B and 25C are formed at equal intervals, it is needless to say that they are not necessarily at equal intervals. Also, in FIG. 1, the innermost FLR
25A and body region 23, outermost FLR 25
Although the interval between C and the EQR diffusion region 30 is drawn equal to the interval between adjacent FLRs, design changes can be made as appropriate, such as a configuration in which these intervals are gradually increased toward the outside of the element formation region. These intervals can be set arbitrarily based on conditions such as desired withstand voltage and chip size.

Further, in the above embodiment, a silicon substrate is used, but other semiconductor materials such as silicon carbide (SiC) other than silicon can be used. Although a silicon substrate (base material) having a relatively high specific resistance is used as it is for the first semiconductor region 22, a silicon substrate having a low specific resistance is used for the sixth semiconductor region 28, and a relatively high specific resistance silicon substrate is formed thereon. An epitaxial growth layer may be formed, and this epitaxial growth layer may be used as the first semiconductor region 22.

As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0049]

As is apparent from the above description, according to the present invention, the movement of mobile ions in the insulating film is suppressed, and the mobile ions are prevented from affecting the depletion layer.

Therefore, according to the present invention, it is possible to provide a highly reliable power semiconductor device in which the withstand voltage is not affected by the environmental temperature, the operating temperature, the operating voltage and the like, and the change with time is small.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a power semiconductor device (power MOSFET) according to an embodiment of the present invention.

FIG. 2 is a plan view (top view) of one main surface of a silicon substrate in a power semiconductor device (power MOSFET) according to an embodiment of the present invention. In FIG. 2, the illustration of the insulating film, the source electrode, and the like of the power MOSFET 20 is omitted, and the pattern of the underlying semiconductor region is mainly shown.

FIG. 3 is a plan view showing the entire second semiconductor region on one main surface side of the silicon substrate in the power semiconductor device (power MOSFET) according to the embodiment of the present invention;

FIG. 4 is a sectional view of a conventional power semiconductor device.

[Explanation of symbols]

 Reference Signs List 20 power MOSFET (power semiconductor device) 21 silicon substrate (semiconductor base) 22 first semiconductor region (drift region) 23 second semiconductor region (body region) 24 third semiconductor region (source region) 25A, 25B, 25C FLR ( 4th semiconductor region) 26 1st insulating film (field insulating film) 27A, 27B, 27C, 27D 1st conductive film 28 6th semiconductor region (drain region) 29 drain electrode 30 EQR diffusion region (5th semiconductor region) 31 gate Insulating film 32 Gate electrode 33 Second insulating film (interlayer insulating film) 34 Source electrode 35 Protective film (passivation film) 36 EQR wiring film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/78 655 H01L 29/78 655Z 29/744 29/74 C 29/74 M 21/337 29/80 C 29/808

Claims (9)

[Claims] A first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type disposed inside the first semiconductor region on one main surface side of the first semiconductor region; A third semiconductor region of a first conductivity type; a fourth semiconductor region of the second conductivity type arranged in an annular shape surrounding the second and third semiconductor regions on the one main surface side; And a first conductive film disposed on the insulating film in a region from the second semiconductor region to the fourth semiconductor region. Power semiconductor device. 2. A fifth semiconductor region of a first conductivity type which is annularly disposed on the one main surface and surrounds the fourth semiconductor region on an outer peripheral side of the fourth semiconductor region, and an upper portion of the insulating film. 2. The power semiconductor device according to claim 1, further comprising: a second conductive film disposed at an opening of the insulating film and connected to the fifth semiconductor region at an opening of the insulating film. 3. The power semiconductor device according to claim 1, wherein the fourth semiconductor region is arranged as a plurality of concentric rings separated from each other. 4. A plurality of first conductive films spatially separated from each other above the fourth semiconductor region are disposed above the first semiconductor region located between the plurality of concentric rings. The power semiconductor device according to claim 3, wherein: 5. The power semiconductor device according to claim 4, wherein said plurality of first conductive films are electrically connected. 6. The method according to claim 1, wherein the first conductive film is used in a floating state.
Item 7. A power semiconductor device according to Item 1. 7. The third semiconductor region is a first main electrode region arranged inside the second semiconductor region, and the third semiconductor region is provided on the other main surface of the first semiconductor region facing the one main surface, 7. The power semiconductor device according to claim 1, further comprising a sixth semiconductor region serving as a second main electrode region. 8. A semiconductor device further comprising: a gate insulating film disposed on a surface of the second semiconductor region between the third semiconductor region and the first semiconductor region; and a gate electrode on the gate insulating film. The power semiconductor device according to claim 7, wherein: 9. The semiconductor device according to claim 1, wherein a plurality of the second semiconductor regions are arranged as a pair facing each other, and the third semiconductor region is arranged between the paired second semiconductor regions. Claims 1-6
The power semiconductor device according to claim 1.