JP2007134421A - Vertical semiconductor device such as power mosfet and igbt, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure for improving resisting pressure in a vertical semiconductor device such as power MOS-FET and an IGBT element, and to provide a manufacturing method of the device. <P>SOLUTION: The vertical semiconductor device such as MOS-FET and the IGBT element has the structure where gate wiring is selectively formed on a main face of a drain region through a source electrode and an insulating layer as an opposite electrode. A mask for forming a source region is corrected, and a diffusion layer for maintaining resisting pressure is formed in a drift layer just below gate wiring in an island shape by diffusion in the same process as source formation. Extension is suppressed in a depletion layer to a source electrode direction of the drift layer. Resisting pressure deterioration is improved in concentration of an electric field, and resisting pressure is improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure of a semiconductor device such as a power MOSFET or IGBT having improved breakdown voltage and a method for manufacturing the same.

As a conventional technique of this type, Patent Document 1 discloses a technique relating to a breakdown voltage improvement.
In paragraph (0008), “FIG. 1 (FIG. 5 of this document) is a cross-sectional view of a high voltage MOS transistor according to the present invention. In this example, an N-type lateral MOS transistor is illustrated. , 11 is a P-type substrate, 26 is a drain / drift region layer provided on this substrate, and is formed by stacking N-type epitaxial layers, and 12 is an element isolation provided on the drain / drift region layer 26. For example, the oxide film is formed of LOCOS (Local Oxidation of Silicon) having a thickness of about 1 μm, and 18 is an interlayer film (insulating film) formed on the oxide film 12. There is a description that the drift region layer 26 may be formed of a diffusion layer in addition to the case where the epitaxial layers are stacked and formed.
In paragraph (0009), “14 is a source electrode formed on the substrate 11, 16 is a drain electrode, and 17 is a gate electrode disposed between the source electrode 14 and the drain electrode 16. The drain electrode 16 is disposed away from the source electrode 14 and the gate electrode 17. Here, the area between the gate electrode 17 and the drain electrode 16 is called a drain / drift region. The high voltage can be absorbed by the depletion layer extending into this drain / drift region layer. "
In paragraph (0011), “27a, 27b, 27c are island-like shallow P layers (N layers if the substrate 11 is N type) provided on the surface of the drain / drift region layer 26, which is a feature of the present invention. In this example, the island-shaped shallow P layer 27 has a concentration of 1 × 10 ¹⁶ (/ cm ³ ) and a depth of 1 μm, for example. The concentration of the drain / drift region layer 26 is 2 × 10 ¹⁵ (/ cm ³ ) and the thickness is 4 μm, and the length between the drain electrode and the source electrode (drain / drift region) is about 50 μm ”.
Paragraph (0012) is a diagram showing the electric field distribution when a high voltage is applied between the drain electrode 16 and the source electrode 14 in FIG. 2 (FIG. 7 in this document), and contrasts with the case where the P layer is configured. Is shown. "
In the paragraph (0013), “In FIG. (B), the electric field is concentrated at two locations immediately below the gate electrode 17 and immediately below the drain electrode 16. On the other hand, the structure of the present invention shown in FIG. In the case of (1), the electric field is concentrated at four locations because the potential enters between the divided shallow P layers 27a, 27b, and 27c, and four peaks appear, whereby the electric field concentration is dispersed. The drain voltage can withstand even higher voltages, and the breakdown voltage can be improved. "
In paragraph (0014), “the effect of providing a shallow P layer on the surface of the drain / drift region layer 26 will be described. The on-resistance of the high voltage MOS transistor is determined by the resistance of the drain / drift region layer”. In paragraph (0015), “In order to lower the on-resistance of the MOS transistor, the epitaxial concentration Nepi should be increased (increased), but if this is increased, the depletion layer in the drain / drift region layer will not be elongated. When a shallow P layer is provided on the surface of the drain / drift region layer, the depletion layer in the drain / drift region layer is easily extended, and even if the epitaxial concentration N epi is increased, high breakdown voltage is absorbed. It can be done ".

In paragraph (0020), “FIG. 5 (not shown in this document) is a diagram showing an example of a method of manufacturing a high voltage MOS transistor according to the present invention. A process after the process of forming the island-shaped P layer on the surface of the drift region layer is shown, (a) shows a state where the gate electrode 17 is formed on the oxide film (LOCOS) 12. 5A, a photoresist film 31 serving as a mask is applied on the oxide film (LOCOS) 12 and the gate electrode 17, and a photoresist film corresponding to a position where an island-shaped shallow P layer is formed as shown in FIG. The thickness of the photo resist film 31 is thick enough to withstand high energy ion implantation, for example, about three times as thick as usual. "
In the paragraph (0021), “as shown in (c), boron ions are implanted into the drain / drift region layer 26 from the upper part of the photo resist film. The ion implantation is performed through the oxide film 12. Subsequently, the photoresist film 31 is removed, and the island-shaped P layer 27 formed on the surface of the drain / drift region layer 26 is annealed to a predetermined depth (for example, 1 μm) ”.

“JP-A-9-82960”, name “high voltage MOS transistor and manufacturing method thereof”

  In the paragraph (0021), “as shown in (c), boron ions are implanted into the drain / drift region layer 26 from the upper part of the photo resist film. The ion implantation is performed through the oxide film 12. Therefore, it is assumed that high energy implantation equipment for ion implantation is introduced as described. In order to complete a product at a low cost, it is a challenge to create a manufacturing method and a semiconductor device structure that establishes a technique for improving the breakdown voltage without introducing a new high energy injection facility.

  By eliminating the production process that would otherwise be possible without introducing ion implantation equipment, and modifying only the mask shape, the semiconductor device that can be used in the conventional manufacturing process can be realized with the structure described below. With respect to claim 1, as a technique applied to an IGBT having a basic structure of pnpn, an anode electrode, an anode layer of a high-concentration first conductivity type (p + type) semiconductor, a drift of a second conductivity type (n− type) semiconductor The layers are stacked in the order of the cathode region of the high-concentration first conductivity type (p + type) semiconductor, and the gate wiring is selectively formed in the stripe structure or the mesh structure through the gate oxide film on the drift layer excluding the cathode region. In the vertical semiconductor device, the first conductivity type (p− type) semiconductor or the high concentration first conductivity type (p + type) semiconductor is provided in the drift layer of the second conductivity type (n− type) semiconductor immediately below the gate wiring. A vertical semiconductor device characterized in that the withstand voltage diffusion layer is arranged in an island shape to improve the withstand voltage.

With respect to claim 2, this is the case when applied to a MOSFET,
The drain electrode, the drain layer of the high-concentration first conductivity type (p + -type) semiconductor, the drift layer of the second conductivity type (n − -type) semiconductor, and the source region of the high-concentration first conductivity type (p + -type) semiconductor In a vertical semiconductor device in which gate wiring is selectively formed in a stripe structure or mesh structure on the drift layer excluding the source region via a gate oxide film, the second conductivity type (n -Diffusion layer for maintaining the breakdown voltage of the first conductivity type (p-type) semiconductor or the high-concentration first conductivity type (p + type) semiconductor is arranged in an island shape in the drift layer of the semiconductor to improve the breakdown voltage. The vertical semiconductor device is characterized by this.

  3. The vertical semiconductor device according to claim 1, wherein the withstand voltage maintaining diffusion layers arranged in the form of islands are island-shaped diffusion layers arranged at a dimension interval equal to or less than an interval between cells. It was.

  In the case of claim 4, the withstand voltage maintaining diffusion layer arranged in the shape of an island is a withstand voltage maintaining diffusion layer of the first conductivity type semiconductor, which is arranged as one plane with the islands approaching and integrated. A vertical semiconductor device according to claim 1.

In the case of claim 5,
In order to form a breakdown voltage maintaining diffusion layer arranged in an island shape, there is no need to add a new process other than using a mask modified so that the source region is simultaneously diffused in the diffusion process. 5. A method of manufacturing a vertical semiconductor device having a structure according to claim 1, which is a layer forming method.

  The mask for forming the source region is modified to form a breakdown voltage maintaining diffusion layer in the form of islands by diffusing in the same process as the source formation, suppressing the expansion of the depletion layer toward the source electrode of the drift layer, and electric field concentration As a result, the pressure drop was suppressed and the pressure resistance was improved. For this reason, the manufacturing process can remain the same except for mask correction for improving the breakdown voltage. Therefore, the target 600V class has been achieved without adding the high-energy ion implantation process which has been expensive in order to tighten the control in manufacturing. The pressure resistance was achieved.

  1 and 3, the structure of an apparatus according to an embodiment of the present invention will be described. The drain electrode 1, the drain layer 2 of the high-concentration first conductive semiconductor, the drift layer 3 of the second conductive semiconductor, the high-concentration first A source region 5 of one conductivity type semiconductor is stacked in this order, and a diffusion layer 8 for maintaining a withstand voltage of the first conductivity type semiconductor or the high concentration first conductivity type semiconductor is provided in the drift layer in an island shape at the same time as the source region formation. . A gate wiring 6 is selectively formed in a stripe structure or a mesh structure on the drift layer 3 excluding the source region 5 via a gate oxide film 7, and as a result, the breakdown voltage maintaining diffusion layer 8 is directly below the gate wiring 6. The semiconductor device is characterized by being arranged in an island shape. 9 is a gate electrode (FIG. 3), 10 is a source electrode, and 13 is an interlayer insulating layer. This semiconductor device is turned OFF because the depletion layer 11 is formed at the junction surface between the p + type drain layer 2 and the n − type drift layer. A drain electrode 1 is formed on the other main surface of the drain layer 2 to complete the semiconductor device.

In order to flatten the depletion layer 11, the first conductivity type semiconductor or the high-concentration first conductivity type semiconductor withstand voltage maintaining diffusion layer 8 is disposed inside the drift layer 3 of the second conductivity type semiconductor, and the interval G is equal to or less than the cell interval. The improvement in pressure resistance was measured by providing it in an island shape while maintaining the same. For example, when the cell spacing is 30 μm and the inter-island size of the breakdown voltage maintaining diffusion layer is 15 μm, the breakdown voltage is 600 V as shown in FIG. This is about 2.4 times the breakdown voltage of 250 V shown in FIG. 6 when the breakdown voltage maintaining diffusion layer 8 is not formed.
FIG. 3A shows a conventional example in which the breakdown voltage maintaining diffusion layer 8 is arranged at a wide interval, showing the case where the elongation of the depletion layer depicted by the dotted line in FIG. 3A is larger than that in FIG. 3B. In the semiconductor device, the depletion layer 11 is not distributed flat and extends in the source direction as indicated by the dotted line in FIG. 3A, so that the equipotential surface has a shape of an independent peak. It was found that the electric field concentrated and the breakdown voltage decreased. In this case where the breakdown voltage maintaining diffusion layer 8 is arranged at a narrower interval, as shown in FIG. 3 (b) where the elongation of the depletion layer drawn by the dotted line is smaller than the above, the depletion layer 11 drawn by the dotted line is Since it approaches flatness, the factor of decreasing the breakdown voltage is suppressed, contributing to the improvement of the breakdown voltage.

  Regarding dielectric breakdown due to electric field concentration, “basic voltage design is to design a uniform electric field distribution so that the electric field is not concentrated locally”.

  The structure of the device according to the second embodiment of the present invention will be described with reference to FIG. 2. The drain electrode 1, the drain layer 2 of the high-concentration first conductivity type (p + type) semiconductor, and the second conductivity type (n− type). A semiconductor drift layer 3 and a high-concentration first conductivity type (p + -type) semiconductor source region 5 are stacked in this order, and a stripe structure or a mesh structure is formed on the drift layer 3 excluding the source region via a gate oxide film 7. A gate wiring 6 is selectively formed, and as a result, a first conductive type (p − type) semiconductor or a high conductivity is formed inside the drift layer 3 of the second conductive type (n − type) semiconductor immediately below the gate wiring 6. A semiconductor device in which the breakdown voltage maintaining diffusion layer 8 of the first conductivity type (p + type) semiconductor is arranged in an island shape. 10 is a source electrode, 11 is a depletion layer, and 13 is an interlayer insulating film. A drain electrode 1 is formed on the other main surface of the drain layer 2 to complete the semiconductor device.

  The breakdown voltage maintaining diffusion layer 8 arranged in an island shape is a vertical semiconductor device which is an island-like diffusion layer arranged at a dimensional interval equal to or smaller than the inter-cell interval size.

  The breakdown voltage maintaining diffusion layer 8 arranged in the shape of the island is, for example, a polysilicon window (minimum drilling dimension rule of 5 microns) and a diffusion layer formed as a diffusion mask hole interval of 4 microns. A vertical semiconductor device which is a diffusion layer for maintaining a withstand voltage of a first conductivity type (p-type) semiconductor, which is close and integrated and arranged as one plane, is obtained.

  The breakdown voltage maintaining diffusion layer 8 arranged in an island shape is a vertical semiconductor device which is a diffusion layer having a thickness of 1 to 3 μm. FIG. 4 is a voltage / current characteristic diagram according to the embodiment of the present invention. As can be seen from the graph of FIG.

  The breakdown voltage maintaining diffusion layer 8 arranged in an island shape uses a mask modified so as to be diffused simultaneously with the step of forming the source region 5 by diffusion, and there is no need to add a new step. It was set as the manufacturing method.

  The complexity of the conventional process disclosed in Patent Document 1 is eliminated, and others can be manufactured in the same process as the conventional process only by correcting the mask.

1 is a structural diagram showing a first embodiment according to the present invention. It is a structural diagram showing a second embodiment according to the present invention. It is a principal part detail drawing by 1st Embodiment by this invention. It is a voltage-current characteristic figure by embodiment by this invention. 1 is a structural diagram of a semiconductor device according to a technique disclosed in Patent Document 1. FIG. It is a voltage-current characteristic view by a conventional semiconductor device. It is explanatory drawing (FIG. 2 of patent document 1) of the conventional semiconductor device.

Explanation of symbols

1 drain electrode 2 drain layer 3 drift layer 4 depletion layer 5 source region 6 gate wiring (conductor)
7 Gate oxide film 8 Diffusion layer 9 for maintaining a breakdown voltage Gate electrode 10 Source electrode 11 P-type substrate 12 Oxide film 13 Interlayer insulating film 14 Source electrode 16 Drain electrode 17 Gate electrode 18 Interlayer film 26 Drain / drift region layer 27a Shallow island shape P layer 27b Insular shallow P layer 27c Insular shallow P layer G spacing

Claims (5)

  Applicable to IGBTs with a basic structure of pnpn, anode electrode, anode layer of high-concentration first conductivity type (p + type) semiconductor, drift layer of second conductivity type (n− type) semiconductor, high-concentration first conductivity type (p + type) In a vertical semiconductor device in which gate wirings are selectively formed in a stripe structure or a mesh structure on the drift layer excluding the cathode region, with a gate oxide film interposed therebetween, in a stripe structure or a mesh structure. In the drift layer of the second conductivity type (n− type) semiconductor, a breakdown voltage maintaining diffusion layer of the first conductivity type (p− type) semiconductor or the high concentration first conductivity type (p + type) semiconductor is arranged in an island shape And a vertical semiconductor device characterized in that the withstand voltage is improved.   Adapted to MOSFET, drain electrode, drain layer of high-concentration first conductivity type (p +) semiconductor, drift layer of second conductivity type (n-type) semiconductor, high-concentration first conductivity type (p + type) semiconductor In a vertical semiconductor device in which a gate wiring is selectively formed in a stripe structure or a mesh structure on a drift layer excluding the source region, and in a stripe structure or a mesh structure, the first layer immediately below the gate wiring is stacked. A first-conductivity-type (p-type) semiconductor or a high-concentration first-conductivity-type (p +) semiconductor withstand voltage maintaining diffusion layer is arranged in an island shape in the drift layer of a two-conductivity type (n-type) semiconductor; A vertical semiconductor device characterized in that withstand voltage is improved.   3. The vertical semiconductor device according to claim 1, wherein the withstand voltage maintaining diffusion layers arranged in an island shape are island-shaped diffusion layers arranged at a dimension interval equal to or less than an interval between cells.   4. The breakdown voltage maintaining diffusion layer disposed in the shape of an island is a p-type semiconductor breakdown voltage maintaining diffusion layer that is arranged in one plane by bringing the islands close together. The vertical semiconductor device described.   The formation process of the withstand voltage maintaining diffusion layer arranged in an island shape is performed simultaneously with the source region formation by using a mask modified so as to be diffused simultaneously when forming the source region by diffusion, and there is no need to add a new process. The method for manufacturing a vertical semiconductor device according to claim 1, wherein the method is a step of diffusing and forming in the step.

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