JP2006344802A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which uses an SiC semiconductor substrate and has a high breakdown voltage, and also to provide a method for manufacturing the semiconductor device. <P>SOLUTION: An active region 1 functioning as a field effect transistor is formed on an SiC semiconductor substrate 5. An inner ring 16 fixed to the same potential as a source electrode 14 is formed at the peripheral edge of the active region 1. An electrically floating ring 2 is formed to be spaced by a distance from the inner ring 16. An outer ring 3 fixed to the same potential to the SiC substrate 5 is provided at the peripheral edge of the substrate 5. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a SiC (silicon carbide) semiconductor substrate and a method for manufacturing the same.

  Conventionally, a power MOSFET using a Si (silicon) semiconductor substrate has been used for a power source (especially one using an inverter) of a household consumer device or an electric vehicle (for example, a hybrid vehicle). In the field of power electronics, loss in devices during power conversion is a problem, and low loss is an issue, but it is said that power MOSFETs using Si materials are approaching the technical limits. As a result, it is difficult to achieve higher efficiency.

Therefore, research on application of SiC semiconductors to power devices is underway. SiC is a compound with excellent physical properties such as 3 times the band gap of Si and 10 times the dielectric breakdown electric field of Si. When applied to power devices, it realizes a device with lower loss than Si-based power devices. it can.
JP 2000-22137 A

However, the power MOSFET using the SiC semiconductor substrate has a problem that it is difficult to realize a stable high voltage device due to breakdown due to electric field concentration around the active region.
Accordingly, an object of the present invention is to provide a high breakdown voltage semiconductor device using a SiC semiconductor substrate and a method for manufacturing the same.

  In order to achieve the above object, an invention according to claim 1 includes a first conductivity type SiC semiconductor substrate (5) and an active region (1) formed on the SiC semiconductor substrate and functioning as a field effect transistor. An electrically floating floating ring (2) formed by introducing an impurity of a second conductivity type different from the first conductivity type into a ring-shaped region surrounding the active region on the SiC semiconductor substrate; And an outer ring (3) formed by introducing the first conductivity type impurity into a ring-shaped region surrounding the floating ring at a predetermined interval from the floating ring on the SiC semiconductor substrate. A semiconductor device characterized by the above. The alphanumeric characters in parentheses indicate corresponding components in the embodiments described later. The same applies hereinafter.

  In this configuration, the SiC semiconductor substrate functions as the drain of the field effect transistor, and the outer ring is fixed at the same potential as the SiC semiconductor substrate, contributing to stabilization of the electric field around the active region. In the present invention, the depletion layer extending from the active region can be expanded to the outer ring side by the action of the floating ring provided between the active region and the outer ring. As a result, the bending of the depletion layer around the active region can be reduced, so that the concentration of the electric field between the active region and the outer ring can be reduced. As a result, a stable high breakdown voltage can be obtained. The achievable withstand voltage is, for example, 600 to 2000V.

In addition, since the floating ring is provided between the active region and the outer ring, a stable high breakdown voltage can be obtained even if the distance between the active region and the outer ring is shortened. This also has the advantage that the semiconductor device can be reduced in size. For example, the distance between the active region and the outer ring can be, for example, 30 μm or more and 150 μm or less.
The floating ring and the outer ring are preferably formed so that the distance between them is almost constant over the entire circumference.

The floating ring may be composed of a plurality of multiple rings arranged at intervals.
The invention according to claim 2 further includes an inner ring (16) formed on the SiC semiconductor substrate by introducing the impurity of the second conductivity type into a ring-shaped region at the periphery of the active region. The semiconductor device according to claim 1. According to this configuration, the bending of the depletion layer around the active region can be further relaxed, so that a more stable high breakdown voltage can be achieved.

The inner ring and the floating ring are preferably formed at almost equal intervals throughout the entire circumference. Furthermore, it is preferable that the inner ring and the outer ring are formed at almost equal intervals throughout the entire circumference.
Although the inner ring may be in an electrically floating state (floating), as described in claim 3, a wiring member (which has the same potential as the source of the field effect transistor) in the inner ring. 14) is preferably further included. Thereby, since the electric field around the active member can be further stabilized, a more stable high breakdown voltage can be achieved.

The wiring member may be integrated with a source electrode connected to the field effect transistor.
According to a fourth aspect of the present invention, there is provided a step of forming an active region (1) functioning as a field effect transistor on a first conductivity type SiC semiconductor substrate (5), and surrounding the active region on the SiC semiconductor substrate. A step of forming an electrically floating floating ring (2) by introducing an impurity of a second conductivity type different from the first conductivity type into the ring-shaped region, and the floating on the SiC semiconductor substrate Forming an outer ring (3) by introducing the first conductivity type impurity into a ring-shaped region surrounding the floating ring at a predetermined distance from the ring. It is a manufacturing method of an apparatus.

By this method, the semiconductor device having the configuration of claim 1 can be manufactured.
According to a fifth aspect of the present invention, the step of forming the active region includes a step of forming the second conductivity type well (6), and the step of forming the floating ring includes the step of forming the well; 5. The method of manufacturing a semiconductor device according to claim 4, wherein the method is performed simultaneously.

  In this method, since the floating ring can be formed simultaneously with the formation of the well, a semiconductor device that realizes a stable high breakdown voltage can be manufactured without increasing the number of steps.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is an enlarged plan view of a semiconductor device according to an embodiment of the present invention. This semiconductor device is a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) element (individual element) using SiC (silicon carbide). For example, the length in the vertical direction in FIG. 1 is about 1 mm. . This power MOSFET is provided in the central part on the SiC semiconductor substrate, and includes an active region 1 that functions as a field effect transistor. A floating ring 2 is formed at a distance from the active region 1 so as to surround the active region 1, and an outer ring 3 is formed so as to surround the floating ring 2. The distance between the active region 1 and the floating ring 2 is substantially constant throughout the entire circumference. Also, the distance between the floating ring 2 and the outer ring 3 is substantially constant throughout the entire circumference.

FIG. 2 is an enlarged cross-sectional view taken along section line II-II shown in FIG. This power MOSFET has a so-called DMOS (Double-Diffusion Metal-Oxide-Semiconductor) structure. However, in the SiC process, the double diffusion technique cannot be applied, and a device having a DMOS structure is manufactured by double-implantation.
In this embodiment, the SiC semiconductor substrate 5 is N-type and functions as the drain region of the field effect transistor. On the surface side of the SiC semiconductor substrate 5, a plurality of P-type wells 6 are formed in a lattice arrangement to form an active region 1. A drain electrode 4 made of, for example, a nickel metal film is formed on the back surface of the SiC semiconductor substrate 5.

In each P type well 6, an N ⁺ type source region 7 and a P ⁺ type region 8 surrounded by the N ⁺ type source region 7 are formed. A gate electrode 9 is formed so as to straddle the adjacent P-type well 6, and a gate insulating film 10 is interposed between the gate electrode 9 and the SiC semiconductor substrate 5. The gate electrode 9 extends between the N ⁺ -type source region 7 and the SiC semiconductor substrate 5 (region between the P-type well 6) as a drain region, and an inversion layer (channel) on the surface of the P-type well 6 Control the formation of.

Further, an interlayer film (insulating film) 11 made of, for example, silicon oxide is formed so as to cover the gate electrode 9. This interlayer film 11 further covers the region from the active region 1 to the outer ring 3. In the interlayer film 11, a contact hole 12 is formed in the central region of the P-type well 6. The contact hole 12 is formed in a region where a part of the P ⁺ type region 8 and the surrounding N ⁺ type source region 7 can be exposed. A contact metal layer 13 made of nickel, for example, is formed in the contact hole 12. A source electrode 14 (for example, made of aluminum) covering most of the substrate is formed so as to be in contact with the contact metal layer 13. Accordingly, the N ⁺ type source region 7 has the same potential as the source electrode 14. Further, since the P-type well 6 is connected to the source electrode 14 via the P ⁺ -type region 8, it has the same potential as the source electrode 14.

On the other hand, an inner ring 16 formed by introducing a P-type impurity is formed at the periphery of the active region 1. The inner ring 16 is formed over the entire circumference of the active region 1. A P ⁺ -type region 17 is formed in the inner region of the inner ring 16. A contact hole 18 corresponding to the P ⁺ type region 17 is formed in the interlayer film 11, and a contact metal layer 19 is disposed in the contact hole 18. The source electrode 14 is in contact with the contact metal layer 19. As a result, the inner ring 16 is fixed to the source potential (for example, 0 V).

  A floating ring 2 is formed on the surface of the SiC semiconductor substrate 5 around the active region 1 and is formed by introducing P-type impurities into a region spaced a predetermined distance D1 from the inner ring 16. The floating ring 2 is covered with the interlayer film 11 covering the surface of the SiC semiconductor substrate 5 and is held in an electrically floating state. The distance D1 between the inner ring 16 and the floating ring 2 is kept substantially constant over the entire circumference. The distance D1 is, for example, about 10 μm.

Further, outside ring 3 is formed on the peripheral edge (edge part) of SiC semiconductor substrate 5 at a certain distance D2 outside outer ring 16. The outer ring 3 is an N ⁺ type region formed by introducing an N type impurity into the SiC semiconductor substrate 5 at a high concentration. Therefore, outer ring 3 is fixed to the same potential (for example, 1000 V) as SiC semiconductor substrate 5 as the drain region. The distance D2 is kept substantially constant over the entire circumference. In this embodiment, the distance D2 is longer than the above-described distance D1, and is about 50 μm, for example. Further, the distance D between the inner ring 16 and the outer ring 3 is also maintained substantially constant over the entire circumference. This distance D is, for example, about 30 to 150 μm.

  On the outer ring 3, a contact hole 23 exposing a part thereof is formed in the interlayer film 11. A contact metal layer 24 is disposed in the contact hole 23. Further, a wiring member 25 in contact with the contact metal layer 24 is formed on the entire periphery of the peripheral portion of the SiC semiconductor substrate 5. Therefore, the potential of wiring member 25 is fixed to the same potential as that of SiC semiconductor substrate 5.

  According to such a configuration, the inner ring 16 is fixed at the same potential as the source, and the outer ring 3 is fixed at the same potential as the drain, thereby uniformizing and stabilizing the electric field distribution in the peripheral region of the active region 1. be able to. Further, the depletion layer 30 extending from the P-type well 6 extends toward the outer ring 3 beyond the floating ring 2 and does not cause a sharp bend. Thereby, the concentration of the electric field can be more effectively mitigated. If the floating ring 2 is not provided, the depletion layer extending from the P-type well 6 causes a sharp bend in the vicinity of the active region 1, as shown by reference numeral 30A, and the electric field concentration associated therewith can be avoided. Absent. In the configuration of the present embodiment in which the floating ring 2 is provided, such electric field concentration can be effectively reduced.

Thus, according to the configuration of this embodiment, the electric field concentration around the active region 1 can be effectively reduced, and as a result, a stable high breakdown voltage power MOSFET can be realized.
FIG. 3 is a flowchart for explaining the manufacturing process of the power MOSFET. First, P-type impurity ions (for example, aluminum ions) are selectively implanted into SiC semiconductor substrate 5 in a room temperature atmosphere, for example, and P-type well 6, inner ring 16 and floating ring 2 are formed simultaneously (step). S1).

Furthermore, P ⁺ -type regions 8 and 17 are simultaneously formed by selectively implanting P-type impurity ions (for example, aluminum ions) into the inner regions of P-type well 6 and inner ring 16 in a room temperature atmosphere. (Step S2).
Then, for example, N ⁺ -type source region 7 and outer ring 3 are formed simultaneously by selective implantation of N-type impurity ions (for example, phosphorus ions) in an atmosphere of 400 ° C. (step S3).

Thereafter, annealing (heat treatment) for activating the implanted impurity ions is performed (step S4). This annealing is, for example, heat treatment at 1725 ° C. for several minutes in an argon gas atmosphere.
Next, the gate insulating film 10 is formed by, for example, a thermal oxidation method (step S5). The film thickness of the gate insulating film 10 is about several hundreds of squares, for example.

Further, for example, a pattern of the gate electrode 9 is formed on the gate insulating film 10 by using a polysilicon film or other conductive film (step S6).
Next, contact metal layers 13, 19, and 24 (for example, made of a nickel metal film) joined to N ⁺ type source region 7 and P ⁺ type region 8 are formed (step S7). These contact metal layers 13, 19, and 24 can be formed simultaneously by, for example, forming a nickel metal film having a thickness of 600 mm by sputtering and then patterning it by lift-off.

Next, a nickel metal film as drain electrode 4 is formed on the back surface of SiC semiconductor substrate 5 by, for example, sputtering (step S8).
Subsequently, an alloying process (metal alloy) is performed (step S9). This alloying treatment is performed, for example, by rapid thermal annealing (RTA) at 1000 ° C. for 2 minutes. By such alloying treatment, the contact interfaces of the contact metal layers 13, 19, 24 and the drain electrode 4 are alloyed, and an ohmic junction can be formed.

Next, for example, an interlayer film 11 made of a silicon oxide film having a thickness of about 8000 mm is formed on the entire surface (step S10), and contact holes 12, 18, and 23 are formed by dry etching or other etching methods (step S11). ).
Then, by forming source electrode 14 made of, for example, an aluminum metal film (step S12), a power MOSFET having the structure shown in FIGS. 1 and 2 is obtained.

In this manufacturing method, the floating ring 2 can be formed simultaneously in the ion implantation process for forming the P-type well 6. In the ion implantation process for forming the N ⁺ type source region 7, the outer ring 3 can be formed simultaneously. Therefore, a stable high voltage structure can be formed without increasing the number of steps.
As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form. For example, in the above-described embodiment, the potential of the inner ring 16 is fixed to the same potential as that of the source electrode 14. However, the inner ring 16 may be an electrically floating ring (floating ring). Also in this case, the depletion layer 30 extending from the P-type well 6 can have a shape extending long toward the outer ring 3, and the electric field concentration caused by the bending of the depletion layer can be reduced.

  Further, in the above-described embodiment, one floating ring 2 is disposed between the active region 1 and the outer ring 3, but a plurality of floating rings are disposed at intervals to form a floating ring. Multiple structures may be formed. Thereby, since the depletion layer 30 can be more effectively extended toward the outer ring 3, the concentration of the electric field can be further reduced.

Further, in the above-described embodiment, the example in which the N-channel type MOSFET is formed by using the N-type SiC semiconductor substrate 5 has been described. However, the present invention relates to the P-channel type MOSFET using the P-type SiC semiconductor substrate. It can also be applied to. In this case, the conductivity type of each part in the configuration of FIG. 2 may be reversed.
Further, in the above-described embodiment, the example in which the present invention is applied to the power MOSFET has been described. However, the present invention is also applied to an SiC FET device having an IGBT (Insulated Gate Bipolar Transistor), JFET (Junction Field Effect Transistor), or other structure. The same can be applied.

  In addition, various design changes can be made within the scope of the matters described in the claims.

1 is an enlarged plan view of a power MOSFET which is a semiconductor device according to an embodiment of the present invention. It is an expanded sectional view in cutting plane line II-II shown in FIG. It is a flowchart for demonstrating the manufacturing process of the said power MOSFET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Active region 2 Floating ring 3 Outer ring 4 Drain electrode 5 SiC semiconductor substrate 6 P type well 7 N ⁺ type source region 8 P ⁺ type region 9 Gate electrode 10 Gate insulating film 11 Interlayer film 12 Contact hole 13 Contact metal layer 14 Source Electrode 16 Inner ring 17 P ⁺ type region 18 Contact hole 19 Contact metal layer 23 Contact hole 24 Contact metal layer 25 Wiring member 30 Depletion layer

Claims (5)

A first conductivity type SiC semiconductor substrate;
An active region formed on the SiC semiconductor substrate and functioning as a field effect transistor;
An electrically floating floating ring formed by introducing an impurity of a second conductivity type different from the first conductivity type into a ring-shaped region surrounding the active region on the SiC semiconductor substrate;
And an outer ring formed by introducing the first conductivity type impurity into a ring-shaped region surrounding the floating ring at a predetermined interval from the floating ring on the SiC semiconductor substrate. Semiconductor device.   2. The semiconductor according to claim 1, further comprising an inner ring formed by introducing the second conductivity type impurity into a ring-shaped region at a peripheral portion of the active region on the SiC semiconductor substrate. apparatus.   The semiconductor device according to claim 2, further comprising a wiring member that makes the inner ring have the same potential as the source of the field effect transistor. Forming an active region functioning as a field effect transistor on a first conductivity type SiC semiconductor substrate;
Forming an electrically floating floating ring by introducing an impurity of a second conductivity type different from the first conductivity type into a ring-shaped region surrounding the active region on the SiC semiconductor substrate;
And introducing an impurity of the first conductivity type into a ring-shaped region surrounding the floating ring at a predetermined interval from the floating ring on the SiC semiconductor substrate, and forming an outer ring. A method of manufacturing a semiconductor device. Forming the active region includes forming a well of the second conductivity type;
5. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the floating ring is performed simultaneously with the step of forming the well.

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