CN104362087A - Method for forming self-aligned metal silicide - Google Patents

Method for forming self-aligned metal silicide Download PDF

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Publication number
CN104362087A
CN104362087A CN201410625361.5A CN201410625361A CN104362087A CN 104362087 A CN104362087 A CN 104362087A CN 201410625361 A CN201410625361 A CN 201410625361A CN 104362087 A CN104362087 A CN 104362087A
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annealing process
metal silicide
self
metal
formation method
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肖天金
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a method for forming self-aligned metal silicide. The method has the advantages that double-step annealing processes are implemented, isotope gas of hydrogen is introduced in the second annealing process, the isotope gas of the hydrogen and trace oxygen in atmosphere react with each other, accordingly, the oxygen can be eliminated, the metal silicide can be prevented from being oxidized, surface defects (such as pyramid shapes) of the metal silicide can be reduced or prevented, and the metal silicide which has flat morphology and is excellent in uniformity can be formed; isotope atoms in the introduced isotope gas of the hydrogen can enter interfaces of the metal silicide and a silicon substrate and can be combined with Si to form new keys which are difficult to break, accordingly, defects at the interfaces can be repaired and reduced, and interface states (Dit) can be improved.

Description

The formation method of self-aligned metal silicate
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of self-aligned metal silicate.
Background technology
In semiconductor fabrication, metal silicide due to there is lower resistivity and with other materials, there is good adhesiveness and be widely used in source/drain contact and gate contact to reduce contact resistance.Dystectic metal and silicon react generation metal silicide, can be formed the metal silicide of low-resistivity by a step or multiple step anneal technique.Early stage TiSi 2because its narrow lines effect has not been suitable for the technology of 0.18um, by CoSi 2replace.CoSi 2the silicide forming same thickness needs to consume more polysilicon or silicon substrate, can not meet the demand of source and drain shallow junction and for ultra-shallow junctions; CoSi 2lower than the polysilicon lines of 45 nanometers showing obvious narrow lines effect; In 45 nanometers and following technology, due to considering of heat budget, CoSi 2formation temperature (Process temperature ranges of RTP2 is 600 DEG C ~ 800 DEG C) can not device requirement be met.Along with the raising of semiconductor process technology, particularly at 45nm and following technology node thereof, in order to obtain lower contact resistance, the alloy of nickel and nickel becomes the main material forming metal silicide.
With TiSi 2and CoSi 2compare, NiSi has following advantage: 1) silicification technics temperature low (350 DEG C ~ 750 DEG C); 2) silicon consumption low (form 1 Ni nanoparticle Si and only consume 0.83 nano Si); 3) not yet find that NiSi square resistance reduces with lines and becomes large; 4) silicide of low resistance can be formed with germanium silicon material at a lower temperature.With TiSi 2and CoSi 2similar place is the technique that NiSi also adopts two step RTP: (220 DEG C ~ 300 DEG C) and N first at a lower temperature 2carry out first step annealing in atmosphere, by the diffusion of Ni, generate the silicide mainly coexisted with Ni2Si and NiSi; Then unreacted Ni or NiPt, at a higher temperature (350 DEG C ~ 750 DEG C) and N on side wall is removed by selective etch 2carry out second step annealing in atmosphere, generate NiSi in source and drain and grid.
Disclosed in, application number is disclose a kind of self-aligned metal silicate (Salicide in the Chinese patent application of 200780015617.9, self-aligned silicide) formation method, the method selects nickel alloy as forming the material of metal silicide.Fig. 1 to Fig. 3 gives the cross-sectional view that the method forms self-aligned silicide each stage.
As shown in Figure 1, first semiconductor base 100 is provided, be formed with multiple MOS transistor (only for a MOS transistor in Fig. 1) in described semiconductor base 100, be formed with isolated area 110 between adjacent MOS transistor, in described isolated area 110, be filled with insulating material; Described MOS transistor comprises: be formed in the gate dielectric layer 104 on semiconductor base 100, the gate electrode 103 that described gate dielectric layer 104 is formed, at the side wall 105 that the both sides of described gate electrode 103 and gate dielectric layer 104 are formed, the source electrode 101 formed in described gate electrode 103 both sides semiconductor base 100 and drain electrode 102.
As shown in Figure 2, at the forming metal layer on surface 106 of described semiconductor base 100, described metal level 106 covers described source electrode 101, drain electrode 102, grid 103 and side wall 105, and the material of described metal level 106 is nickel platinum alloy.Further, can form protective layer 107 on metal level 106, the material of described protective layer 107 is titanium nitride (TiN), and be used for preventing metal level 106 oxidized, the formation of protective layer 107 is optional, can be left in the basket.
As shown in Figure 3, annealing process is carried out to described semiconductor base 100, by annealing, described source electrode 101, drain electrode 102, metal level 106 material on grid 103 surface and described source electrode 101, the silicon materials drained in 102 and grid 103 react generation metal silicide layer, are respectively 101a, 102a, 103a.By selective etch, the metal level 106 do not reacted is removed afterwards, make metal silicide layer 101a, 102a, the 103a formed be exposed to the surface of described semiconductor base 100.
In the manufacturing process of self-aligned metal silicate, pattern is smooth to be not only conducive to reducing contact resistance and series resistance with metal silicide that is that have good uniformity, and is conducive to the reliability improving device.By the self-aligned metal silicate that above-mentioned existing manufacturing process obtains; although can metal level be prevented to a certain extent oxidized by protective layers such as titanium nitrides; but still trace oxygen touches the metal silicide surface of generation in inevitable reaction atmosphere in technical process; and make it oxidized; cause metal silicide pattern defect (as pyramid shape), affect surface uniformity.
On the other hand, NBTI (Negative Bias Temperature Instability, Negative Bias Temperature Instability) is an important indicator of semiconductor device.In existing manufacturing process, there is a large amount of cavitation damages and Si-H key in the interface of metal silicide and silicon substrate, when carrying out NBTI test, Si-H key ruptures by thermal excitation, form Si dangling bonds, combine between H atom and with the release of hydrogen form, form cavitation damage further, cause the negative sense of threshold voltage to drift about, make the NBTI poor-performing of device.
Summary of the invention
In order to solve above-mentioned prior art Problems existing, the invention provides a kind of formation method of self-aligned metal silicate, to reduce the defect of metal silicide, smooth and the metal silicide had good uniformity of pattern can be obtained, simultaneously, the present invention can also improve the interface between metal silicide and silicon, improves NBTI performance.
The formation method of self-aligned metal silicate provided by the invention, it comprises the following steps:
There is provided Semiconductor substrate, described semiconductor substrate surface has a silicon area at least;
At the forming metal layer on surface of described silicon area;
Carry out first time annealing process, make described metal level and the silicon on silicon area surface that contacts with it in conjunction with formation first metal silicide layer;
After removing unreacted metal level, second time annealing process is carried out under the atmosphere of the isotope gas containing hydrogen, while described first metal silicide layer forms the second metal silicide layer, the combination with oxygen existed in the isotope gas of described hydrogen and atmosphere is with the oxygen in eliminative reaction atmosphere, and interface has Si dangling bonds between described second metal silicide layer formed and silicon area, the atom X of the isotope gas of described hydrogen also combines with Si dangling bonds, forms Si-X key.
Further, the isotope gas of described hydrogen is protium gas, deuterium or tritium gas.Preferred deuterium (D 2).
Further, in second time annealing process, the volumn concentration of isotope gas in atmosphere of hydrogen is 1-50%.
Further, in second time annealing process, the flow of carrier gas is 5-30slm (standard liter per minute), and the volumn concentration of isotope gas in atmosphere of hydrogen is 2-10%.
Further, in annealing process, the carrier gas of atmosphere is selected from nitrogen, helium or argon gas for the first time, and annealing process is selected from the one in cycle annealing technique, spike annealing process, flash anneal technique or laser annealing technique.
Further, in second time annealing process, the carrier gas of atmosphere is selected from nitrogen, helium or argon gas, and annealing process is selected from the one in cycle annealing technique, spike annealing process, flash anneal technique or laser annealing technique.
Further, described first metal silicide layer is containing high resistant phase silicide, and described second metal silicide layer is low-resistance phase silicide.
Further, described metal level is Ni.
Further, the NiPt of described metal level also containing 1-10%.
Further, described first metal silicide layer contains NiSi and Ni 2si, described second metal silicide layer contains NiSi.
Further, be also included on described metal level before annealing process for the first time and form protective layer, also comprise before second time annealing process and remove described protective layer.
Further, described protective layer is Ti or TiN.
Further, described silicon area is the source-drain area of grid and both sides thereof.
Compared with prior art, the present invention has the following advantages:
The formation method of self-aligned metal silicate of the present invention, by introducing the isotope gas of hydrogen in second time annealing process, as deuterium, the trace oxygen in itself and atmosphere is utilized to react to eliminate oxygen, prevent the metal silicide of generation oxidized, thus reduce or avoid the blemish (as pyramid shape) of metal silicide, form the metal silicide that pattern is smooth and have good uniformity; This isotope atom in the isotope gas of the hydrogen introduced, as D atom, the interface of metal silicide and silicon substrate can be entered into, Si-D key is formed with Si dangling bonds, or replace already present Si-H key formation Si-D key, thus repair and reduce the defect of interface, improve interfacial state (Dit); The Si-D key bond energy formed is greater than Si-H key, is difficult to fracture, can improves the NBTI performance of device.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention be described in detail, wherein:
Fig. 1 to Fig. 3 is each step cross-sectional view of the self-aligned metal silicate formation method of prior art;
Fig. 4 to Fig. 6 is each step cross-sectional view of the self-aligned metal silicate formation method of the embodiment of the present invention.
Embodiment
Embodiments of the invention are using existing conventional Ni as the material forming metal silicide, and based on double annealing technique, composition graphs 4 to Fig. 5, annotate the improvements of technical scheme of the present invention in detail, but technical scheme of the present invention is not limited thereto.
The formation method of the self-aligned metal silicate of the present embodiment, comprises the following steps:
Step 1, as shown in Figure 4, provides Semiconductor substrate 11, and substrate 11 surface has a silicon area, and silicon area comprises the source region 13 and drain region 14 that are formed in the grid 12 of MOS transistor and grid 12 both sides substrate 11.Grid 12 comprises the side wall 123 of gate dielectric layer 121, gate electrode layer 122 and gate dielectric layer and the formation of gate electrode layer both sides.
Before carrying out metal level deposition, preferably first prerinse is carried out to silicon chip, to make to need the surface forming described silicon area there is no impurity or oxide-film, avoid affecting the quality forming metal level and metal silicide layer.Prerinse can adopt the hydrofluoric acid etc. of dilution.
Step 2, as shown in Figure 5, the surface of described silicon area is formed Ni layer 15, Ni layer 15 cover gate 12, source region 13 and drain region 14, and the surface of grid and source-drain area is contacted with W metal, and the thickness of Ni layer 15 is .Wherein, the NiPt preferably containing 5% in Ni layer 15, the existence of nickel platinum alloy can make in the process of follow-up formation metal silicide, and nickel silicide is formed finer and close, even, and NiPt is optional, and content can be 1-10%.This step adopts the depositing operation of this area routine, and as chemical vapour deposition (CVD) or physical vapour deposition (PVD) etc., thickness can be .In other embodiments, the Ni in metal level also can be replaced by a kind of metal or alloy in Er, Yb, Pt, Ti or Co, and the first metal silicide layer generated subsequently is containing rich high resistant phase silicide, and the second metal silicide layer is low-resistance phase silicide.
Preferably, Ni layer also can deposit formation layer protective layer, as Ti or TiN, to protect Ni layer surface in subsequent technique process not oxidized, its thickness can be the technique forming protective layer also can be chemical vapor deposition method or the physical gas-phase deposition of this area routine.Protective layer does not participate in reaction in subsequent annealing process, and can be removed in the lump when removing unnecessary Ni layer.
Follow-uply carry out annealing process, the present embodiment adopts twice annealing: low temperature rta technique (RTP1) and high temperature rapid thermal annealing technique (RTP2).Below describe in detail:
Step 3, as shown in Figure 6, carries out first time annealing process, makes the silicon on Ni layer 15 and the grid contacted with it and source-drain area surface in conjunction with formation first metal silicide layer 16.Described first metal silicide layer 16 is containing NiSi and Ni 2the rich nickel phase such as Si silicide.
Carrier gas in this step atmosphere is nitrogen, and in technical process, the flow of nitrogen is 15slm.In practical application, the flow of carrier gas is preferably 5-30slm.In other embodiments, carrier gas can also be the inert gas such as helium, argon gas.This step adopts low temperature rta technique, and annealing temperature, generally within the scope of 220-300 DEG C, in the present embodiment is 290 DEG C, and annealing time, generally at 3-120s, is 25s in the present embodiment.
Step 4, by selective etch, removes unreacted Ni layer 15, prevents it from continuing to react with silicon area when second time annealing.Afterwards, under containing the atmosphere of deuterium, carry out second time annealing process, make the first metal silicide layer 16 form the second metal silicide layer, even if rich nickel phase silicide is phase-changed into single nickel phase silicide NiSi, described second metal silicide layer is NiSi.
Deuterium is introduced in the atmosphere of this step, the trace oxygen in deuterium and atmosphere is utilized to react to eliminate oxygen, prevent metal silicide oxidized, thus the blemish (as pyramid shape) of the second metal silicide layer reducing or avoid the formation of, form the second metal silicide layer that pattern is smooth and have good uniformity; In the deuterium introduced, D atomic energy enters into the interface of the silicon areas such as the second metal silicide layer and grid, Si-D key is formed with the dangling bonds of Si, also can replace already present Si-H key and form Si-D key, thus repair and reduce the defect of interface, improve interfacial state (Dit); The Si-D key bond energy formed is greater than Si-H key, is more difficult to fracture, can improves the NBTI performance of device in NBTI test.
The present embodiment provides a kind of semiconductor device with grid, there is the Si/SiO of grid oxygen and silicon substrate below grid 2interface, also there is hole and Si-H key in this interface, the D atom in the present embodiment deuterium also can enter this interface, and forms Si-D key with Si dangling bonds, or replace Si-H key formation Si-H key, thus improve Si/SiO 2interfacial state.
Carrier gas in this step atmosphere is nitrogen, and in technical process, the flow of deuterium is 2slm, and the flow of nitrogen is 15slm, and the volumn concentration of deuterium in atmosphere is 11.76%.In practical application, carrier gas and deuterium can be passed in reaction boiler tube by respective pipeline, wherein, the flow of carrier gas is preferably 5-30slm, the volumn concentration of deuterium in whole atmosphere is preferably 1-50%, is more preferably 2-10%, optimum about 5%, do not reach effect at least, cause waste at most.In other embodiments, the gas of introducing can also be other isotope gas of hydrogen, as protium gas, tritium gas, but preferred deuterium, the Si-D key that itself and Si are formed more by force, is more difficult to than protium gas rupture, and it more easily obtains than tritium gas, and cost is also lower.In other embodiments, carrier gas can also be the inert gas such as helium, argon gas.This step adopts high temperature rapid thermal annealing technique, and annealing temperature, generally within the scope of 350-750 DEG C, in the present embodiment is 390 DEG C, and annealing time, generally at 3-120s, is 25s in the present embodiment.
First time annealing process in the present embodiment adopts cycle annealing technique, in other embodiments, also can adopt other annealing processs, as the one in spike annealing process, flash anneal technique or laser annealing technique.Wherein, when adopting spike annealing process, annealing temperature is 300-400 DEG C, and annealing time is 1.5-2 second; When adopting flash anneal technique, annealing temperature is 400-650 DEG C, and annealing time is 3-100 millisecond; When adopting laser annealing technique, annealing temperature is 500-700 DEG C, and annealing time is 0.25-1.6 millisecond.
Second time annealing process in the present embodiment adopts cycle annealing technique, in other embodiments, also can adopt other annealing processs, as the one in spike annealing process, flash anneal technique or laser annealing technique.Wherein, when adopting spike annealing process, annealing temperature is 500-800 DEG C, and annealing time is 1.5-2 second; When adopting flash anneal technique, annealing temperature is 700-850 DEG C, and annealing time is 3-100 millisecond; When adopting laser annealing technique, annealing temperature is 750-900 DEG C, and annealing time is 0.25-1.6 millisecond.

Claims (10)

1. a formation method for self-aligned metal silicate, it is characterized in that, it comprises the following steps:
There is provided Semiconductor substrate, described semiconductor substrate surface has a silicon area at least;
At the forming metal layer on surface of described silicon area;
Carry out first time annealing process, make described metal level and the silicon on silicon area surface that contacts with it in conjunction with formation first metal silicide layer;
After removing unreacted metal level, second time annealing process is carried out under the atmosphere of the isotope gas containing hydrogen, while described first metal silicide layer forms the second metal silicide layer, the combination with oxygen existed in the isotope gas of described hydrogen and atmosphere is with the oxygen in eliminative reaction atmosphere, and interface has Si dangling bonds between described second metal silicide layer formed and silicon area, the atom X of the isotope gas of described hydrogen also combines with Si dangling bonds, forms Si-X key.
2. the formation method of self-aligned metal silicate according to claim 1, is characterized in that: the isotope gas of described hydrogen is deuterium.
3. the formation method of self-aligned metal silicate according to claim 1 and 2, is characterized in that: in second time annealing process, the volumn concentration of isotope gas in atmosphere of hydrogen is 1-50%.
4. the formation method of self-aligned metal silicate according to claim 3, is characterized in that: in second time annealing process, the flow of carrier gas is 5-30slm, and the volumn concentration of isotope gas in atmosphere of hydrogen is 2-10%.
5. the formation method of self-aligned metal silicate according to claim 4, it is characterized in that: in annealing process, the carrier gas of atmosphere is selected from nitrogen, helium or argon gas for the first time, and annealing process is selected from the one in cycle annealing technique, spike annealing process, flash anneal technique or laser annealing technique; In second time annealing process, the carrier gas of atmosphere is selected from nitrogen, helium or argon gas, and annealing process is selected from the one in cycle annealing technique, spike annealing process, flash anneal technique or laser annealing technique.
6. the formation method of self-aligned metal silicate according to claim 1, is characterized in that: described first metal silicide layer is containing high resistant phase silicide, and described second metal silicide layer is low-resistance phase silicide.
7. the formation method of self-aligned metal silicate according to claim 6, is characterized in that: described metal level is Ni, and described first metal silicide layer is containing NiSi and Ni 2si, described second metal silicide layer is NiSi.
8. the formation method of self-aligned metal silicate according to claim 7, is characterized in that: the NiPt of described metal level also containing 1-10%.
9. the formation method of self-aligned metal silicate according to claim 1, is characterized in that: be also included on described metal level before annealing process for the first time and form protective layer, also comprises and remove described protective layer before second time annealing process.
10. the formation method of self-aligned metal silicate according to claim 1, is characterized in that: described silicon area is the source-drain area of grid and both sides thereof.
CN201410625361.5A 2014-11-07 2014-11-07 Method for forming self-aligned metal silicide Pending CN104362087A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115295615A (en) * 2022-10-08 2022-11-04 合肥晶合集成电路股份有限公司 Semiconductor structure and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
CN1185022A (en) * 1996-12-10 1998-06-17 联华电子股份有限公司 Method for mfg. electronic device with silicide having improved automatic aligning property
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* Cited by examiner, † Cited by third party
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Application publication date: 20150218