CN101197281A - Production method for silicide contact in semiconductor element - Google Patents
Production method for silicide contact in semiconductor element Download PDFInfo
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- CN101197281A CN101197281A CNA2006101191603A CN200610119160A CN101197281A CN 101197281 A CN101197281 A CN 101197281A CN A2006101191603 A CNA2006101191603 A CN A2006101191603A CN 200610119160 A CN200610119160 A CN 200610119160A CN 101197281 A CN101197281 A CN 101197281A
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Abstract
The invention discloses a manufacture method for silicide contact in semi-conductor device, which comprises the following steps of: providing a semi-conductor substrate with a device layer; forming a metal layer on the semi-conductor substrate; annealing the metal layer; selectively etching the metal layer by mixed solution of sulphuric acid and oxyful. The manufacture method of the invention can avoid the drawback problem caused by corrosion of the bottom of side wall by corrosive solution during silicide contact manufacture process.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the manufacture method of silicide contacts in particularly a kind of semiconductor device.
Background technology
The metal of infusibility and silicon react together and fuse the formation metal silicide, can form the metal silicide of low-resistivity by a step or multistep annealing process.Metal silicide is widely used in the source drain contact and contacts with grid and reduce contact resistance owing to it has lower resistivity and has good bond properties with other material.Number of patent application is the manufacture method that 03145935.8 Chinese patent discloses a kind of metal silicide contact.Fig. 1～Fig. 5 is the generalized section of the manufacture method of this patent disclosure.As shown in Figure 1, at first provide a substrate 100 with isolated groove 101, form insulating barrier 102 and conductor layer 104 in described substrate 100, wherein said conductor layer 104 materials can be polysilicon or doped polycrystalline silicon.As shown in Figure 2, form grid 104a and gate insulation layer 102a by chemical wet etching definition conductor layer 104 and insulating barrier 102.As shown in Figure 3, inject formation source electrode 106a and drain electrode 106b, form side wall 108 in described grid 104a both sides carrying out ion in the described grid 104a substrate on two sides.As shown in Figure 4, comprehensive depositing metal layers 114 on described substrate surface, described metal level 114 materials can be that tungsten, molybdenum, cobalt, titanium or other can be used for the metal material of manufacture of semiconductor.As shown in Figure 5, described metal level 114 is carried out temper, generate metal silicide contact 114a so that silicon materials and the metal level 114 that contacts of source electrode 106a, drain electrode 106b and grid 104a react, and remove not the metal level 114 that reacts with silicon materials by wet etching.
Along with dwindling day by day of dimensions of semiconductor devices; require more and more higher to device performance; particularly 90nm and following technology node thereof; for obtaining lower contact resistance; industry adopts the metal material of nickel metal as the metal silicide that forms low-resistivity; and on nickel metal layer, deposit for example titanium nitride of a cover layer again, not oxidized with protection nickel.The nickel metal back of annealing is generated low-resistance nickle silicide, need not remove by wet etching with the nickel and the titanium nitride of pasc reaction, general choose SC1 (aqueous solution of aqua ammonia and hydrogen peroxide) and MII (mixed solution of phosphoric acid, nitric acid and formic acid) carries out etching as corrosive liquid, promptly pass through the titanium nitride on SC1 etching upper strata earlier, again the nickel that does not react by the MII etching.Yet existing corrosive liquid SC1 and the MII that is used for etching nickel metal and titanium nitride do not have good selectivity to nickel and primer, after removing nickel and titanium nitride, etching can carry out etching to the material of side wall, cause the side wall bottom to cave in to the grid direction, as shown in Figure 6, the side wall of silica 115-silicon nitride 116 structures bottom produces defective 117 owing to being corroded.Thereby reduced the supression effect of charge carrier diffusion during side wall leaks to the protective effect of grid with to the source, can increase the leakage current of device, reduced the stability of the device that brings thus.
Summary of the invention
Therefore, the object of the present invention is to provide the manufacture method of silicide contacts in a kind of semiconductor device, to solve corrosive liquid in the existing silicide contacts manufacture process produces defective to the corrosion of side wall bottom problem.
For achieving the above object, the manufacture method of silicide contacts in a kind of semiconductor device provided by the invention comprises:
The one semiconductor-based end with device layer, be provided;
On the described semiconductor-based end, form metal level;
Described metal level is annealed;
With the mixed solution of sulfuric acid and hydrogen peroxide to described metal level selective etch.
Described device layer comprises metal oxide semiconductor transistor.
Described metal layer material comprises a kind of in nickel, titanium, cobalt, tantalum, platinum, germanium, tungsten, the copper.
The method of described formation metal level is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), plating, the ald.
The ratio of described sulfuric acid and hydrogen peroxide is 2: 1～8: 1.
The temperature of described sulfuric acid and hydrogen peroxide is greater than 60 ℃.
The concentration of described sulfuric acid is 98%.
The temperature of described annealing is 200～1000 ℃.
Accordingly, the present invention also provides the manufacture method of silicide contacts in a kind of semiconductor device, comprising:
On the semiconductor-based end, form metal level;
On described metal level, form cover layer;
To annealing at the described semiconductor-based end;
With the mixed solution of sulfuric acid and hydrogen peroxide to described metal level and cover layer selective etch.
Described metal layer material comprises a kind of in nickel, titanium, cobalt, tantalum, platinum, germanium, tungsten, the copper.
Described cover layer material comprise titanium nitride, titanium, tungsten, tantalum, cobalt, in a kind of or its combination.
The ratio of described sulfuric acid and hydrogen peroxide is 2: 1～8: 1.
Compared with prior art, the present invention has the following advantages: adopt the corrosive liquid of the mixed solution of sulfuric acid and hydrogen peroxide as wet etching in the manufacture method of silicide contacts of the present invention, it is fast to have an etching speed, selects than high advantage.
Sulfuric acid and hydrogen peroxide mixed solution have fine etching selection to the oxide and the nitride of nickel and its bottom, oxide and nitride are had very slow etch rate thereby can not cause the silica of nickel metal layer bottom and silicon nitride is corroded and produces defective, avoided side wall bottom generation of defects; And the present invention adopts a step etching technics, with respect to going on foot etching technics with two of MII again with SC1 earlier in the prior art, saves time more and corrosive liquid, and the raising and the cost that help productive rate reduce.
Description of drawings
Fig. 1～Fig. 5 is the manufacture method profile of existing silicide contacts;
Fig. 6 is the defective generalized section of the manufacture method generation of existing silicide contacts;
Fig. 7 is the manufacture method flow chart according to the embodiment of the invention;
Fig. 8～Figure 14 is the manufacture method generalized section according to the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 7 is the flow chart according to the silicide contacts manufacture method of the embodiment of the invention.
As shown in Figure 7, at first, provide the semiconductor-based end (S200) with device layer.Described device layer comprises source electrode and the drain electrode at the semiconductor-based end, the suprabasil dielectric layer of semiconductor between described source electrode and the drain electrode, the side wall of grid on the described dielectric layer and described grid both sides.Described dielectric layer is a kind of in silica or the carbon oxygen silicon compound, and described grid can be the stack architecture that polysilicon, metal silicide, silicon nitride form, and described side wall can be a kind of or its combination in silica, the silicon nitride.
Described semiconductor-based basal surface is cleaned, with the oxide of source electrode and drain electrode upper surface and gate upper surface in the removal substrate.Remove the aqueous vapor (degas) on surface then by baking.The depositing operation chamber is sent at the described semiconductor-based end carried out for example deposition of nickel of metal level, the mode of deposition can be a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), plating or the ald.Form a nickel metal layer by being deposited on described semiconductor-based basal surface, on described nickel metal layer, deposit the titanium nitride layer again to protect described nickel metal layer not oxidized (S210).
Annealing in process (S220) is carried out at the described semiconductor-based end that is formed with metal level.Annealing in process generally was divided into for two steps, at first annealed under lower temperature, and for example Tui Huo temperature is 300～700 ℃; Anneal under higher temperature then, for example Tui Huo temperature is 700～1000 ℃.By annealing process, the silicon materials of the source electrode at the described semiconductor-based end and drain electrode upper surface, gate upper surface contact with metallic nickel reaction generation metal silicide infusibility, that resistivity is low.
After finishing annealing process, metallic nickel and titanium nitride that described semiconductor-based basal surface does not have to contact with silicon materials reaction generation metal silicide are removed (S230) by the wet method selective etch.The corrosive liquid of described wet etching adopts the mixture of sulfuric acid and hydrogen peroxide (SPM), and the ratio of described sulfuric acid and hydrogen peroxide is 2: 1～8: 1, and temperature is greater than 60 ℃, and the concentration of sulfuric acid is 98%.Adopt the mixed solution of sulfuric acid and hydrogen peroxide that described metal level nickel and titanium nitride layer are carried out selective etch, at first titanium nitride layer is removed, then will less than and the nickel that reacts of silicon remove, sulfuric acid and hydrogen peroxide mixed solution have fine etching selection to the oxide and the nitride of nickel and its bottom, oxide and nitride are had very slow etch rate thereby can not cause the silica of nickel metal layer bottom and silicon nitride is corroded and produces defective, avoided side wall bottom generation of defects; And the present invention adopts a step etching technics, with respect to going on foot etching technics with two of MII again with SC1 earlier in the prior art, saves time more and corrosive liquid, and the raising and the cost that help productive rate reduce.
In detail manufacture method of the present invention is described below in conjunction with embodiment.
Fig. 8～Figure 14 is the generalized section according to the manufacture method of the embodiment of the invention.
As shown in Figure 8, at first provide semiconductor substrate 200, material of the described semiconductor-based ends 200 can be a kind of in polysilicon, monocrystalline silicon, the amorphous silicon, and structure of the described semiconductor-based ends 200 also can be a silicon on the insulating barrier (SOI).Form isolated groove 202 and fill insulant therein by chemical wet etching on the described semiconductor-based end, described insulating material can be a kind of or its combination in silica, silicon nitride, the carborundum.
As shown in Figure 9, on the described semiconductor-based end 200, form oxide layer 204 and polysilicon layer 206 successively, the mode that forms is chemical vapour deposition (CVD) or physical vapour deposition (PVD), can improve the resistivity of polysilicon layer 206 by mixing phosphorus or boron impurity, also the part of polysilicon layer 206 can be formed metal silicide to reduce the resistivity of the grid that forms.
As shown in figure 10, form grid 206a and gate oxide 204a by photoetching and etching technics.Described oxide layer 204 also can be used as down the road technology barrier layer that ion injects when forming source electrode and drain electrode, reducing energetic ion to the damage of substrate and to avoid ion to inject dark, after source electrode to be formed and the drain electrode again by etching formation gate oxide 204a.
As shown in figure 11, to mixing to form source electrode and drain electrode 209a, 209b at the semiconductor-based end of described grid 206a both sides, the described foreign ion that mixes is different with the most foreign ions at the semiconductor-based end 200, the for example described semiconductor-based end 200 is the substrate of N type, its most foreign ions are electronics, and the foreign ion that forms source electrode and drain electrode 209a, 209b that then mixes is a for example boron of P type ion.Form side wall 208 at described grid 206a and oxide layer 204a both sides then, described side wall 208 can be a kind of or its combination in silica, the silicon nitride.With described side wall 208 is that silica and silicon nitride are combined as example, the step of its formation is, at first on the described semiconductor-based end that is formed with grid 206a, form silicon oxide layer, on described silicon oxide layer 208a, form silicon nitride layer, remove the partial oxidation silicon layer and silicon nitride layer stays grid both sides silica 208a and silicon nitride 208b by photoetching and etching technics, the silica and the silicon nitride stack of grid top also are removed simultaneously, expose described grid 206a upper surface.
As shown in figure 12, on surface, the described semiconductor-based ends 200, grid 206a and side wall 208 surface depositions one metal level 210, described metal level 210 materials can be a kind of or its combinations in nickel, titanium, cobalt, tantalum, platinum, germanium, tungsten, the copper.The method that forms described metal level 210 is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), plating, the ald.The thickness of the metal level 210 of deposition is 20～150 dusts.
As shown in figure 13, on described metal level 210, form a cover layer 212, described cover layer material is a kind of or its combination in titanium nitride, titanium, tungsten, tantalum, the cobalt, the mode of its deposition is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), plating, the ald, and the thickness of the cover layer 212 of deposition is 50～300 dusts.Cover layer 212 is not oxidized in order to protection metal level 210.
As shown in figure 14, sent into high-temperature annealing furnace the described semiconductor-based end that is formed with metal level 210 and cover layer 212 and carry out the short annealing processing.Annealing in process generally is divided into two step or multisteps.For example, at first anneal under as 400～700 ℃ in lower temperature, then in higher temperature as 700～1000 ℃ of annealing down; By double annealing technology, spread in the silicon materials of the metal material in the described metal level 210 source electrode and drain electrode 209a, 209b and grid 206a upper surface in the semiconductor-based end 200, the metal silicide that forms infusibility with the silicon materials reaction contacts 210a, and improves the resistivity of described metal silicide contact 210a; The resistivity that reduces described metal silicide contact 210a by the second step annealing technology to desirable scope for example less than 300u Ω/cm.
After finishing annealing process, described metallic nickel and the titanium nitride that does not have to contact with silicon materials reaction generation metal silicide removed by the wet method selective etch.The corrosive liquid of described wet etching adopts the mixture of sulfuric acid and hydrogen peroxide (SPM), and the ratio of described sulfuric acid and hydrogen peroxide is 2: 1～8: 1, and temperature is greater than 60 ℃, and the concentration of sulfuric acid is 98%.Adopt the mixed solution of sulfuric acid and hydrogen peroxide that described metal level nickel and titanium nitride layer are carried out selective etch, at first titanium nitride layer is removed, then will be not and the nickel removal that reacts of silicon.Metal level 210 by annealing process make source electrode 209a and the drain electrode 209b, layer metal silicide contact 210a is given birth in the reaction of grid 206a upper surface silicon materials, and at semiconductor-based the end other zone for example side wall 208 outer surfaces since be silica or silicon nitride material and not with metal level 210 reactions, unreacted metal layer 210 material are removed in mixed liquor corrosion by sulfuric acid and hydrogen peroxide, sulfuric acid and hydrogen peroxide mixed solution have fine etching selection to the oxide and the nitride of nickel and its bottom, oxide and nitride are had very slow etch rate thereby can not cause the silica of nickel metal layer bottom and silicon nitride is corroded and produces defective, avoided side wall bottom generation of defects; And the present invention adopts a step etching technics, with respect to going on foot etching technics with two of MII again with SC1 earlier in the prior art, saves time more and corrosive liquid, and the raising and the cost that help productive rate reduce.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1. the manufacture method of silicide contacts in the semiconductor device comprises:
The one semiconductor-based end with device layer, be provided;
On the described semiconductor-based end, form metal level;
Described metal level is annealed;
With the mixed solution of sulfuric acid and hydrogen peroxide to described metal level selective etch.
2. manufacture method as claimed in claim 1 is characterized in that: described device layer comprises metal oxide semiconductor transistor.
3. manufacture method as claimed in claim 1 is characterized in that: described metal layer material comprises a kind of in nickel, titanium, cobalt, tantalum, platinum, germanium, tungsten, the copper.
4. manufacture method as claimed in claim 1 is characterized in that: the method for described formation metal level is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), plating, the ald.
5. manufacture method as claimed in claim 1 is characterized in that: the ratio of described sulfuric acid and hydrogen peroxide is 2: 1～8: 1.
6. manufacture method as claimed in claim 1 is characterized in that: the temperature of described sulfuric acid and hydrogen peroxide is greater than 60 ℃.
7. manufacture method as claimed in claim 1 is characterized in that: the concentration of described sulfuric acid is 98%.
8. manufacture method as claimed in claim 1 is characterized in that: the temperature of described annealing is 200～1000 ℃.
9. the manufacture method of silicide contacts in the semiconductor device comprises:
On the semiconductor-based end, form metal level;
On described metal level, form cover layer;
To annealing at the described semiconductor-based end;
With the mixed solution of sulfuric acid and hydrogen peroxide to described metal level and cover layer selective etch.
10. manufacture method as claimed in claim 9 is characterized in that: described metal layer material comprises a kind of in nickel, titanium, cobalt, tantalum, platinum, germanium, tungsten, the copper.
11. manufacture method as claimed in claim 9 is characterized in that: described cover layer material comprise titanium nitride, titanium, tungsten, tantalum, cobalt, in a kind of or its combination.
12. manufacture method as claimed in claim 9 is characterized in that: the ratio of described sulfuric acid and hydrogen peroxide is 2: 1～8: 1.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2006101191603A CN101197281A (en) | 2006-12-05 | 2006-12-05 | Production method for silicide contact in semiconductor element |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2006101191603A CN101197281A (en) | 2006-12-05 | 2006-12-05 | Production method for silicide contact in semiconductor element |
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| CN101197281A true CN101197281A (en) | 2008-06-11 |
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| CNA2006101191603A Pending CN101197281A (en) | 2006-12-05 | 2006-12-05 | Production method for silicide contact in semiconductor element |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403211A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for metal silicide |
| CN102437035A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for removing excess nickel after forming nickel silicide |
| CN102437034A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for forming nickel silicide blocking layer |
| CN103165623A (en) * | 2011-12-16 | 2013-06-19 | 群康科技(深圳)有限公司 | Thin film transistor base plate, preparation method thereof and displayer |
| CN103187274A (en) * | 2012-01-03 | 2013-07-03 | 三星电子株式会社 | Ethods of forming semiconductor devices |
| CN109545685A (en) * | 2018-11-16 | 2019-03-29 | 扬州扬杰电子科技股份有限公司 | A kind of front metal rework preocess not influencing Schottky barrier quality |
-
2006
- 2006-12-05 CN CNA2006101191603A patent/CN101197281A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403211A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for metal silicide |
| CN102403211B (en) * | 2010-09-17 | 2015-05-20 | 中芯国际集成电路制造(北京)有限公司 | Preparation method for metal silicide |
| CN102437035A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for removing excess nickel after forming nickel silicide |
| CN102437034A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for forming nickel silicide blocking layer |
| CN103165623A (en) * | 2011-12-16 | 2013-06-19 | 群康科技(深圳)有限公司 | Thin film transistor base plate, preparation method thereof and displayer |
| CN103165623B (en) * | 2011-12-16 | 2015-12-16 | 群康科技(深圳)有限公司 | Thin film transistor base plate and its method for making, display |
| CN103187274A (en) * | 2012-01-03 | 2013-07-03 | 三星电子株式会社 | Ethods of forming semiconductor devices |
| CN109545685A (en) * | 2018-11-16 | 2019-03-29 | 扬州扬杰电子科技股份有限公司 | A kind of front metal rework preocess not influencing Schottky barrier quality |
| CN109545685B (en) * | 2018-11-16 | 2023-01-06 | 扬州扬杰电子科技股份有限公司 | Front metal reworking process without affecting quality of Schottky barrier |
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