CN115939175A - Ohmic contact structure and manufacturing method thereof, silicon carbide device and manufacturing method thereof - Google Patents
Ohmic contact structure and manufacturing method thereof, silicon carbide device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses an ohmic contact structure and a manufacturing method thereof, a silicon carbide device and a manufacturing method thereof.A different ohmic contact is respectively formed on doping regions with different conductive types by using two metals with different work functions as ohmic contact materials, and the specific contact resistance of a P type and an N type is effectively reduced, so that the reverse breakdown resistance of the device caused by the sudden change of voltage current is improved, and the power consumption of the device during conduction is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an ohmic contact structure and a manufacturing method thereof, and a silicon carbide device and a manufacturing method thereof.
Background
SiC is a semiconductor material with excellent physical, chemical and electrical properties, and has a good application prospect in the field of power semiconductor devices, especially under the conditions of high power and high voltage. Ohmic contact is a key process in the preparation process of the SiC device, good ohmic contact is formed between metal and a semiconductor, and the performance of the semiconductor device can be obviously improved.
In the conventional method for forming an ohmic contact, a contact layer pattern is formed on an interlayer dielectric material by photolithography and etching techniques, and then a single metal structure, such as metallic nickel, is formed by PVD sputtering. And reacting the metal nickel and the SiC contact region through a high-temperature rapid thermal annealing process to form a nickel complex, thereby forming ohmic contact.
However, in the conventional manufacturing method, it is very difficult to simultaneously form good N-type and P-type ohmic contacts through a single metal structure. For the same metal, the sum of potential barriers of the N-type gold half contact and the P-type gold half contact is equal to the forbidden bandwidth, so that for a single metal structure, the N-type ohmic contact is well made, and the P-type ohmic contact is deteriorated. This can cause sudden changes of current and voltage when the device works, and negative inductance generated in the circuit is easy to break down the device in the reverse direction.
In view of the above problems, the present application provides a new ohmic contact structure and a method for fabricating the same, and a silicon carbide device and a method for fabricating the same.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention provides a method for manufacturing an ohmic contact structure, which comprises the following steps:
providing a substrate, forming a first doped region extending from the top surface of the substrate to the inside of the substrate and a second doped region adjacent to the first doped region and having an opposite conductivity type, and forming a gate structure over the substrate, wherein the gate structure covers a part of the second doped region;
forming a side wall on the side wall of the grid structure, wherein the side wall at least covers the exposed area of the second doping area;
forming a first metal layer on the first doping region;
carrying out first annealing treatment to enable the first metal layer and the surface layer of the first doping region to be alloyed to form a first ohmic contact region;
removing the side wall to expose the second doped region;
forming a second metal layer at least covering the exposed region of the second doped region, wherein the first metal layer and the second metal layer are made of different materials;
and performing second annealing treatment to enable the second metal layer and the surface layer of the second doping region at least covered by the second metal layer to be alloyed to form a second ohmic contact region.
Further, forming a sidewall spacer on the sidewall of the gate structure includes:
forming a side wall material layer covering the substrate;
and etching back the side wall material layer to expose at least part of the top of the first doped region, and simultaneously forming a side wall on the side wall of the grid structure, wherein the side wall at least covers the exposed region of the second doped region.
Further, the conductivity type of the first doped region is P-type, and the conductivity type of the second doped region is N-type, or the conductivity type of the first doped region is N-type, and the conductivity type of the second doped region is P-type.
Further, when the conductivity type of the first doped region is P-type and the conductivity type of the second doped region is N-type, the first metal layer comprises at least one of titanium, aluminum or tungsten or a combination thereof, and the second metal layer comprises at least one of nickel, aluminum or tungsten or a combination thereof;
when the conductivity type of the first doped region is N-type and the conductivity type of the second doped region is P-type, the first metal layer comprises at least one of nickel, aluminum or tungsten or a combination thereof, and the second metal layer comprises at least one of titanium, aluminum or tungsten or a combination thereof.
Further, the substrate is a silicon carbide substrate, a well is formed in the substrate, the first doped region and the second doped region are both located in the well, the conductivity type of the first doped region is opposite to that of the well, and the conductivity type of the second doped region is the same as that of the well.
Further, the grid structure comprises a grid dielectric layer and a grid material layer which are sequentially stacked from bottom to top, and an interlayer dielectric layer which covers the top and the side wall of the stacked structure formed by the grid dielectric layer and the grid material layer.
Further, the thickness of the first metal layer is less than or equal to the thickness of the second metal layer.
Further, the annealing temperature of the first annealing treatment is 800-900 ℃, and the annealing temperature of the second annealing treatment is 900-1000 ℃.
Further, a step of forming a third metal layer covering the substrate is further included after forming the second ohmic contact region.
The present invention also provides an ohmic contact structure comprising:
the semiconductor device comprises a substrate, wherein a first doped region and a second doped region which is adjacent to the first doped region and has an opposite conductivity type are arranged on the top surface of the substrate and extend into the substrate, and a gate structure is arranged above the substrate and covers a part of the second doped region;
the first ohmic contact region comprises an alloyed first metal layer and a surface layer of the first doping region;
and the second ohmic contact region comprises an alloyed second metal layer and a surface layer of the second doped region at least covered by the second metal layer, wherein the first metal layer and the second metal layer are made of different materials.
Further, the substrate is a silicon carbide substrate, a well is formed in the substrate, the first doped region and the second doped region are both located in the well, the conductivity type of the first doped region is opposite to that of the well, and the conductivity type of the second doped region is the same as that of the well.
The invention also provides a manufacturing method of the silicon carbide device, which comprises the steps in the manufacturing method of the ohmic contact structure or comprises the step of preparing the silicon carbide device by the ohmic contact structure.
The invention also provides a silicon carbide device which comprises the ohmic contact structure or is prepared by the ohmic contact structure.
According to the ohmic contact structure and the manufacturing method thereof, the silicon carbide device and the manufacturing method thereof provided by the invention, two metals with different work functions are used as ohmic contact materials to form different ohmic contacts on the doping regions with different conduction types respectively, and the specific contact resistance of the P type and the N type is effectively reduced, so that the reverse breakdown resistance of the device caused by the sudden change of the voltage current is improved, and the power consumption of the device during conduction is reduced.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a process flow diagram of a method of forming an ohmic contact structure according to an embodiment of the invention;
fig. 2A-2I are schematic structural diagrams of devices obtained by steps related to a method for fabricating an ohmic contact structure according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In the existing method for manufacturing the ohmic contact structure, it is very difficult to simultaneously form good ohmic contacts of an N type and a P type through a single metal structure. For the same metal, the sum of the potential barriers of the N-type gold half-contact and the P-type gold half-contact is equal to the forbidden bandwidth, so that for a single metal structure, the N-type ohmic contact is well made, and the P-type ohmic contact is poor. This can cause sudden changes of current and voltage when the device works, and negative inductance generated in the circuit is easy to break down the device in the reverse direction.
In view of the above problems, the present invention provides a method for manufacturing an ohmic contact structure, as shown in fig. 1, the method mainly includes the following steps:
step S101: providing a substrate, forming a first doped region extending from the top surface of the substrate to the inside of the substrate and a second doped region adjacent to the first doped region and having an opposite conductivity type, and forming a gate structure over the substrate, wherein the gate structure covers a part of the second doped region;
step S102: forming a side wall on the side wall of the grid structure, wherein the side wall at least covers the exposed area of the second doping area;
step S103: forming a first metal layer on the first doping region;
step S104: carrying out first annealing treatment to enable the first metal layer and the surface layer of the first doping region to be alloyed to form a first ohmic contact region;
step S105: removing the side wall to expose the second doped region;
step S106: forming a second metal layer at least covering the exposed region of the second doped region, wherein the first metal layer and the second metal layer are made of different materials;
step S107: and carrying out second annealing treatment to enable the second metal layer and the surface layer of the second doping region at least covered by the second metal layer to be alloyed to form a second ohmic contact region.
Hereinafter, a method for fabricating an ohmic contact structure according to the present invention will be described in detail with reference to the accompanying drawings. Fig. 2A to 2I show schematic structural diagrams of devices obtained by relevant steps of a method for manufacturing an IGBT device according to an embodiment of the present invention.
Firstly, step S101 is performed, as shown in fig. 2A, a substrate 200 is provided, a first doped region 201 extending from a top surface of the substrate 200 to an inside of the substrate and a second doped region 202 adjacent to the first doped region 201 and having an opposite conductivity type are formed, a gate structure 204 is formed above the substrate, and the gate structure 204 covers a portion of the second doped region 202.
In one embodiment, the substrate 200 is a silicon carbide (SiC) substrate, and further, the substrate 200 is an N-type SiC substrate.
In one embodiment, a well 203 is formed in the substrate 200. Further, when the substrate is an N-type substrate and a P-well is formed in the N-type substrate, in an embodiment of the present invention, a P-well window is first formed on the N-type substrate, ion implantation is performed in the P-well window, and then an annealing step is performed to form the P-well.
In one embodiment, a first doped region 201 and a second doped region 202 are formed in the well 203, the first doped region 201 has a conductivity type opposite to that of the well 203, and is a source region of a silicon carbide MOS transistor, the first doped region 201 has an equipotential with the well 203, and the second doped region 202 has a conductivity type the same as that of the well 203 and is a same-type doped region of the well 203.
In one embodiment, the first doped region 201 and the second doped region 202 are adjacent to each other and have opposite conductivity types, specifically, the conductivity type of the first doped region 201 is P-type, and the conductivity type of the second doped region 202 is N-type. In the embodiment of the present invention, P-type doped ions are implanted into the substrate 200 to form a first doped region 201 (which may also be referred to as a P + source region), N-type doped ions are implanted into the substrate 200 to form a second doped region 202 (which may also be referred to as an N + source region), and the upper surfaces of the first doped region 201 and the second doped region 202 are flush with the upper surface of the well 203.
It should be noted that, in the above embodiments, the conductivity types of the substrate, the well region, and the first and second doped regions are all described by taking an NMOS device as an example, but this is not limiting, and in the embodiments taking a PMOS device as an example, the substrate, the well region, and the first and second doped regions all have the opposite conductivity types to the above.
In addition, the first doped region 201 and the second doped region 202, which are adjacent and have opposite conductivity types, may have a plurality of repeating units, and in the embodiment shown in fig. 2A, the second doped region 202 is adjacent to both sides of the first doped region 201.
Illustratively, the gate structure 204 includes a gate dielectric layer 2041 and a gate material layer 2042 which are sequentially stacked from bottom to top, and an interlayer dielectric layer 2043 which covers the top and the side wall of the stacked structure formed by the gate dielectric layer 2041 and the gate material layer 2042.
In one embodiment, gate dielectric layer 2041 comprises an oxide layer, such as silicon dioxide (SiO) 2 ) And (3) a layer. Gate material layer 2042 includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer, where the metal layer may be composed of tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride layer includes a titanium nitride (TiN) layer; the conductive metal oxide layer comprises iridium oxide (IrO) 2 ) A layer; the metal silicide layer includes a titanium silicide (TiSi) layer. The interlayer dielectric layer 2043 may be formed using an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, an insulating layer containing polyvinyl phenol, polyimide, siloxane, or the like.
Next, step S102 is executed, as shown in fig. 2B-2C, a sidewall is formed on a sidewall of the gate structure 204, where the sidewall at least covers the exposed region of the second doped region 202.
Illustratively, the forming of the sidewall spacers 205 on the sidewalls of the gate structure 204 includes:
forming a side wall material layer 205' covering the substrate 200;
the spacer material layer 205' is etched back to expose at least a portion of the top of the first doped region 201, and a spacer 205 is formed on the sidewall of the gate structure 204, where the spacer 205 at least covers the exposed region of the second doped region 202.
First, as shown in fig. 2B, a sidewall spacer material layer 205' is formed to cover the substrate 200. In one embodiment, the spacer material layer 205' includes, but is not limited to, a silicon nitride (SiN) layer. The sidewall material layer 205' may be formed by any conventional technique known to those skilled in the art, and is preferably formed by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), low Pressure Chemical Vapor Deposition (LPCVD), rapid Thermal Chemical Vapor Deposition (RTCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD). In embodiments of the present invention, low Pressure Chemical Vapor Deposition (LPCVD) is preferred to form the SiN layer.
Next, as shown in fig. 2C, the spacer material layer 205' is etched back to expose at least a portion of the top of the first doped region 201, and a spacer 205 is formed on the sidewall of the gate structure 204, where the spacer 205 at least covers the exposed region of the second doped region 202.
Illustratively, the method for etching back the sidewall material layer 205' may be dry etching or wet etching, wherein the dry etching method can use an anisotropic etching method based on carbon fluoride gas, and the wet etching method can use a hydrofluoric acid solution, such as a buffered oxide etchant or a buffered hydrofluoric acid solution.
In the embodiment of the present invention, etching is performed to etch the sidewall spacer material layer 205 'until at least a portion of the top of the first doped region 201 is exposed, and at the same time, the sidewall spacer 205 is formed on the sidewall of the gate structure 204 by the remaining sidewall spacer material layer 205', and the sidewall spacer 205 covers the exposed region of the second doped region 202.
Next, step S103 is performed, as shown in fig. 2D, a first metal layer 206 is formed on the first doping region 201.
Illustratively, when the conductivity type of the first doped region 201 is P-type and the conductivity type of the second doped region 202 is N-type, the first metal layer 206 includes at least one of titanium, aluminum, or tungsten or a combination thereof, and preferably, the first metal layer 206 is a titanium metal layer. The deposition method of the first metal layer 206 may be one of Low Pressure Chemical Vapor Deposition (LPCVD), laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, or the like. In one embodiment, first metal layer 206 is formed to a thickness in the range of
Next, step S104 is performed, as shown in fig. 2E, a first annealing process is performed to alloy the first metal layer 206 with the surface layer of the first doped region 201 to form a first ohmic contact region 210.
In one embodiment, the annealing temperature of the first annealing treatment is 800 ℃ to 900 ℃. After the first annealing treatment, ti element is diffused to the first doped region 201, so that the first metal layer 206 is alloyed with the surface layer of the first doped region 201 to form a first ohmic contact region 210.
By forming the Ti metal layer on the P + source region, the first ohmic contact region is formed on the surface layers of the Ti metal layer and the P + source region, the P-type specific contact resistance is reduced, the capacity of preventing reverse breakdown of the device caused by voltage current mutation of the device is improved, and the power consumption of the device during conduction is reduced.
Next, after forming the first ohmic contact region 210, a step of etching away an excess first metal layer (e.g., the first metal layer covering the sidewall spacers 205, the interlayer dielectric layer 2043, etc.) is further included. Illustratively, the excess first metal layer may be removed by dry etching or wet etching. The wet etching may use a heated mixed solution of phosphoric acid, nitric acid, acetic acid, and water to remove the excess first metal layer.
Next, step S105 is executed, as shown in fig. 2F, the sidewall spacers 205 are removed to expose the second doped region 202.
For example, the method for removing the sidewall spacers 205 may be a dry etching method or a wet etching method, wherein the wet etching method may use 85% of H heated at 180 ℃ 3 P0 4 And (5) dissolving to completely remove the side wall 205 and expose the second doped region 202.
Next, step S106 is executed, as shown in fig. 2G, a second metal layer 207 is formed, where the second metal layer 207 at least covers the exposed region of the second doped region 202, and the material of the first metal layer 206 is different from that of the second metal layer 207.
Illustratively, when the conductivity type of the first doped region is P-type and the conductivity type of the second doped region is N-type, the second metal layer 207 includes at least one of nickel (Ni), aluminum, or tungsten or a combination thereof, and preferably, the second metal layer 207 is a nickel metal layer. The deposition method of the second metal layer 207 may be a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) methodOr Low Pressure Chemical Vapor Deposition (LPCVD), laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG) by Atomic Layer Deposition (ALD), or the like. In one embodiment, the second metal layer 207 is formed to a thickness in the range of
The thickness of the first metal layer 206 is equal to or less than the thickness of the second metal layer 207.
Next, step S107 is performed, as shown in fig. 2H, a second annealing process is performed to alloy the second metal layer 207 and a surface layer of the second doped region 202 at least covered by the second metal layer 207 to form a second ohmic contact region 220.
In one embodiment, the annealing temperature of the second annealing treatment is 900 ℃ to 1000 ℃. After the second annealing treatment, the Ni element is diffused to the second doped region 202, so that the second metal layer 207 and the surface layer of the second doped region 202 at least covered by the second metal layer 207 are alloyed to form a second ohmic contact region.
By forming the Ni metal layer on the N + source region, the Ni metal layer and the surface layer of the N + source region at least covered by the Ni metal layer are formed into the second ohmic contact region 220, so that the N-type specific contact resistance is reduced, the capability of preventing reverse breakdown of the device caused by voltage current mutation of the device is improved, and the power consumption of the device during conduction is reduced.
Next, after forming the second ohmic contact region 220, a step of etching and removing an excess second metal layer (e.g., the second metal layer covering the sidewall spacers 205, the first ohmic contact region 210, etc.) is further included. Illustratively, the redundant second metal layer can be removed by a dry etching method or a wet etching method. The wet etching may use a heated mixed solution of phosphoric acid, nitric acid, acetic acid, and water to remove the excess second metal layer.
When the conductivity type of the first doped region is N-type and the conductivity type of the second doped region is P-type, the first metal layer includes at least one of nickel, aluminum, or tungsten, or a combination thereof, and the second metal layer includes at least one of titanium, aluminum, or tungsten, or a combination thereof.
Next, referring to fig. 2I, after forming the second ohmic contact region 220, a step of forming a third metal layer 208 covering the substrate 200 is further included.
The introduction of the key steps of the method for manufacturing the ohmic contact structure of the present invention is completed, and a plurality of other processes may be required for the complete device preparation, which is not described herein in detail.
The present invention also provides an ohmic contact structure, as shown in fig. 2I, comprising:
a substrate 200, wherein a first doped region 201 and a second doped region 202 which is adjacent to the first doped region 201 and has an opposite conductivity type are arranged on the top surface of the substrate extending to the inside of the substrate, a gate structure 204 is arranged above the substrate, and the gate structure 204 covers part of the second doped region 202;
a first ohmic contact region 210 comprising an alloyed first metal layer 206 and a surface layer of the first doped region 201;
a second ohmic contact region 220 comprising an alloyed second metal layer 207 and a surface layer of the second doped region at least covered by the second metal layer, wherein the first metal layer and the second metal layer are made of different materials.
In one embodiment, the substrate 200 is a silicon carbide (SiC) substrate, and further, the substrate 200 is an N-type SiC substrate.
In one embodiment, a well 203 is formed in the substrate 200. Further, when the substrate is an N-type substrate, a P well is formed in the N-type substrate.
In one embodiment, a first doped region 201 and a second doped region 202 are formed within the well 203. The first doped region 201 and the well 203 have opposite conductivity types and are source regions of a silicon carbide MOS transistor, the first doped region 201 and the well 203 have the same potential, and the second doped region 202 and the well 203 have the same conductivity type and are the same type doped regions of the well 203.
In one embodiment, the first doped region 201 and the second doped region 202 are adjacent and have opposite conductivity types, specifically, the conductivity type of the first doped region 201 is P-type, and the conductivity type of the second doped region 202 is N-type. The upper surfaces of the first doped region 201 (which may also be referred to as a P + source region) and the second doped region 202 (which may also be referred to as an N + source region) are flush with the upper surface of the well 203.
It should be noted that, in the above embodiments, the conductivity types of the substrate, the well region, and the first and second doped regions are all described by taking an NMOS device as an example, but this is not limiting, and in the embodiments taking a PMOS device as an example, the substrate, the well region, and the first and second doped regions all have the opposite conductivity types to the above.
In addition, the first doped region 201 and the second doped region 202, which are adjacent and have opposite conductivity types, may have a plurality of repeating units, and in the embodiment shown in fig. 2A, the second doped region 202 is adjacent to both sides of the first doped region 201.
Illustratively, the gate structure 204 includes a gate dielectric layer 2041 and a gate material layer 2042 which are sequentially stacked from bottom to top, and an interlayer dielectric layer 2043 which covers the top and the side wall of the stacked structure formed by the gate dielectric layer 2041 and the gate material layer 2042.
In one embodiment, gate dielectric layer 2041 comprises an oxide layer, such as silicon dioxide (SiO) 2 ) And (3) a layer. Gate material layer 2042 includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer, where the metal layer may be composed of tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride layer includes a titanium nitride (TiN) layer; the conductive metal oxide layer comprises iridium oxide (IrO) 2 ) A layer; the metal silicide layer includes a titanium silicide (TiSi) layer. The interlayer dielectric layer 2043 may be formed using an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, an insulating layer containing polyvinyl phenol, polyimide, siloxane, or the like.
Illustratively, when the conductivity type of the first doped region is P-type and the conductivity type of the second doped region is N-type, the first metal layer 206 comprises at least one of titanium, aluminum or tungsten or a combination thereof, and preferably, the first metal layer 206Is a titanium (Ti) metal layer. The thickness of the first metal layer 206 is within a range of
Because the first ohmic contact region 210 is formed on the surface layer of the first metal layer 206 and the first doped region 201, the first ohmic contact region 210 is formed on the surface layer of the P + source region by forming the Ti metal layer on the P + source region, so that the P-type specific contact resistance is reduced, the capability of preventing reverse breakdown of the device caused by sudden change of voltage current of the device is improved, and the power consumption of the device during conduction is reduced.
Illustratively, when the conductivity type of the first doped region is P-type and the conductivity type of the second doped region is N-type, the second metal layer 207 includes at least one of nickel (Ni), aluminum, or tungsten or a combination thereof, and preferably, the second metal layer 207 is a nickel metal layer. In one embodiment, a second metal layer 207 is formed between the two gate structures 204, the second metal layer 207 covers the first ohmic contact region 210 and the top of the second doped region 202, and the thickness of the second metal layer 207 ranges from
The thickness of the first metal layer 206 is equal to or less than the thickness of the second metal layer 207.
Since the second ohmic contact region 220 is formed on the second metal layer 207 and the surface layer of the second doped region 202 at least covered by the second metal layer, the Ni metal layer is formed on the N + source region, so that the second ohmic contact region 220 is formed on the surface layer of the N + source region at least covered by the Ni metal layer and the Ni metal layer, thereby reducing the N-type specific contact resistance, improving the capability of preventing reverse breakdown of the device caused by sudden change of voltage current of the device, and reducing the power consumption of the device during conduction.
When the conductivity type of the first doped region is N-type and the conductivity type of the second doped region is P-type, the first metal layer includes at least one of nickel, aluminum, or tungsten, or a combination thereof, and the second metal layer includes at least one of titanium, aluminum, or tungsten, or a combination thereof.
A third metal layer 208 is also formed over the second metal layer 207 covering the substrate 200.
The invention also provides a manufacturing method of the silicon carbide device, which comprises the steps in the manufacturing method of the ohmic contact structure, or comprises the step of preparing the silicon carbide device by using the ohmic contact structure.
The invention also provides a silicon carbide device which comprises the ohmic contact structure or is prepared by the ohmic contact structure.
According to the ohmic contact structure and the manufacturing method thereof, the silicon carbide device and the manufacturing method thereof provided by the invention, two metals with different work functions are used as ohmic contact materials to form different ohmic contacts on the doping regions with different conduction types respectively, and the specific contact resistance of the P type and the N type is effectively reduced, so that the reverse breakdown resistance of the device caused by the sudden change of the voltage current is improved, and the power consumption of the device during conduction is reduced.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, all of which fall within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (13)
1. A method for fabricating an ohmic contact structure, comprising:
providing a substrate, forming a first doped region extending from the top surface of the substrate to the inside of the substrate and a second doped region adjacent to the first doped region and having an opposite conductivity type, and forming a gate structure over the substrate, wherein the gate structure covers a part of the second doped region;
forming a side wall on the side wall of the grid structure, wherein the side wall at least covers the exposed area of the second doping area;
forming a first metal layer on the first doped region;
carrying out first annealing treatment to enable the first metal layer and the surface layer of the first doping region to be alloyed to form a first ohmic contact region;
removing the side wall to expose the second doped region;
forming a second metal layer at least covering the exposed region of the second doped region, wherein the first metal layer and the second metal layer are made of different materials;
and carrying out second annealing treatment to enable the second metal layer and the surface layer of the second doping region at least covered by the second metal layer to be alloyed to form a second ohmic contact region.
2. The method of claim 1, wherein forming a sidewall spacer on a sidewall of the gate structure comprises:
forming a side wall material layer covering the substrate;
and etching back the side wall material layer to expose at least part of the top of the first doped region, and simultaneously forming a side wall on the side wall of the grid structure, wherein the side wall at least covers the exposed region of the second doped region.
3. The method of claim 1, wherein the first doped region has a conductivity type of P-type and the second doped region has a conductivity type of N-type, or wherein the first doped region has a conductivity type of N-type and the second doped region has a conductivity type of P-type.
4. The method of claim 3, wherein when the conductivity type of the first doped region is P-type and the conductivity type of the second doped region is N-type, the first metal layer comprises at least one of titanium, aluminum, or tungsten, or a combination thereof, and the second metal layer comprises at least one of nickel, aluminum, or tungsten, or a combination thereof;
when the conductivity type of the first doped region is N-type and the conductivity type of the second doped region is P-type, the first metal layer comprises at least one of nickel, aluminum or tungsten or a combination thereof, and the second metal layer comprises at least one of titanium, aluminum or tungsten or a combination thereof.
5. The method of claim 1, wherein the substrate is a silicon carbide substrate, a well is formed in the substrate, the first doped region and the second doped region are both located in the well, the first doped region is of a conductivity type opposite to that of the well, and the second doped region is of a same conductivity type as that of the well.
6. The method of claim 1, wherein the gate structure comprises a gate dielectric layer and a gate material layer stacked in sequence from bottom to top, and an interlayer dielectric layer covering a top and a sidewall of the stacked structure formed by the gate dielectric layer and the gate material layer.
7. The method of claim 1, wherein a thickness of the first metal layer is less than or equal to a thickness of the second metal layer.
8. The method of claim 1, wherein the first annealing temperature is 800 ℃ to 900 ℃ and the second annealing temperature is 900 ℃ to 1000 ℃.
9. The method of claim 1 further comprising the step of forming a third metal layer overlying the substrate after forming the second ohmic contact.
10. An ohmic contact structure, comprising:
the semiconductor device comprises a substrate, wherein a first doped region and a second doped region which is adjacent to the first doped region and has an opposite conductivity type are arranged on the top surface of the substrate and extend into the substrate, and a gate structure is arranged above the substrate and covers a part of the second doped region;
the first ohmic contact region comprises an alloyed first metal layer and a surface layer of the first doping region;
and the second ohmic contact region comprises an alloyed second metal layer and a surface layer of the second doped region at least covered by the second metal layer, wherein the first metal layer and the second metal layer are made of different materials.
11. The ohmic contact structure of claim 11, wherein the substrate is a silicon carbide substrate, a well is further formed in the substrate, the first doped region and the second doped region are both located in the well, the first doped region is of a conductivity type opposite the well, and the second doped region is of the same conductivity type as the well.
12. A method of fabricating a silicon carbide device comprising the steps of the method of fabricating an ohmic contact structure according to any of claims 1 to 9 or comprising using an ohmic contact structure according to any of claims 10 or 11 to fabricate a silicon carbide device.
13. A silicon carbide device comprising or produced using the ohmic contact structure of claim 10 or 11.
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| CN117650051A (en) * | 2023-12-22 | 2024-03-05 | 芯联集成电路制造股份有限公司 | Silicon carbide power device and method for manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117650051A (en) * | 2023-12-22 | 2024-03-05 | 芯联集成电路制造股份有限公司 | Silicon carbide power device and method for manufacturing same |
| CN117650051B (en) * | 2023-12-22 | 2024-09-27 | 芯联集成电路制造股份有限公司 | Silicon carbide power device and method for manufacturing same |
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