CN115954272A - SGT device and manufacturing method thereof - Google Patents

Abstract

The invention discloses an SGT device and a manufacturing method thereof, wherein the method comprises the following steps: providing a semiconductor substrate, wherein a groove is formed in the semiconductor substrate, the inner surface of the groove is covered with a first dielectric layer, and a shielding grid is formed in the groove; etching back the first dielectric layer to expose the top of the shield grid and the semiconductor substrate of the side wall of the groove; depositing and forming a dielectric material layer covering the top of the shielding grid electrode, the top of the first dielectric layer and the side wall of the groove; the dielectric material layer is etched back, and the residual dielectric material on the top of the shielding grid is used as a second dielectric layer. According to the SGT device and the manufacturing method thereof provided by the invention, the IPO is formed by depositing and forming the dielectric material layer covering the top of the shielding grid and the side wall of the groove in the groove, so that the diffusion of doped ions of the shielding grid can be avoided, the thickness uniformity of a grid dielectric layer (GOX) is improved, the consistency of threshold voltage (Vth) is further improved, the thickness of the formed IPO is ensured, and the risk of grid leakage current (IGSS) increase or device failure is reduced.

Description

SGT device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to an SGT device and a manufacturing method thereof.

Background

The power MOSFET device with the Shielded Gate Trench (SGT) can simultaneously realize low on-resistance (Rdson) and low reverse recovery capacitance (Crss), thereby simultaneously reducing the conduction loss and the switching loss of a system and improving the service efficiency of the system.

The gate structure of an SGT device includes a shield gate (also referred to as source polysilicon or shield polysilicon) and a control gate (also referred to as polysilicon gate), both of which are formed in a trench, and is generally divided into an up-down structure and a left-right structure according to the arrangement of the shield gate and the control gate in the trench. The upper and lower structures are provided with a shielding grid at the bottom of the groove, a control grid at the top of the groove, an upper and lower structure relationship is formed between the shielding grid and the control grid, and an inter-gate oxide (IPO) is arranged between the shielding grid and the control grid.

In the process flow of forming the IPO layer of the SGT device in one step, after the Liner oxide layer (Liner oxide) is etched back, the side wall of the trench and the top of the shield Gate are exposed, and doping ions (for example, phosphorus ions) in the shield Gate are easily diffused to the side wall of the trench in the process of forming the Gate oxide layer (Gate oxide, GOX), so that the side wall of the trench is polluted, and the uniformity of the thickness of the GOX is poor and the uniformity of the threshold voltage (Vth) is poor. In addition, the IPO layer of the one-step forming SGT device is formed by thermal oxidation of the shielding grid, the thickness of the IPO layer is mainly determined by the ion doping concentration of the shielding grid and the oxidation temperature, the filling problem is easily caused by the overhigh doping concentration, and the problems of grid leakage current (IGSS) increase or device failure and the like caused by ion diffusion are also possible.

Therefore, it is necessary to provide a new SGT device and a method for manufacturing the same to solve the above technical problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

The invention provides a manufacturing method of an SGT device, which comprises the following steps:

providing a semiconductor substrate, wherein a groove is formed in the semiconductor substrate, the inner surface of the groove is covered with a first dielectric layer, and a shielding grid is formed in the groove;

etching back the first dielectric layer to expose the top of the shielding grid and the semiconductor substrate on the side wall of the groove;

depositing a layer of dielectric material covering the top of the shield gate, the top of the first dielectric layer and the trench sidewalls;

and etching back the dielectric material layer, wherein the residual dielectric material on the top of the shielding grid is used as a second dielectric layer.

Further, depositing a layer of dielectric material covering the top of the shield gate, the top of the first dielectric layer, and the trench sidewalls comprises:

performing a first chemical vapor deposition to form a first layer of dielectric material having a first thickness on top of the shield gate, on top of the first dielectric layer and on the trench sidewalls;

performing a second chemical vapor deposition to form a second layer of dielectric material on top of the shield gate, on top of the first layer of dielectric material, and on the trench sidewalls, wherein the second layer of dielectric material on top of the shield gate has a second thickness and the second layer of dielectric material on the trench sidewalls has a third thickness.

Further, the first chemical vapor deposition comprises sub-atmospheric pressure chemical vapor deposition, and the second chemical vapor deposition comprises high density plasma chemical vapor deposition.

Further, after the second dielectric layer is formed, a step of forming a third dielectric layer covering the trench sidewall is further included.

Further, forming a third dielectric layer overlying the trench sidewalls comprises:

etching back the dielectric material layer until the semiconductor substrate of the side wall of the groove is exposed;

and oxidizing the semiconductor substrate of the exposed groove side wall to form a third dielectric layer covering the groove side wall.

Further, forming a third dielectric layer overlying the trench sidewalls comprises: and etching back the dielectric material layer, wherein the residual dielectric material on the side wall of the groove is used as a third dielectric layer.

Further, the thickness of the second dielectric layer is greater than the thickness of the third dielectric layer.

Further, the first thickness is in the range of

The second thickness is in the range of

Said third thickness ranges between +>

Further, the thickness of the second dielectric layer is in the range of

The present invention also provides an SGT device, comprising:

the semiconductor device comprises a semiconductor substrate, a grid electrode and a grid electrode, wherein a groove is formed in the semiconductor substrate, and a shielding grid electrode is formed in the groove;

a first dielectric layer is formed between the shielding grid electrode and the semiconductor substrate, a second dielectric layer is formed on the top of the shielding grid electrode, and a third dielectric layer is formed on the side wall of the groove above the second dielectric layer.

Further, the thickness of the second dielectric layer is greater than the thickness of the third dielectric layer.

According to the SGT device and the manufacturing method thereof provided by the invention, the dielectric material layer covering the top of the shielding grid and the side wall of the groove is deposited in the groove to form the inter-grid oxide layer (IPO), so that the diffusion of doped ions of the shielding grid can be avoided, the thickness uniformity of the grid dielectric layer (GOX) is improved, the consistency of threshold voltage (Vth) is further improved, the thickness of the formed inter-grid oxide layer (IPO) is ensured, and the risk of grid leakage current (IGSS) increase or device failure is reduced.

Drawings

The following drawings of the present invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a process flow diagram of a method of manufacturing an SGT device according to one embodiment of the present invention;

fig. 2A-2F are schematic structural views of devices obtained at steps associated with a SGT device fabrication method according to one embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

In the process flow of forming the inter-gate oxide (IPO) of the SGT device in one step, after the Liner oxide (Liner oxide) is etched back, the sidewall of the trench and the top of the shield gate are exposed, and doped ions (for example, phosphorus ions) in the shield gate are easily diffused to the sidewall of the trench during the formation of the Gate Oxide (GOX), which causes pollution to the sidewall of the trench, resulting in poor uniformity of the thickness of the GOX and poor uniformity of the threshold voltage (Vth). In addition, the IPO layer of the one-step forming SGT device is formed by thermal oxidation of the shielding grid, the thickness of the IPO layer is mainly determined by the ion doping concentration of the shielding grid and the oxidation temperature, the filling problem is easily caused by the overhigh doping concentration, and the problems of grid leakage current (IGSS) increase or device failure and the like caused by ion diffusion are also possible.

In view of the above problems, the present invention provides a method for manufacturing an SGT device, as shown in fig. 1, the method mainly includes the following steps:

step S101: providing a semiconductor substrate, wherein a groove is formed in the semiconductor substrate, the inner surface of the groove is covered with a first dielectric layer, and a shielding grid is formed in the groove;

step S102: etching back the first dielectric layer to expose the top of the shielding grid and the semiconductor substrate on the side wall of the groove;

step S103: depositing a dielectric material layer covering the top of the shielding grid electrode, the top of the first dielectric layer and the side wall of the groove;

step S104: and etching back the dielectric material layer, wherein the residual dielectric material on the top of the shielding grid is used as a second dielectric layer.

Hereinafter, a method of manufacturing the SGT device of the present invention will be described in detail with reference to the accompanying drawings. Fig. 2A to 2F are schematic structural diagrams of devices obtained in relevant steps of a SGT device manufacturing method according to an embodiment of the present invention.

Step S101 is first performed, as shown in fig. 2A, a semiconductor substrate 200 is provided, a trench is formed in the semiconductor substrate 200, an inner surface of the trench is covered with a first dielectric layer 201, and a shield gate 202 is formed in the trench.

Illustratively, the semiconductor substrate 200 may be any suitable semiconductor material known to those skilled in the art, such as germanium or silicon, or combinations thereof. The semiconductor substrate 200 has a first conductivity type, such as an N type or a P type, and is appropriately selected according to a device type to be manufactured actually, in this embodiment, the conductivity type of the semiconductor substrate 200 is an N type.

In one embodiment, the semiconductor substrate 200 may be at least one of the following mentioned materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is monocrystalline silicon.

Illustratively, any suitable insulating material may be used for the first dielectric layer 201 material, and optionally, the first dielectric layer 201 material may include SiO ₂ One or more of SiCN, siN, siC, siOF and SiON. The first dielectric layer 201 may be formed using a chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method, or the like.

In one embodiment, the first dielectric layer 201 is a Liner oxide (Liner oxide). The material of the first dielectric layer 201 includes an oxide, such as silicon oxide. In this embodiment, when the first dielectric layer 201 is silicon oxide, the first dielectric layer 201 can be formed by thermally oxidizing the surface of the semiconductor substrate 200.

Illustratively, the shield gate 202 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the constituent material of the metal gate may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide comprises iridium oxide (IrO) ₂ ) (ii) a The metal silicide includes titanium silicide (TiSi). In the present embodiment, the material of the shield gate 202 includes polysilicon (Poly).

Illustratively, the method of forming the shielding gate 202 may employ any technique known to those skilled in the art, preferably a Chemical Vapor Deposition (CVD) method, such as Low Temperature Chemical Vapor Deposition (LTCVD), low Pressure Chemical Vapor Deposition (LPCVD), rapid Thermal Chemical Vapor Deposition (RTCVD), plasma Enhanced Chemical Vapor Deposition (PECVD).

Next, step S102 is performed, as shown in fig. 2B, the first dielectric layer 201 is etched back to expose the top of the shield gate 202 and the semiconductor substrate of the trench sidewall.

Illustratively, the first dielectric layer 201 is etched back by a dry etching method or a wet etching method, and a single etching method may be used, or more than one etching method may be used. In this embodiment, a wet etching process is used to etch back the first dielectric layer 201 until the top of the shielding gate 202 and the semiconductor substrate on the sidewall of the trench are exposed. In one embodiment, the wet etch process can employ a hydrofluoric acid solution, such as Buffered Oxide Etchant (BOE) or buffered hydrofluoric acid (BHF).

It should be noted that due to the isotropic etching characteristic of the wet etching, when the first dielectric layer 201 is etched back, the etching is performed not only in the direction perpendicular to the trench sidewall but also in the direction parallel to the trench sidewall, so that the top surface of the first dielectric layer 201 after etching is lower than the top surface of the shield gate 202, as shown in fig. 2B.

Step S103 is performed next, as shown in fig. 2C and 2D, a dielectric material layer covering the top of the shield gate, the top of the first dielectric layer and the trench sidewall is deposited and formed.

Illustratively, depositing a layer of dielectric material covering the top of the shield gate, the top of the first dielectric layer and the trench sidewalls comprises the steps of:

performing a first chemical vapor deposition to form a first layer of dielectric material 2031 of a first thickness on top of the shield gate, on top of the first dielectric layer, and on the trench sidewalls;

a second chemical vapor deposition is performed to form a second layer of dielectric material 2032 on top of the shield gate, on top of the first layer of dielectric material, and on the trench sidewalls, wherein the second layer of dielectric material on top of the shield gate has a second thickness and the second layer of dielectric material on the trench sidewalls has a third thickness.

Illustratively, the first chemical vapor deposition comprises sub-atmospheric chemical vapor deposition (SACVD). The SACVD process refers to a chemical vapor deposition reaction in which a reaction gas is deposited in a chamber at a pressure of 500torr to 600 torr. The sub-atmospheric pressure chemical vapor deposition process has better step coverage capability and trench filling capability, and the reaction process is pure chemical reaction without generating plasma damage.

In one embodiment, the power is 200W-400W when the chemical vapor deposition is carried out by the SACVD process, the temperature in the cavity is heated to 300-400 ℃, the pressure in the cavity is 500 mTorr-600 mTorr, and O is used ₂ The gas flow rate of (1) is 2000-6000 cubic centimeters per minute (sccm/slm), N ₂ The gas flow rate of the deposition chamber is 4000-8000 cubic centimeters per minute (sccm), and the deposition time lasts 80-100 s.

Referring to fig. 2C, a first layer of dielectric material 2031 having a first thickness is formed on top of the shield gate, on top of the first dielectric layer, and on the trench sidewalls by the above stepsA thickness in the range of

By first forming the first dielectric material layer 2031 with a first thickness on the top of the shield gate, the top of the first dielectric layer and the trench sidewall to cover the shield gate 202 and the semiconductor substrate exposed by the trench sidewall in step S102, dopant ions (e.g., phosphorous ions) in the shield gate are prevented from diffusing to the trench sidewall, thereby avoiding contamination to the trench sidewall, improving GOX thickness uniformity and improving threshold voltage (Vth) uniformity.

Illustratively, the second chemical vapor deposition comprises high density plasma chemical vapor deposition (HDP-CVD). HDP-CVD is a chemical vapor deposition apparatus that utilizes an inductively coupled plasma source. In order to avoid the phenomenon that the middle of the interval is pinched off and hollow when the interval with high aspect ratio is filled, the HDP-CVD synchronously carries out deposition and etching processes in the same reaction cavity, simultaneously meets the filling and controlling cost of the high aspect ratio gap, and improves the filling capacity of the groove or the hole.

In one embodiment, in the chemical vapor deposition by the HDP-CVD process, the power is 200W-400W, the temperature in the chamber is heated to 600 ℃ to 700 ℃, the pressure in the chamber is 800 mTorr-1 Torr, and SiH is used ₄ The gas flow rate of (2) is 100-140 cubic centimeters per minute (sccm), O ₂ The gas flow rate of the gas source is 260-300 cubic centimeters per minute (sccm), and the deposition time lasts for 60-90 s.

Referring to fig. 2D, a second layer of dielectric material 2032 is formed on top of the shield gate, on top of the first layer of dielectric material and on the trench sidewalls by the above steps, wherein the second layer of dielectric material on top of the shield gate has a second thickness in the range of a third thickness on the trench sidewalls

The third thickness ranges from £ £ v>

Next, step S104 is performed, as shown in fig. 2E, the dielectric material layer is etched back, and the dielectric material remaining on the top of the shielding gate serves as the second dielectric layer 203.

Illustratively, the dielectric material layer is etched back by a dry etching method or a wet etching method, a single etching method may be used, or more than one etching method may be used. In this embodiment, the dielectric material layer is etched back using a wet etching process. In one embodiment, the wet etching process can employ a hydrofluoric acid solution, such as Buffered Oxide Etchant (BOE) or buffered hydrofluoric acid (BHF).

In one embodiment, the second dielectric layer 203 is an inter-gate oxide (IPO). The material of the second dielectric layer 203 includes an oxide, such as silicon oxide. The thickness of the second dielectric layer 203 ranges from

As shown in fig. 2F, after the second dielectric layer 203 is formed, a step of forming a third dielectric layer 204 covering the trench sidewall is further included.

In one embodiment, the dielectric material layer is etched back until the remaining dielectric material on the top of the shield gate reaches a predetermined thickness as the second dielectric layer 203, while the dielectric material on the trench sidewalls reaches a predetermined thickness as the third dielectric layer 204. Wherein the thickness of the second dielectric layer 203 is greater than the thickness of the third dielectric layer 204.

In one embodiment, the dielectric material layer is etched back in step S104 until the trench sidewalls expose the semiconductor substrate, the remaining dielectric material on the top of the shield gate serves as the second dielectric layer 203, and then the semiconductor substrate of the exposed trench sidewalls is oxidized to form the third dielectric layer 204 covering the trench sidewalls.

In one embodiment, the semiconductor substrate of the exposed trench sidewalls is oxidized using a thermal oxidation process, which includes dry oxygen oxidation or wet oxygen oxidation.

In one embodiment, the third dielectric layer 204 is a gate oxide layer (GOX). The material of the third dielectric layer 204 includes an oxide, such as silicon oxide. The thickness of the third dielectric layer 204 ranges from

Thus, the introduction of the key steps of the method for manufacturing the SGT device of the present invention is completed, and a plurality of other processes, such as a step of forming a control gate, may be required for the complete device preparation, which is not described herein in detail.

The present invention also provides an SGT device, as shown in fig. 2F, including:

a semiconductor substrate 200 having a trench formed therein, the trench having a shield gate 202 formed therein;

a first dielectric layer 201 is formed between the shielding gate 202 and the semiconductor substrate 200, a second dielectric layer 203 is formed on the top of the shielding gate 202, and a third dielectric layer 204 is formed on the side wall of the trench above the second dielectric layer 203;

the thickness of the second dielectric layer 203 is greater than the thickness of the third dielectric layer 204.

Illustratively, the semiconductor substrate 200 may be any suitable semiconductor material known to those skilled in the art, such as germanium or silicon, or combinations thereof. The semiconductor substrate 200 has a first conductivity type, such as an N-type or a P-type, and is appropriately selected according to a device type to be manufactured in actual need, in this embodiment, the conductivity type of the semiconductor substrate 200 is an N-type.

In one embodiment, the semiconductor substrate 200 may be at least one of the following mentioned materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is monocrystalline silicon.

Illustratively, the shield gate 202 comprises one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the constituent material of the metal gate may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide comprises iridium oxide (IrO) ₂ ) (ii) a The metal silicide includes titanium silicide (TiSi). In the present embodiment, the material of the shield gate 202 includes polysilicon (Poly).

Illustratively, the materials of the first dielectric layer 201, the second dielectric layer 203, and the third dielectric layer 204 may use any suitable insulating material, including but not limited to SiO ₂ One or more of SiCN, siN, siC, siOF and SiON.

In one embodiment, the first dielectric layer 201 is a Liner oxide (Liner oxide), the second dielectric layer 203 is an inter-gate oxide (IPO), and the third dielectric layer 204 is a Gate Oxide (GOX). The materials of the first dielectric layer 201, the second dielectric layer 203, and the third dielectric layer 204 include oxides, such as silicon oxide.

Illustratively, the thickness of the second dielectric layer 203 is greater than the thickness of the third dielectric layer 204. In the present embodiment, the thickness of the second dielectric layer 203 ranges from

The thickness of the third dielectric layer 204 ranges from

According to the SGT device and the manufacturing method thereof provided by the invention, the dielectric material layer covering the top of the shielding grid and the side wall of the groove is deposited in the groove to form the inter-grid oxide layer (IPO), so that the diffusion of doped ions of the shielding grid can be avoided, the thickness uniformity of the grid dielectric layer (GOX) is improved, the consistency of the threshold voltage (Vth) is further improved, the thickness of the formed inter-grid oxide layer (IPO) is ensured, and the risk of grid leakage current (IGSS) increase or device failure is reduced.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A method of fabricating an SGT device, comprising the steps of:

providing a semiconductor substrate, wherein a groove is formed in the semiconductor substrate, the inner surface of the groove is covered with a first dielectric layer, and a shielding grid is formed in the groove;

etching back the first dielectric layer to expose the top of the shielding grid and the semiconductor substrate on the side wall of the groove;

depositing a dielectric material layer covering the top of the shielding grid electrode, the top of the first dielectric layer and the side wall of the groove;

and etching back the dielectric material layer, wherein the residual dielectric material on the top of the shielding grid is used as a second dielectric layer.

2. The method of claim 1, wherein depositing a layer of dielectric material covering a top of the shield gate, a top of the first dielectric layer, and sidewalls of the trench comprises:

performing a first chemical vapor deposition to form a first layer of dielectric material having a first thickness on top of the shield gate, on top of the first dielectric layer and on the trench sidewalls;

performing a second chemical vapor deposition to form a second layer of dielectric material on top of the shield gate, on top of the first layer of dielectric material, and on the trench sidewalls, wherein the second layer of dielectric material on top of the shield gate has a second thickness and the second layer of dielectric material on the trench sidewalls has a third thickness.

3. The method of claim 2, wherein the first chemical vapor deposition comprises sub-atmospheric chemical vapor deposition and the second chemical vapor deposition comprises high density plasma chemical vapor deposition.

4. The method of claim 1, further comprising, after forming the second dielectric layer, the step of forming a third dielectric layer covering the trench sidewalls.

5. The method of claim 4, wherein forming a third dielectric layer covering the trench sidewalls comprises:

etching back the dielectric material layer until the semiconductor substrate of the side wall of the groove is exposed;

and oxidizing the semiconductor substrate of the exposed groove side wall to form a third dielectric layer covering the groove side wall.

6. The method of claim 4, wherein forming a third dielectric layer covering the trench sidewalls comprises:

and etching back the dielectric material layer, wherein the residual dielectric material on the side wall of the groove is used as a third dielectric layer.

7. The method of claim 4, wherein a thickness of the second dielectric layer is greater than a thickness of the third dielectric layer.

8. The method of claim 2, wherein the first thickness is in a range of

The second thickness ranges from £ greater than>

The third thickness ranges from £ £ v>

9. An SGT device, comprising:

the semiconductor device comprises a semiconductor substrate, a grid electrode and a grid electrode, wherein a groove is formed in the semiconductor substrate, and a shielding grid electrode is formed in the groove;

a first dielectric layer is formed between the shielding grid electrode and the semiconductor substrate, a second dielectric layer is formed on the top of the shielding grid electrode, and a third dielectric layer is formed on the side wall of the groove above the second dielectric layer.

10. The device of claim 9, wherein a thickness of the second dielectric layer is greater than a thickness of the third dielectric layer.

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