TWI808856B - Bottom source trench mosfet with shield electrode - Google Patents

Abstract

An improved inverted field-effect-transistor semiconductor device and method of making thereof may comprise a source layer on a bottom and a drain disposed on a top of a semiconductor substrate and a vertical current conducting channel between the source layer and the drain controlled by a trench gate electrode disposed in a gate trench lined with an insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding an upper portion of a shield trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding a lower portion of the shield trench. A shield electrode extends upward from the source layer in the shield trench for electrically shorting the source layer and the body region wherein the shield structure extends upward to a heavily doped drain region and is insulated from the heavily doped drain region to act as a shield electrode.

Description

Bottom-source trench MOSFET with masked electrode

Aspects of the invention generally relate to semiconductor power devices. More specifically, various aspects of the invention relate to reverse trench grounded field effect transistors (FETs).

The packaging size of semiconductor power devices such as metal oxide semiconductor field effect transistors (MOSFETs) continues to shrink. Recent developments in FETs have led to the creation of three-dimensional stacked power devices for voltage regulators (so-called "buck converters"). These three-dimensional stacked devices use bottom-source lateral double-diffused MOSFETs (LD MOSFETs). Although the LD MOSFET design allows stacking, the channel density of LD MOSFETs is low and requires an expensive complementary MOSFET (CMOS)-based process requiring many mask steps to create.

Therefore, it would be beneficial to develop 3D stacked power devices using cheaper transistor device designs such as trench MOSFET designs. One possible trench MOSFET design is the inverted trench grounded field-effect transistor (iT-FET). These designs have a bottom source and top drain, allowing the devices to be easily stacked. These iT-FETs have higher channel density compared to LD MOSFETs/One issue with current iT-FET designs is that they have high gate-to-drain capacitance, resulting in slower switching in the on-state (R _ds-on ) and higher drain-to-source resistance. In addition, current manufacturing processes are complex and costly.

Therefore, there is a need in the art for iT-FETs with reduced R _ds-on , faster switching speeds and better manufacturing process flow.

The present invention provides an inverse field effect transistor (iT-FET) semiconductor device, comprising a source layer at the bottom and a heavily doped drain region at the top of a semiconductor substrate:

a vertical current conduction path between the source layer and the drain region controlled by trench gates disposed in gate trenches lined with insulating material;

a mask trench disposed between adjacent gate trenches, the heavily doped drain region disposed near the top of the substrate surrounding the mask trench and an upper portion of the gate trench;

a doped body region disposed in the substrate and surrounding the lower portion of the mask trench;

A mask electrode in the mask trench extends upwardly from the source layer to electrically short the source layer and the body region, wherein the mask electrode extends upwardly in the mask trench to the heavily doped drain region and is insulated from the heavily doped drain region to serve as the mask electrode.

The present invention also provides a method for preparing an iT-FET semiconductor device, comprising:

a) forming an epitaxial layer doped with impurities of a second conductivity type on a substrate heavily doped with impurities of a first conductivity type, wherein the first conductivity type is opposite to the second conductivity type, wherein the substrate is used as a source layer;

b) forming a gate trench through the epitaxial layer into the source layer;

c) lining the mask trench with an insulating material and forming a gate electrode in the gate trench;

d) forming a drift region and a heavily doped drain region doped with impurities of the first conductivity type in the epitaxial layer;

e) Forming masked trenches in the epitaxial layer through heavily doped drain regions and drift regions;

f) forming a body contact region at the bottom of the mask trench by heavily doping with impurities of the second conductivity type;

g) lining trenches with insulating material;

h) deepening the mask trench to the source layer through the body contact region, and forming a mask structure in the mask trench, wherein the mask structure extends upward from the source layer to electrically short the source layer and the body region, wherein the mask structure extends upward to the heavily doped drain region and is insulated from the drain region;

i) A drain is formed over the epitaxial layer.

Although the following detailed description contains many specific details for purposes of illustration, those of ordinary skill in the art will understand that many changes and modifications to the following details are within the scope of the invention. Accordingly, the exemplary embodiments of the present invention described below do not impose any general loss of generality on, nor impose limitations on, the claimed invention.

In the following detailed description, reference is made to the accompanying drawings, which constitute a part of the present invention, and the accompanying drawings show by way of illustrations specific embodiments in which the present invention can be practiced. In this regard, directional terms such as "top," "bottom," "front," "rear," "leading," "trailing," etc. are used with reference to the orientation of the depicted figures. Since elements of embodiments of the present invention may be oriented in a number of different orientations, the directional terms are used for illustration and are not limiting in any way. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be regarded as a description in a limiting sense, and the scope of the present invention is defined by the scope of the appended invention patent application.

In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. Those skilled in the art will understand that in any such implemented embodiment, a number of embodiment-specific decisions must be made to achieve the developer's specific goals, such as compliance with application and business-related constraints, and that these specific goals will vary from embodiment to embodiment and from developer to developer. In addition, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

According to various aspects of the invention, various types of operating systems may be used to implement components, process steps, and/or data structures; computing platforms; user interfaces/displays, including personal or notebook computers, video game consoles, PDAs, and other handheld devices such as cell phones, tablet computers, portable gaming devices; and/or general purpose machines. Furthermore, those of ordinary skill in the art will recognize that less general purpose devices, such as hardwired devices, field programmable gate arrays (FPGs), application specific integrated circuits (ASICs), etc., may also be used without departing from the scope and spirit of the inventive concepts disclosed herein.

The present invention relates to silicon doped with ions of a first conductivity type or a second conductivity type. Ions of the first conductivity type may be counter ions of the second conductivity type. For example, ions of the first conductivity type may be n-type, which generate charge carriers when doped into silicon. Ions of the first conductivity type include phosphorus, antimony, bismuth, lithium, and arsenic. Ions of the second conductivity can be p-type, which when doped into silicon creates holes for charge carriers, and in this way is said to be the opposite of n-type. P-type ions include boron, aluminum, gallium, and indium. Although the above description refers to the n-type as the first conductivity type and the p-type as the second conductivity type, the present invention is not limited thereto, the p-type may be the first conductivity type, and the n-type may be the second conductivity type.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustrations specific embodiments in which the invention may be practiced. For convenience, the use of + or – after specifying conductivity or net impurity carrier type (p or n) generally refers to the relative concentration of the specified type of net impurity carriers within the semiconductor material. In general, n+ materials have a higher concentration of N-type net dopants (eg, electrons) than n materials, and n materials have a higher carrier concentration than n− materials. Similarly, p+ material has a higher concentration of p-type net dopants (eg, holes) than p material, and p material has a higher concentration than p− material. Note that what is relevant is the net concentration of carriers, not necessarily dopants. For example a material may be heavily doped with n-type dopants, but if the material is also sufficiently back-doped with p-type dopants, the material will still have a relatively low net carrier concentration. As used herein, a dopant concentration of less than about 10 ¹⁶ /cm ³ may be considered "lightly doped," while a dopant concentration of greater than about 10 ¹⁷ /cm ³ may be considered "heavily doped."

A major feature in current designs of iT-FETs is the lack of an effective shield electrode that reduces R _ds-on on the circuit. The mask electrode reduces the coupling of the drain to the gate, thereby reducing the Miller effect to drive the gate (Q _gd ), and through this "shading effect" increases the switching speed. A typical iT-FET structure includes a short from the source layer of the substrate to the body region. In prior art embodiments, the shorting region is included in the gate trenches or in separate trenches formed at a greater spacing than the gate spacing in the device. A detail in the present invention is that the source-body junction and the shield electrode can be combined to improve Q _gd and switching speed and R _ds-on .

An improved inverse field-effect transistor (iT-FET) semiconductor device may include a source layer at the bottom and a drain region disposed at the top of a semiconductor substrate, and a vertical conduction channel between the source layer and the drain region controlled by a trench gate disposed in a gate trench lined with an insulating material. A drain region is disposed near the top of the substrate surrounding the upper portion of the mask trench and the gate trench. A doped body region is disposed in the substrate and surrounds a lower portion of the mask trench. A mask structure extends upward from the source layer for electrically shorting the source layer and the body region, wherein the mask structure extends upward to the drain region in the mask trench and is insulated from the drain region to serve as a mask electrode. The mask structure may extend from the bottom of the drain region to the source layer through the mask trench and the body region. The mask structure may further include a conductive plug extending upwardly from the source layer through the body region to at least a portion of the drain region in the mask trench. The mask structure may also include a titanium silicide plug in the mask trench extending upward from the source layer. Alternatively, the mask structure may further include cobalt silicide plugs in the mask trenches extending upward from the source.

The source layer of the semiconductor substrate may be heavily doped with impurities of the first conductivity type, and the semiconductor substrate may further include an epitaxial layer formed on top of the source layer and doped with impurities of the second conductivity type. Doped body regions can also be formed in the epitaxial layer by implanting impurities of the second conductivity type. The drain region is composed of a heavily doped region and a lightly doped region of the first conductivity type. The lightly doped region is also called the drift region. The heavily doped region may be formed in the epitaxial layer implanted with impurities of the first conductivity type. A drift region can be created between the bulk region and the heavily doped region in the epitaxial layer. The drift region may be more lightly doped with impurities of the first conductivity type than the heavily doped region. The drift region may have an impurity concentration gradient, where the impurity concentration is highest near the heavily doped drain region and decreases in the epitaxial layer deeper below the heavily doped drain region. A conductive drain contact plug may contact the heavily doped drain region and the drain. device

Figure 1 shows a side cross-sectional view of an improved iT-FET device with a combined source-body short and mask electrode in accordance with various aspects of the present invention. The device includes a bottom source layer 101 formed in a semiconductor substrate. The source layer may be heavily doped with impurities of the first conductivity type. The epitaxial layer 102 may be disposed on top of the source layer 101 . The epitaxial layer 102 may be lightly doped with impurities of the second conductivity type, which also form the bulk of the device. In an upper region of the epitaxial layer 102 of the semiconductor substrate, a heavily doped drain region 104 may be formed. The heavily doped drain region 104 may be heavily doped with impurities of the first conductivity type. A drift region 105 may be formed between the heavily doped drain region 104 and the epitaxial layer/body region 102 . The drift region may be doped with impurities of the first conductivity type at a lower concentration than the heavily doped drain region 104 . In some embodiments, the drift region 105 may be doped into the epitaxial layer with the highest dopant concentration near the heavily doped drain region 104 in a gradient of decreasing concentration. The ion concentration decreases near the epitaxial layer 102 . On top of the heavily doped drain region 104, a drain contact plug 113 may be provided. The drain contact plug 113 may include silicide and a diffusion barrier layer 114 to improve contact resistance with the drain region 104 and device reliability. For example, but not limited to, the diffusion barrier layer 114 can be metal silicide of titanium or cobalt and titanium nitride, and the drain contact plug 113 can be metal such as tungsten. A drain metal (also referred to herein as “drain”) 112 is disposed on top of the drain contact plug 113 and contacts and connects the drain contact plug 113 to serve as a drain terminal. The drain metal can be a metal such as copper or aluminum.

A vertical channel may be formed in the body region 102 between the drain 112 controlled by the gate electrode 107 and the source layer 101 . The gate electrode 107 is disposed on the insulating layer 106 in the gate trench 120 . The gate trench 120 is lined with an insulating material 106, and the insulating material 106 insulates the gate electrode 107 from the semiconductor substrate in the active region of the device. The gate electrode 107 may be controlled by the gate bar electrode 108 in the gate bar region of the semiconductor substrate in the device termination region. Gate bars 108 may be disposed on insulating material 106 lining gate bar trenches 121 . Gate bars 108 may be electrically coupled to gate electrodes 107 . As shown, the gate bar 108 may be conductively coupled to the gate metal 115 through the gate bar contact plug 116 . The gate bar contact plug 116 may have a complementary material coating 117 similar to the drain contact plug. The gate bar contact plug 116 may include a metal silicide with a complementary diffusion barrier 114 to improve contact resistance with the gate bar 108 and device reliability. For example, without limitation, gate bar contact plug 116 may be a metal such as tungsten, and diffusion barrier 114 may be titanium or a metal silicide of cobalt and titanium nitride. The gate bars 108 and the gate electrodes 107 can be made of conductive materials, such as metal or polysilicon. The insulating material 106 may be a silicon oxide layer.

Mask electrodes 110 may be disposed in mask trenches 122 between adjacent gate trenches 120 in the active region of the device. As shown, the mask trench 122 may be disposed between adjacent drain contact plugs 113 , and the drain plug 113 may be disposed in a space between the gate trench 120 and the shield trench 122 . The mask electrode 110 also acts as a conductive short between the source layer and the body region. Therefore, the mask electrode 110 is in conductive contact with the source layer 101 and the body region 102 . The body region 102 surrounds a lower portion of the mask trench 122 . The drain region 104 surrounds the upper portion of the mask trench 122 , and the drift region 105 surrounds the mask trench 122 below the heavily doped drain region 104 . The bottom of the mask trench 122 is located in the source layer 101 . A mask electrode 110 extends upwardly from the source layer 101 through the body region 102 . A mask insulator 109 isolates the mask electrode 110 from the heavily doped drain region 104 and the drift region 105 and lines the sidewalls of the mask trench 122 over the body region 102 . A body contact region 103 having the same conductivity type as the body region 102 but with a higher doping concentration may be formed near the bottom of the mask trench to provide an ohmic contact between the body region 102 and the mask electrode 110 . The shield electrode 110 may extend upward through the drift region 105 and into the heavily doped drain region 104 . The insulator layer 109 between the mask electrode 110 and the heavily doped drain region 104 and the drift region 105 may be thicker than the insulator layer 106 between the gate 107 and the source 120 , the body region 102 and the drift region 105 .

During operation, when the device is in the off state, the masking electrode 110 can induce a masking effect, allowing a more heavily doped drift region, resulting in a lower R _ds-on . Similar to the gate and drain contacts, the shield electrode 110 may include a coating 111 of a complementary material, such as but not limited to tungsten. The mask electrode 110 may be a metal, such as titanium or cobalt silicide or a suitable alloy thereof. The mask insulator 109 can be any suitable insulating material, such as silicon dioxide. According to various aspects of the present invention, the improved trench gate design of iT-FETs allows for greater device density, as well as improved switching time characteristics and reduced R _ds-on . The pitch of the device units 130 may be 0.7 to 1.2 microns. The gate 107 is recessed to reduce overlap with the heavily doped drain region 104 and the drift region 105 , thereby reducing the gate-drain capacitance (C _gd ). Preparation

Figures 2A-2T represent cross-sectional views of methods for fabricating improved iT-FET devices in accordance with various aspects of the present invention. Figure 2A shows a cross-sectional view of the source and epitaxial layers of a semiconductor substrate during formation of an improved iT-FET in accordance with aspects of the present invention. Initially, the semiconductor substrate includes a source layer 201 heavily doped with ions of the first conductivity type. Epitaxial layer 202 may be formed on the main surface of source layer 201 . The epitaxial layer 202 may be lightly doped with ions of the second conductivity type, and may be grown on the surface of the source layer using an atmospheric or reduced pressure epitaxial process. A gate trench mask 203 may be applied to the main surface of the epitaxial layer 202 in preparation for gate trench formation. The gate trench mask 203 may be formed by any known method, such as but not limited to photolithography, or a patterned oxide layer formed by photolithography and oxide etching.

Figure 2B shows a side view cross-section of gate trench formation in an improved iT-FET device in accordance with various aspects of the present invention. A gate trench 204 may be formed in the semiconductor substrate through the epitaxial layer 202 and into the source layer 201 . Gate trench 204 may be formed using any known etching method. For example, without limitation, dry reactive ion etching (DRIE) may be used to create gate trenches 204 . During the etch process, the gate trench mask 203 prevents the portion of the epitaxial layer covered by the etch mask from being etched. The semiconductor substrate is etched in areas not covered by the mask. After forming the gate trenches, mask 203 is removed. Mask 203 may be removed by any suitable mask removal method, such as chemical etching or plasma ashing.

Figure 2C shows a side view cross-section of steps for forming a gate in an improved iT-FET device according to various aspects of the present invention. As shown, insulating layer 205 is blanket deposited on the surface of epitaxial layer 202 . The insulating layer 205 is arranged inside the gate trench 204 . The insulating layer 205 can be a non-conductive material, such as but not limited to silicon dioxide. Silicon dioxide can be formed by chemical vapor deposition (CVD) or thermal oxidation.

Figure 2E shows a cross-sectional side view of the step of forming a gate electrode in an improved iT-FET device according to various aspects of the present invention. The top surface of the semiconductor 15 substrate is polished to remove conductive material from regions of the insulating layer 205 that are not in the gate trench 204 . Thus, the gate electrode layer 206 is confined within the gate trench 204 . Conductive material may be removed by polishing methods such as but not limited to chemical mechanical polishing or plasma etching processes. In addition, the gate electrode layer 206 can be etched to further reduce the height of the gate and source layer 201 in the gate trench. The gate electrode layer 206 may be etched using any known suitable plasma etch process.

Figure 2F shows a side view cross-section of the step of forming a gate electrode and gate bars in an improved iT-FET device according to various aspects of the present invention. A gate bar mask 207 is formed on top of the full height gate electrode 208 in the gate bar region. For example, gate bar mask 207 may be formed by any known masking method suitable for silicon etching, and without limitation, gate bar mask 207 may be a photolithographic mask. The full height gate electrodes are etched after masking 207 gate bars 208 to create gate electrodes 209 at appropriate depths in gate trenches 204 . The conductive material in gate bar trench 230 is not etched because it is covered by gate bar mask 207 forming gate bar electrode 208 . The gate electrode 209 may be etched in this second etching step using any known suitable polysilicon or metal etching method, depending on the material of the gate electrode precursor.

Figure 2G shows a cross-sectional side view of steps for forming gate electrodes and gate bars in an improved iT-FET device according to various aspects of the present invention. The gate bar mask 207 may be removed by any known mask removal method, such as but not limited to chemical etching or plasma ashing, depending on the type of mask used. An insulating layer 205 is deposited to cover the gate electrode 209 and the gate bar electrode 208 . The gate insulating layer 205 can be deposited by any known deposition method such as but not limited to CVD.

Figure 2H shows a cross-sectional side view of steps for forming gate electrodes and gate bars in an improved iT-FET device according to various aspects of the present invention. The upper surface of the semiconductor substrate is polished to expose the surface of the epitaxial layer 202 and the height of the insulating layer 205 near the gate electrode 209 and the gate runner insulation 210 near the gate runner electrode 208 is lowered. The semiconductor substrate may be polished by any suitable method, such as CMP.

Figure 21 shows a side view cross-section of the steps of forming a heavily doped drain region and a drift region in an improved iT-FET device according to various aspects of the present invention. A drain region mask 211 is formed over the non-active transistor region including, for example, the gate track 208 . The drain region mask 211 may extend from the edge of the semiconductor substrate onto the gate bar insulation 210 and terminate at the gate insulation 209 closest to the gate bar trench 230 . The epitaxial layer 202 is doped with ions of the first conductivity type. The heavily doped drain region 212 is implanted with high-concentration impurities of the first conductivity type after masking the gate-strip region. The drift region 213 is formed by implanting a lower concentration of impurities of the first conductivity type with an implantation energy of 150 KeV to 500 KeV. The doping of the drift region may be on a gradient with a maximum impurity concentration near the heavily doped drain region 212 , and the gradient decreases with distance from the heavily doped drain region 212 to the epitaxial layer 202 . The drain region mask thereby protects the gate-strip region from doping, leaving a portion of the epitaxial layer 202 undoped in the non-active transistor region. The doping of the drift region 213 and the heavily doped drain region 212 can be performed by any suitable method such as but not limited to ion implantation. The drift doping concentration counter dopes the bulk dopant in the epitaxial layer.

Figure 2J shows a cross-sectional side view of the step of forming a mask structure in an improved iT-FET device according to various aspects of the present invention. The heavily doped drain region 212 and the drift region 213 can be annealed by heating. For example, but not limited to, the semiconductor substrate can be heated in a furnace at about 1000° C. for 30-60 minutes to anneal the drift region 213 and the heavily doped drain region 212 . An insulating layer 214 is formed over the top of the semiconductor substrate covering the gate trenches and the gate bar trenches. The insulating layer can be formed by any oxide layer forming method, such as, but not limited to, CVD or thermal oxidation during the annealing of the heavily doped drain and drift regions.

Figure 2K shows a side view cross-section of the step of forming a mask structure in an improved iT-FET device according to various aspects of the present invention. As shown, a mask trench mask 215 is formed on the semiconductor substrate over the insulating layer 214 . The mask is patterned to have gaps in the regions between gate electrodes 209 . After the shadow trench mask 215 is formed, the semiconductor substrate is etched through the openings in the shadow trench mask. The etch process forms a masked trench precursor that passes through the heavily doped drain region 212 , the drift region 213 and into the epitaxial layer 202 . The etch process may be any suitable silicon dioxide and silicon deep etch method such as but not limited to DRIE. Then, the tops of the epitaxial layer 202 at the masked trench precursors are implanted with ions of the second conductivity type to form body contact regions 216 at the bottom of each masked trench. The body contact region 216 may be implanted with, for example, 20KeV-60KeV of boron.

Figure 2L shows a side view cross-section of the step of forming a mask structure in an improved iT-FET device according to various aspects of the present invention. Then, the masking trench mask 215 is removed after the implantation of the epitaxial layer and the body contact region 216 . The mask trench mask 215 may be removed by any mask removal method, such as chemical etching or plasma ashing. An insulating layer 214 is further grown on the surface of the semiconductor substrate and masks the trench 217 . The insulating layer 214 is arranged along the sides and bottom of the masked trench precursor 217 covering the body contact region 216 and the sides of the heavily doped drain region 212 , the drift region 213 and the epitaxial layer 202 .

Figure 2M shows a side view cross-section of the step of forming a mask structure in an improved iT-FET device according to various aspects of the present invention. The insulating layer 214 at the bottom of the mask trench precursor 217 is etched away, exposing the upper surface of the body region 216 . DRIE can be used to etch the insulating layer 214 that masks the bottom of the trench precursor 217 without a masking step.

Figure 2N shows a side view cross-section of the step of forming a mask structure in an improved iT-FET device according to various aspects of the present invention. The body contact region 216 and the epitaxial layer 202 are then etched in the mask trench precursor 217 to complete the mask trench. Select high selectivity RIE etch to preferentially etch the silicon at the bottom of the trench precursor eg silicon substrate without removing too much silicon dioxide. The insulating layer 214 also acts as a mask, preventing etching in the regions covered by the insulating layer and allowing etching at the bottom of the masked trench precursor 217 .

Figure 20 shows a side view cross-section of the step of forming a mask structure in an improved iT-FET device according to various aspects of the present invention. After forming the mask trench, a mask trench electrode layer 219 may be formed on the exposed top surface of the semiconductor substrate and in the mask trench. The mask trench electrode layer 219 may be a metal silicide, such as tungsten. Mask trench metal layer 219 may be coated with supplemental material 218 that acts as a diffusion barrier. The supplemental material coating 218 may be titanium, cobalt, titanium nitride.

Figure 2P shows a side view cross-section of the step of forming a mask structure in an improved iT-FET device according to various aspects of the present invention. Applying an etch on the masked trench electrode layer etches metal from the major surface of the gate insulating layer precursor 214 . The upper surface of the mask trench electrode layer is etched away in the mask trench, resulting in a mask trench electrode 220 coated with a complementary metal coating 221 . The etchant may be any etchant that is selective to the metal used to mask the electrodes. Mask trench electrode 220 and coating 221 extend from source layer 201 , through epitaxial layer 202 and body contact region 216 . The mask trench extends over the body contact region 216 to the drift region 213 and the heavily doped drain region 212 . The thickness of insulating layer 214 is optimized to reduce R _ds-on and reliable undervoltage potential between mask trench electrode 220 and heavily doped drain region 212 and drift region 213 . The mask electrode 220 and the coating 221 also act as a short connecting the source layer 201 and the epitaxial layer 202 through the body contact region 216 .

Figure 2Q shows a cross-sectional side view of the step of forming a mask structure in an improved iT-FET device according to various aspects of the present invention. An insulating layer 222 is deposited over the previous insulation 214 over the mask electrode 220 and coating 221 . The insulating layer 222 may be, for example but not limited to, silicon dioxide and borophosphosilicate glass (BPSG) applied via CVD. After the insulating layer 222 is applied, the top surface of the semiconductor substrate may not be uniform. The insulating layer 222 may then be planarized to form a uniform top surface of the semiconductor substrate.

Figure 2R shows a cross-sectional side view of steps for forming drain and gate contacts in an improved iT-FET device according to various aspects of the present invention. After planarization, a drain mask 235 is applied to the surface of the insulating layer. Drain mask 235 may be applied by any suitable method, such as but not limited to photolithography. Etching is then performed on the upper surface of the semiconductor substrate. The etchant removes the portion of the insulating layer not covered by the drain electrode mask 235 . The heavily doped drain region 226 is exposed after the etch process. In addition, the mask may expose the gate bar electrode 225 after etching. This prepares the top of the semiconductor substrate for forming drain contacts and gate-strip contacts. After this etching and the final shape of the gate insulation 224 and the mask insulation 223 , the insulating layer of the gate bar region 227 is finally defined. The drain contact mask 235 may be removed after etching by any suitable mask removal method, such as chemical cleaning, plasma ashing, or planarization.

Figure 2S shows a cross-sectional side view of steps for forming drain and gate contacts in an improved iT-FET device according to various aspects of the present invention. After removing the mask, a metal layer 228 may be applied to the top surface of the semiconductor substrate. A metal layer may cover the exposed gate bar electrodes 225 forming gate bar contact plugs 229 . The gate bar contact may include a complementary metal coating 236 . In addition, the metal layer 228 may cover the drain contact region 226 forming the drain contact plug 231 . The drain contact plug 231 may include a complementary metal coating 232 . The metal coating can be metal silicide, such as but not limited to titanium, cobalt silicide. Complementary metal plugs for drain contacts and gate bar contacts may be, for example but not limited to, tungsten.

Figure 2T shows a side view cross-section of steps for forming drain and gate bars in an improved iT-FET device in accordance with aspects of the present invention. A metal layer mask is applied to the metal layer surface over the gate bar metal 233 and the drain metal 234 . The metal layer mask can be applied by any suitable method, such as photolithography. An etching process is applied to the mask metal layer to form the final gate bar metal 233 and drain metal layer 234 . The mask can be removed by any suitable process, such as, but not limited to, chemical etching, plasma ashing. Therefore, the improved iT-FET device has an internal combination of source-body contact and mask electrode. The combination of the source-body contact and the mask electrode reduces the Rds _-on of the device by this masking effect. The recessed gate electrode reduces the gate-to-drain capacitance. In addition, the improved iT-FET device can be fabricated using existing trench FET fabrication equipment with an additional masking step, which reduces the overall manufacturing cost of the improved iT-FET device relative to bottom-source LDMOS.

Aspects of the present invention, integral source-body short and shield electrode allow for improved iT-FET devices with relatively low gate-to-drain capacitance and low on-state (R _ds-on ) resistance from drain to source. This device configuration allows for faster switching speeds. Furthermore, the process to fabricate such a device can be achieved with a relatively simple and inexpensive process flow.

While the above is a complete description of the preferred embodiment of the invention, various alternatives, modifications and equivalents may be used. Therefore, the scope of the present invention should be determined not with reference to the above description, but should be determined with reference to the scope of the appended patent applications and all equivalent scopes thereof. Any feature, whether preferred or not, can be combined with any other feature, whether preferred or not. In the scope of subsequent patent applications, the indefinite article "A" or "An" refers to the quantity of one or more items following the article, unless otherwise expressly stated. The scope of the appended patent applications should not be construed to include means-plus-function limitations, unless such limitation is expressly recited in a given claim using the phrase "means". Any element in the claims of a patent application that does not expressly state "means for" performing a particular function shall not be construed as a "means" or "step" clause under 35 U.S.C. § 112, Section 6.

101: source layer 102: Epitaxial layer 103: body contact area 104:Heavily doped drain region 105: Drift Zone 106: insulation layer 107: gate electrode 108: Gate bar 109: mask insulator 110: mask electrode 111: material coating 112: drain 113: drain plug 114: Diffusion barrier layer 115: gate metal 116: contact plug 117: material coating 120: gate trench 121: Groove 201: source layer 202: epitaxial layer 203: mask 204: gate trench 205: insulation layer 206: gate electrode layer 207: Gate bar mask 208: electrode 209: gate electrode 210: insulation 211: Drain area mask 212:Heavily doped drain region 213: drifting area 214: insulating layer 215: mask trench mask 216: body contact area 217: Mask groove 218: Supplementary material 219: Mask trench electrode layer 220: mask trench electrode 221: coating 222: insulating layer 223: mask insulation 224: gate insulation 225: Gate bar electrode 226: drain contact area 227: Gate strip area 228: metal layer 229: Gate bar contact plug 230: gate bar groove 231: drain contact plug 232: Complementary metal coating 233: Gate bar metal 234: drain metal layer 235: drain mask 236: Complementary metal coating

Other features and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the following drawings, in which: Figure 1 shows a side cross-sectional view of an improved iT-FET device having a combination of source-body shorting and a mask electrode in accordance with aspects of the present invention. Figure 2A shows a cross-sectional view of a source layer and an epitaxial layer of a semiconductor substrate during the fabrication of an improved iT-FET in accordance with aspects of the present invention. Figure 2B shows a side cross-sectional view of gate trenches fabricated in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2C shows a side cross-sectional view of gate insulators fabricated in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2D shows a side cross-sectional view of a gate electrode fabricated in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2E shows a side cross-sectional view of a gate electrode fabricated in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2F shows a side cross-sectional view of the fabrication of gate electrodes and gate bars in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2G shows a side cross-sectional view of the gate electrodes and gate bars prepared in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2H shows a side cross-sectional view of the fabrication of gate electrodes and gate bars in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2I shows a side cross-sectional view of the fabrication of drain and drift regions in an improved iT-FET device according to various aspects of the present invention. Figure 2J shows a cross-sectional side view of a planarization process prior to fabrication of a mask structure in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2K shows a side cross-sectional view of the fabrication of a source-body short and mask structure in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2L shows a side cross-sectional view of a source-body short circuit and mask structure fabricated in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2M shows a side cross-sectional view of the fabrication of source-body short and mask structures in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2N shows a side cross-sectional view of the fabrication of source-body short and mask structures in an improved iT-FET device in accordance with various aspects of the present invention. Figure 20 shows a side cross-sectional view of the fabrication of source-body short and mask structures in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2P shows a side cross-sectional view of the fabrication of source-body short and mask structures in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2Q shows a side cross-sectional view during the planarization process prior to the fabrication of tabs in an improved iT-FET device in accordance with aspects of the present invention. Figure 2R shows a side cross-sectional view of drain contact openings and gate contact openings fabricated in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2S shows a side cross-sectional view of drain contact plugs and gate contact plugs prepared in an improved iT-FET device in accordance with various aspects of the present invention. Figure 2T shows a side cross-sectional view of drain metal and gate metal bars fabricated in an improved iT-FET device in accordance with various aspects of the present invention.

101: source layer

102: Epitaxial layer

103: body contact area

104:Heavily doped drain region

105: Drift Zone

106: insulation layer

107: gate electrode

108: Gate bar

109: mask insulator

110: mask electrode

111: material coating

112: drain

113: drain plug

114: Diffusion barrier layer

115: gate metal

116: contact plug

117: material coating

120: gate trench

121: Groove

Claims (19)

An inverse field-effect transistor (iT-FET) semiconductor device comprising a source layer at the bottom and a heavily doped drain region disposed on the top of a semiconductor substrate: a vertical current conduction channel between the source layer and the drain region, controlled by a trench gate disposed in a gate trench lined with an insulating material; a mask trench disposed between adjacent gate trenches, the heavily doped drain region disposed near the top of the substrate surrounding the shield trench and an upper portion of the gate trench; A doped body region is disposed in the substrate and surrounds the lower portion of the mask trench; a mask electrode in the mask trench extends upward from the source layer to electrically short the source layer and the body region, wherein the mask electrode extends upward to the heavily doped drain region in the mask trench and is insulated from the heavily doped drain region to serve as the mask electrode. The iT-FET semiconductor device as claimed in claim 1, wherein the mask structure further comprises a conductive plug in the mask trench extending from the source layer upwardly through the body region to at least a part of a drift region. The iT-FET semiconductor device according to claim 1, wherein the mask electrode further includes a tungsten plug in the mask trench extending upward from the source layer. The iT-FET semiconductor device according to claim 1, wherein the mask electrode further includes a titanium silicide plug in the mask trench extending upward from the source layer. The iT-FET semiconductor device as claimed in claim 1, wherein the source layer of the semiconductor substrate is heavily doped with impurities of the first conductivity type, and the semiconductor substrate further includes an epitaxial layer formed above the source layer, doped with impurities of the second conductivity type, wherein the second conductivity type is opposite to the first conductivity type. The iT-FET semiconductor device according to claim 5, wherein the body region is formed in the epitaxial layer and is heavily doped with impurities of the second conductivity type. The iT-FET semiconductor device as claimed in claim 5, wherein the heavily doped drain region is formed in the epitaxial layer and is heavily doped with ions of the first conductivity type. The iT-FET semiconductor device as claimed in claim 7, wherein an insulator layer between the mask electrode and the heavily doped drain region and the drift region is thicker than an insulating material portion between the gate electrode and the source layer and the body region. The iT-FET semiconductor device according to claim 7, further comprising a drift region between the body region and the heavily doped drain region formed in the epitaxial layer, wherein the drift region is more lightly doped with impurities of the first conductivity type than the heavily doped drain region. The iT-FET semiconductor device according to claim 9, wherein the drift region has an impurity concentration gradient, wherein the impurity concentration is highest near the heavily doped drain region, and the impurity concentration decreases in the epitaxial layer deeper below the heavily doped drain region. The iT-FET semiconductor device as claimed in claim 1, further comprising a conductive drain contact plug in contact with the heavily doped drain region and the drain metal. A method for preparing an iT-FET semiconductor device, comprising: a) forming an epitaxial layer doped with impurities of a second conductivity type on a substrate heavily doped with impurities of a first conductivity type, wherein the first conductivity type is opposite to the second conductivity type, wherein the substrate is used as the source layer; b) forming a gate trench through the epitaxial layer and into the source layer; c) lining the mask trench with an insulating material and forming a gate electrode in the gate trench; d) forming a drift region and a heavily doped drain region doped with impurities of the first conductivity type in the epitaxial layer; e) forming the mask trench in the epitaxial layer through the heavily doped drain region and the drift region; f) forming a body contact region at the bottom of the mask trench heavily doped with impurities of the second conductivity type; g) Lining the trench with insulating material; h) deepening the mask trench to the source layer through the body contact region, and forming a mask structure in the mask trench, wherein the mask structure extends upward from the source layer to electrically short the source layer and the body region, wherein the mask structure extends upward to the heavily doped drain region and is insulated from the drain region; i) A drain is formed above the epitaxial layer. The method for fabricating an iT-FET semiconductor device according to Claim 12, wherein the mask structure includes a mask electrode extending downward from the bottom of the drain region through the mask trench and the body region to reach the source. The method for fabricating an iT-FET semiconductor device as claimed in item 13, wherein fabricating the mask electrode further includes fabricating a conductive plug extending upwardly from the source electrode through the body region and reaching at least a part of the drain electrode region in the mask trench. The method for manufacturing an iT-FET semiconductor device as claimed in claim 14, wherein the conductive plug can be a tungsten plug extending upward from the source in the mask trench. The method for manufacturing an iT-FET semiconductor device according to claim 14, wherein the conductive plug is lined with titanium silicide, and extends upward from the source in the mask trench. The method for manufacturing an iT-FET semiconductor device according to Claim 12, wherein forming the drift region further includes forming an impurity concentration gradient in the drift region, wherein the impurity concentration is highest near the drain region, and the ion concentration decreases in the epitaxial layer deeper below the heavily doped drain region. The method for fabricating an iT-FET semiconductor device as claimed in claim 12, wherein h) further includes lining the sidewall of the mask trench with a mask insulator thicker than the insulating material in the gate trench. The method for fabricating an iT-FET semiconductor device as claimed in claim 12, wherein preparing a drain above the epitaxial layer further includes preparing a conductive drain contact plug to be in contact with the heavily doped drain region and the drain metal above the drain contact plug.