CN105097937B - A kind of transverse conductance structure SIC MOSFET power devices - Google Patents
A kind of transverse conductance structure SIC MOSFET power devices Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The present embodiments relate to a kind of transverse conductance structure SIC MOSFET power devices, the SiC MOSFET power devices include from top to bottom：Grid, SiO2Spacer medium layer, N+Drain region, N+Source region, P+Ohmic contact regions, p-well, N‑Drift region and p-type SiC substrate；Wherein, N+Drain region, N+Source region and P+Ohmic contact regions are horizontally disposed with, N+Source region and P+Ohmic contact regions are located in p-well；In SiO2Spacer medium layer and N‑Interface between drift region has one layer of plasma enhanced CVD PECVDSiO2Boundary layer.
Description
Technical field
The present invention relates to microelectronics technology, more particularly to a kind of transverse conductance structure SIC MOSFET power devices.
Background technology
SiC becomes one kind of manufacture high temperature, high-power electronic device with its excellent physicochemical characteristics and electrology characteristic
Most advantageous semi-conducting material, and the power device quality factor with much larger than Si materials.SiC power devices metal-
Oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor,
MOSFET research and development) start from the 1990s, it is with input impedance is high, switching speed is fast, working frequency is high, high temperature resistant is high
The series of advantages such as pressure, achieve extensively in switching power supply, high-frequency heating, automotive electronics and power amplifier etc.
General application.
However, the main material of SiC power MOS (Metal Oxide Semiconductor) device gate mediums is the SiO of thermal oxide generation at present2, but SiC and SiO2
Contact interface it is second-rate, highdensity interfacial state and interface roughness cause device channel mobility and conducting resistance seriously to be moved back
Change, or even the performance of the device based on SiC is not reached the performance of the device based on Si also.Although through process modification, annealing
During be passed through nitride composition, can partly reduce interfacial state, but for SiC in oxidizing process and SiO2The C of interface is former
Sub- complex compound problem is unable to the solution of essence, also so that the channel mobility of SiC is very low always, seriously restricts SiC power
The development of device.
The content of the invention
A kind of the defects of the purpose of the present invention is for the prior art, there is provided transverse conductance structure SIC MOSFET power devices
Part, in SiO2Spacer medium and N-Interface between drift region has one layer of plasma enhanced CVD PECVD
SiO2Boundary layer, can effectively solve the problem that SiC and SiO in oxidizing process2Contact interface C atom complex produce the defects of to boundary
The influence of face state and mobility, so as to improve the performance of device.
To achieve the above object, the present invention provides a kind of transverse conductance structure SIC MOSFET power devices, from upper and
Under include：Grid, SiO2Spacer medium layer, N+Drain region, N+Source region, P+Ohmic contact regions, p-well, N-Drift region and p-type SiC substrate；
Wherein, N+Drain region, N+Source region and P+Ohmic contact regions are horizontally disposed with, N+Source region and P+Ohmic contact regions are located in p-well；
In SiO2Spacer medium layer and N-Interface between drift region has one layer of plasma enhanced CVD PECVD SiO2
Boundary layer.
Preferably, the PECVD SiO2The formation of boundary layer includes：
To with N+Drain region, N+Source region, P+Ohmic contact regions, p-well, N-The SiC substrate surface of drift region at 200 DEG C into
Row ultra-violet oxidation；
RCA is cleaned so that forms Si interfacial structures on the surface；
PECVD pretreatments are carried out in 300 DEG C of oxygen atmospheres, the Si interfacial structures are oxidized to SiO2Boundary layer.
Preferably, the N+Source region and P+Also there is source metal on ohmic contact regions；The N+Also have on drain region
Drain metal.
Preferably, SiO2The thickness of boundary layer is 1-2nm.
Preferably, the N-Drift region is specially：
Thickness is 8-9 μm, and doping concentration is 1 × 1015cm-3-2×1015cm-3Nitrogen ion doping N-Epitaxial layer.
Preferably, the depth of the p-well is 0.5 μm, and doping concentration is 3 × 1018cm-3。
Preferably, the N+The depth of source region is 0.2 μm, and doping concentration is 1 × 1019cm-3。
Preferably, the P+The depth of ohmic contact regions is 0.2 μm, and doping concentration is 2 × 1019cm-3。
Preferably, the SiO2The thickness of spacer medium layer is 50-100nm.
Transverse conductance structure SIC MOSFET power devices provided in an embodiment of the present invention, in SiO2Spacer medium and N-Drift
The interface moved between area has a floor plasma enhanced CVD PECVD SiO2Boundary layer, can effectively solve the problem that oxygen
SiC and SiO during change2The influence to interfacial state and mobility of the defects of producing of contact interface C atom complex, so as to carry
The performance of high device.
Brief description of the drawings
Fig. 1 is a kind of structure chart of transverse conductance structure SIC MOSFET power devices provided in an embodiment of the present invention；
Fig. 2 is a kind of preparation method stream of transverse conductance structure SIC MOSFET power devices provided in an embodiment of the present invention
Cheng Tu；
Fig. 3 is one of technical process schematic diagram of LDMOSFET power devices provided in an embodiment of the present invention；
Fig. 4 is the two of the technical process schematic diagram of LDMOSFET power devices provided in an embodiment of the present invention；
Fig. 5 is the three of the technical process schematic diagram of LDMOSFET power devices provided in an embodiment of the present invention；
Fig. 6 is the four of the technical process schematic diagram of LDMOSFET power devices provided in an embodiment of the present invention；
Fig. 7 is the five of the technical process schematic diagram of LDMOSFET power devices provided in an embodiment of the present invention；
Fig. 8 is the six of the technical process schematic diagram of LDMOSFET power devices provided in an embodiment of the present invention；
Fig. 9 is the seven of the technical process schematic diagram of LDMOSFET power devices provided in an embodiment of the present invention；
Figure 10 is the eight of the technical process schematic diagram of LDMOSFET power devices provided in an embodiment of the present invention.
Embodiment
Below by drawings and examples, technical scheme is described in further detail.
An embodiment of the present invention provides a kind of transverse conductance structure SIC MOSFET power devices, it is specific as shown in Figure 1,
SiC MOSFET power devices include from top to bottom：Grid 9, SiO2Spacer medium layer 8, N+Drain region 6, N+Source region 4, P+Ohm connects
Touch area 5, p-well 3, N-Drift region 2 and p-type SiC substrate 1；
Wherein, N+Drain region 6, N+Source region 4 and P+Ohmic contact regions 5 are horizontally disposed, N+Source region 4 and P+Ohmic contact regions 5 are located at P
In trap 3；In SiO2Spacer medium layer 8 and N-Interface between drift region 2 has one layer of plasma enhanced CVD
PECVD SiO2Boundary layer.PECVD SiO2Boundary layer is formed by N+Drain region 6, N+Source region 4, P+Ohmic contact regions
5th, p-well 3, N-The surface of the SiC substrate 1 of drift region 2 carries out ultra-violet oxidation at 200 DEG C, then carries out RCA cleanings so that
Si interfacial structures are formed on the surface, then PECVD pretreatments are carried out in 300 DEG C of oxygen atmospheres, by the Si interfacial structures
It is oxidized to SiO2Boundary layer.
' convex ' shape area on P type substrate 1 is N-Drift region, specially thickness is 8-9 μm in this example, and doping concentration is
1×1015cm-3-2×1015cm-3Nitrogen ion doping N-Epitaxial layer；
The depth of p-well 3 is 0.5 μm, and doping concentration is 3 × 1018cm-3；
N+Source region 4 is in p-well 3, N+The depth of source region is 0.2 μm, and doping concentration is 1 × 1019cm-3。
N+The depth in drain region 6 is 0.2 μm, and doping concentration is 1 × 1019cm-3。
P+Ohmic contact regions 5 are in p-well 3 close to N+Source region 4, depth are 0.2 μm, and doping concentration is 2 × 1019cm-3；
SiO2The as grid oxygen oxide layer of spacer medium layer 8, thickness 50-100nm；
Grid 9 is polysilicon gate, is the polysilicon that thickness is the doping of 200nm phosphonium ions, and doping concentration is 5 × 1019cm-3
To 1 × 1020cm-3；
N+Source region 4 and P+Also there is source metal 10 on ohmic contact regions 3, be specially the Al/Ti conjunctions of 300nm/100nm
Gold；
N+Also there is drain metal 11 on drain region 6, be specially the Al/Ti alloys of 300nm/100nm.
Raising vertical conductive structure SiC MOSFET power devices provided in an embodiment of the present invention, in SiO2Spacer medium with
N-Interface between drift region has one layer of plasma enhanced CVD PECVD SiO2Boundary layer, can effectively solve
Certainly SiC and SiO in oxidizing process2The influence to interfacial state and mobility of the defects of producing of contact interface C atom complex, from
And improve the performance of device.And in deposit SiO2Before boundary layer, the C of SiC epitaxial layer is restored by ultra-violet oxidation
Come, the oxide of C is combined to form with oxonium ion, is discharged in a gaseous form, the surface SiO for then again forming ultra-violet oxidation2
Layer carries out RCA cleanings so that surface forms Si interfacial structures, then is aoxidized by PECVD and form SiO2Boundary layer, so as to be formed good
Contact interface.
The transverse conductance structure SIC MOSFET power devices provided for a better understanding of the present invention, below to its technique
Processing procedure is introduced.
It should be noted that the preparation side of transverse conductance structure SIC MOSFET power devices provided in an embodiment of the present invention
Method, in the making technology for the SiC MOSFET that can be used for various transverse conductance structures, specifically can include but is not limited to：Laterally
Diffused MOS field-effect should manage (Laterally Diffused MOSFET, LDMOSFET).Although in this implementation
In the following specific embodiment schematic diagrames of example illustrated by taking LDMOSFET as an example, but and non-limiting provided in this embodiment carried
The method of high channel mobility is only applicable in the manufacturing process of LDMOSFET.
Fig. 2 is raising transverse conductance structure SIC MOSFET power device channel mobilities provided in an embodiment of the present invention
Method flow diagram.Fig. 3-Figure 10 is the technical process schematic diagram of LDMOSFET power devices provided in an embodiment of the present invention.Below
By taking Fig. 2 as an example, and Fig. 3-Figure 10 is combined, to the raising transverse conductance structure SIC MOSFET power device channel mobilities of the present invention
The method of rate is described in detail.
As shown in Fig. 2, the preparation method of the transverse conductance structure SIC MOSFET of the embodiment of the present invention includes：
Step 210, the N of MOSFET is formed by epitaxy technique in p-type SiC substrate-Drift region；
Specifically, as shown in figure 3, N is formed by epitaxy technique in p-type SiC substrate 1-Drift region 2.
By taking the manufacturing process of LDMOS as an example, the concrete technology condition of epitaxy technique is：Temperature is 1570 DEG C, and pressure is
100mbar, reacting gas are silane and propane, and carrier gas is pure hydrogen, and impurity source is liquid nitrogen.The N of formation-Drift region
Epitaxy layer thickness be 8-9 μm, doping concentration be 1 × 1015cm-3~2 × 1015cm-3。
Step 220, in N-Source region and the drain region of MOSFET is formed in drift region by injection technology；
Specifically, before source region is formed, it is necessary first to form well region.
Preparing for well region can be by the N that is adulterated in Nitrogen ion-Multiple aluminium ion Selective implantation shape is carried out on drift layer
Into.Wherein, implantation temperature is 650 DEG C, forms depth as 0.5 μm, doping concentration is 3 × 1018cm-3P-well 3, as shown in Figure 4；
Its specific embodiment can include：Deposited by low pressure hot wall chemical vapor deposition method on SiC epitaxial wafers surface
A layer thickness is 0.2 μm of SiO2Layer, then redeposited thickness is that 1 μm of Al is used as the barrier layer of p-well ion implanting, is passed through
Photoetching forms p-well injection region with etching；Four Al ion implantings are carried out to p-well injection region under 650 DEG C of environment temperature, first
The Implantation Energy of 450keV, 300keV, 200keV and 120keV are used afterwards, are 7.97 × 10 by implantation dosage13cm-2、4.69×
1013cm-2、3.27×1013cm-2With 2.97 × 1013cm-2Al ion implantation to p-well injection region, form depth as 0.5 μm, mix
Miscellaneous concentration is 3 × 1018cm-3P-well 3；Surface clean is carried out using RCA cleaning standards, the protection of C films is made after drying；Then exist
Ion-activated annealing 10min is carried out in 1700~1750 DEG C of argon atmosphers.
After p-well 3 is formed, in the p-well 3 and N-Source and drain injection is carried out in drift region, is selected by multiple Nitrogen ion
Property injection, implantation temperature is 650 DEG C, forms depth as 0.2 μm, and doping concentration is 1 × 1019cm-3N+Source region 4 and N+Drain region 6,
As shown in Figure 5.
Its specific embodiment can include：By low pressure hot wall chemical vapor deposition method in silicon carbide plate front deposition one
Layer thickness is 0.2 μm of SiO2Layer, the Al that then redeposited thickness is 1 μm are used as N+Source, the barrier layer of drain region ion implanting,
N is formed by photoetching and etching+Source region injection region and N+Drain region injection region；To N under 650 DEG C of environment temperature+Source region is injected
Area and N+Drain region injection region carries out N~+ implantation twice, successively using the Implantation Energy of 80keV, 30keV, is by implantation dosage
3.9×1014cm-2、1.88×1014cm-2, it is injected into N+Source region injection region N+Drain region injection region, forms depth as 0.2 μm, doping
Concentration is 1 × 1019cm-3N+Source region 4 and N+Drain region 6；Surface clean is carried out using RCA cleaning standards, C films are made after drying and are protected
Shield；Then ion-activated annealing 10 minutes is carried out in 1700~1750 DEG C of argon atmospheres.
, will also be in the N of Nitrogen ion doping after source region is formed-Multiple aluminium ion Selective implantation is carried out on drift layer,
Implantation temperature is 650 DEG C, forms depth as 0.2 μm, doping concentration is 2 × 1019cm-3P+Ohmic contact regions 5, as shown in Figure 6.
Its specific embodiment can include：By low pressure hot wall chemical vapor deposition method in silicon carbide plate front deposition one
Layer thickness is 0.2 μm of SiO2Layer, then redeposited thickness is that 1 μm of Al is used as the barrier layer of P+ contact zones ion implanting,
P is formed by photoetching and etching+Contact injection region；To P under 650 DEG C of environment temperature+Contact zone carries out Al ions twice and notes
Enter, successively the Implantation Energy of 90keV, 30keV, be 1.88 × 10 by implantation dosage14cm-2、3.8×1014cm-2Aluminium ion, note
Enter to P+Ohmic contact regions injection region, forms depth as 0.2 μm, doping concentration is 2 × 1019cm-3P+Contact zone 5.
Step 230, the epitaxial surface of the SiC epitaxial wafers to having formed the source region and drain region carries out ultraviolet at 200 DEG C
Line aoxidizes；
Specifically, oxidizing temperature is 200 DEG C, the time is 10 minutes, forms thin oxygen layer 7, as shown in Figure 7.
Epi-layer surface is handled using ultraviolet low-temperature oxidation, can effectively control oxide thickness, realization can
The oxide thin layer of the epitaxial surface of control, in order to be pre-processed to SiC interfaces, is pre-oxidized the surface of SiC epitaxial wafers,
Form SiO2With the oxide of C.Wherein the oxide of C includes CO and CO2, they can be discharged in a gaseous form.Therefore SiC extensions
The surface of piece leaves behind thin layer SiO2。
Step 240, RCA is cleaned so that forms Si interfacial structures in the epitaxial surface；
Specifically, RCA cleanings include the following steps：
A, SiC extensions are placed in 90 DEG C of SPM solution and cleaned 15 minutes, wash away ionized water；
B, cleaned 30 seconds in DHF solution, wash away ionized water；
C, cleaned 10 minutes in 70 DEG C of SC1 solution, wash away ionized water；
D, cleaned 10 minutes in 70 DEG C of SC2 solution again, wash away ionized water, and dry；
Wherein, the SPM solution is the concentrated sulfuric acid and the mixed solution of hydrogen peroxide；The DHF solution is that concentration is
The hydrofluoric acid solution of 0.5%-2%；The SC1 solution is the mixed solution of ammonium hydroxide, hydrogen peroxide and deionized water；The SC2
For the mixed solution of hydrochloric acid, hydrogen peroxide and deionized water.
Step 250, the SiC epitaxial wafers are subjected to plasma enhanced CVD in 300 DEG C of oxygen atmospheres
(PECVD) pre-process, the Si interfacial structures of the epitaxial surface are oxidized to SiO2Boundary layer；
Specifically, SiC epitaxial wafers are put into PECVD device, oxygen is passed through at 300 DEG C 60 seconds, by the extension table
Face is oxidized to the SiO of 1-2nm2Boundary layer.
Step 260, in the SiO2Oxidation deposit and annealing are carried out on boundary layer, forms spacer medium layer；
Specifically, forming 1-2nm SiO2After boundary layer, it is passed through at 300 DEG C in the state of oxygen and is passed through silicon again
Alkane, deposits the SiO of 100nm2Spacer medium 8, as shown in Figure 8.Then, under oxygen atmosphere, 800 DEG C are annealed 60 minutes.Finally
Pass through photoetching, etching SiO2Spacer medium 8 forms gate oxide.
Step 270, polysilicon gate is prepared；
Specifically, with low pressure hot wall chemical vapor deposition method epitaxial wafer surface deposition growing 200nm polysilicon, specifically
Process conditions can be：Temperature is 600-650 DEG C, pressure 60-80Pa, and reacting gas uses silane and hydrogen phosphide, carrying gas
Body uses helium.
Then the polysilicon on gate oxide is retained by photoetching, etching, forms doping concentration as 5 × 1019cm-3, it is thick
The polysilicon gate 9 for 200nm is spent, it is specific as shown in Figure 9.
Step 280, source, leakage metal electrode are prepared, so as to form the transverse conductance structure SIC MOSFET.
Specifically, as shown in Figure 10, in N+And P+The Al/Ti alloys of ohmic contact regions area deposition 300nm/100nm, shape
Into source metal electrode 10 and drain metal electrode 11.
Finally, at a temperature of 1100 ± 50 DEG C, 3 minutes Ohmic contacts for forming electrode of annealing in nitrogen atmosphere to sample.
It is consequently formed transverse conductance structure SIC MOSFET.
Method provided by the present invention, grid oxygen deposit before, using ultraviolet low-temperature oxidation to epi-layer surface at
Reason, can effectively control oxide thickness, and SiC interfaces complete Si faces structure is occurred by RCA cleanings.Then O from
The Si interfacial structures of surface of SiC are pre-processed under sub- atmosphere, the SiO of oxidation generation 1-2nm2Boundary layer, as SiC with
SiO2 interfaces, the gate oxide that can be prepared with subsequent technique form good interracial contact, while by the C atoms at interface
Gas discharge is formed, conventional high-temperature oxidation technology is thus solved and prepares SiC caused by gate oxide and SiO2Contact circle
The problem of interfacial state caused by C atom complex is high in face, and carrier mobility is low, method provided by the invention can be effective
Raising device performance.
Professional should further appreciate that, be described with reference to the embodiments described herein each exemplary
Unit and algorithm steps, can be realized with electronic hardware, computer software or the combination of the two, hard in order to clearly demonstrate
The interchangeability of part and software, generally describes each exemplary composition and step according to function in the above description.
These functions are performed with hardware or software mode actually, application-specific and design constraint depending on technical solution.
Professional technician can realize described function to each specific application using distinct methods, but this realization
It is it is not considered that beyond the scope of this invention.
The step of method or algorithm for being described with reference to the embodiments described herein, can use hardware, processor to perform
Software module, or the two combination are implemented.Software module can be placed in random access memory (RAM), memory, read-only storage
(ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In any other form of storage medium well known to interior.
Above-described embodiment, has carried out the purpose of the present invention, technical solution and beneficial effect further
Describe in detail, it should be understood that the foregoing is merely the embodiment of the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution, improvement and etc. done, should all include
Within protection scope of the present invention.
Claims (7)
1. a kind of transverse conductance structure SIC MOSFET power devices, it is characterised in that the SiC MOSFET power devices are certainly
Include under above：Grid, SiO2Spacer medium layer, N+Drain region, N+Source region, P+Ohmic contact regions, p-well, N-Drift region and p-type SiC
Substrate；
Wherein, N+Drain region, N+Source region and P+Ohmic contact regions are horizontally disposed with, N+Source region and P+Ohmic contact regions are located in p-well；
SiO2Spacer medium layer and N-Interface between drift region has one layer of plasma enhanced CVD PECVD SiO2Boundary
Surface layer, the SiO2The thickness of boundary layer is 1-2nm；
The PECVD SiO2The formation of boundary layer includes：
To with N+Drain region, N+Source region, P+Ohmic contact regions, p-well, N-The SiC substrate surface of drift region carries out ultraviolet at 200 DEG C
Line aoxidizes；
RCA is cleaned so that forms Si interfacial structures on the surface；
PECVD pretreatments are carried out in 300 DEG C of oxygen atmospheres, the Si interfacial structures are oxidized to SiO2Boundary layer.
2. transverse conductance structure SIC MOSFET power devices according to claim 1, it is characterised in that the N+Source region
And P+Also there is source metal on ohmic contact regions；The N+Also there is drain metal on drain region.
3. transverse conductance structure SIC MOSFET power devices according to claim 1, it is characterised in that the N-Drift
Area is specially：
Thickness is 8-9 μm, and doping concentration is 1 × 1015cm-3-2×1015cm-3Nitrogen ion doping N-Epitaxial layer.
4. transverse conductance structure SIC MOSFET power devices according to claim 1, it is characterised in that the p-well
Depth is 0.5 μm, and doping concentration is 3 × 1018cm-3。
5. transverse conductance structure SIC MOSFET power devices according to claim 3, it is characterised in that the N+Source region
Depth be 0.2 μm, doping concentration be 1 × 1019cm-3。
6. transverse conductance structure SIC MOSFET power devices according to claim 1, it is characterised in that the P+Ohm
The depth of contact zone is 0.2 μm, and doping concentration is 2 × 1019cm-3。
7. transverse conductance structure SIC MOSFET power devices according to claim 1, it is characterised in that the SiO2Every
Thickness from dielectric layer is 50-100nm.
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