CN102437034A - Method for forming nickel silicide blocking layer - Google Patents
Method for forming nickel silicide blocking layer Download PDFInfo
- Publication number
- CN102437034A CN102437034A CN2011102352209A CN201110235220A CN102437034A CN 102437034 A CN102437034 A CN 102437034A CN 2011102352209 A CN2011102352209 A CN 2011102352209A CN 201110235220 A CN201110235220 A CN 201110235220A CN 102437034 A CN102437034 A CN 102437034A
- Authority
- CN
- China
- Prior art keywords
- metal layer
- nickel
- silicon substrate
- metal
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method for forming a nickel silicide blocking layer, which mainly comprises the following steps that: the cleaning treatment is carried out on the silicon substrate surface for removing oxides on the silicon substrate surface, and a first metal layer is deposited on a silicon substrate; and the oxidation resistant treatment is carried out on the first metal layer, then, a second metal layer is deposited on the first metal layer, and the first metal layer and the second metal layer jointly form a metal blocking layer of the silicon substrate surface. The first metal layer deposited on the silicon substrate surface is nickel or NiPt, after the first metal layer is deposited on the silicon substrate surface, hydrogen gas capable of preventing the nickel from being oxidized is continuously introduced into the first metal layer surface for 1 second to 5 minutes under the conditions of the temperature being 20 DEG C to 100 DEG C and the pressure being 0.01 to 1MPa, then, the second metal layer is deposited on the first metal layer and is titanium nitride, and the first metal layer and the second metal layer jointly form the metal blocking layer of the silicon substrate surface.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, wherein, relate in particular to a kind of method that forms the nickel silicide barrier layer.
Background technology
In semiconductor machining industry, as the method for a kind of processing with integrated low electrical resistant material on the zone of defining in advance of the semiconductor structure of formation semiconductor device, it is well-known forming self-aligned silicide.Particularly, self-aligned silicide technology is that a kind of silicon area that makes semiconductor structure and metal reaction are to form the method for silicide regions.This self aligned silicide can be selected to form on semiconductor structure, and needn't patterning or the silicide that deposited of etching, uses forming some low-resistance zones.
Along with the micro of processing procedure, to 65nm and following, nickel has generally been made to be used for the silicon materials reaction so that on semiconductor structure, form the metal of self-aligned silicide.But the activity of nickel is very strong, is easy to and oxygen reaction, forms oxide layer on the surface, thereby has improved the resistance of nickel silicide, is unfavorable for the raising of transistor performance.Nickel oxide is general at present to adopt wet method to handle, and like SC2, SC-2 is the acid solution of H2O2 and HCL, and it has extremely strong oxidizability and complexing, can generate salt with the metal function before the oxygen and be removed with deionized water rinsing.The soluble complexes that oxidized metal ion and CL-effect generate also is removed with deionized water rinsing.Follow the raising of IC integrated level, the cleanliness factor of silicon chip surface is most important with high finished product rate for obtaining IC device high-performance, so to the purpose removed with cleaning and removing with just require more strictness.Cleaning is to stain for reducing, and can influence device performance because of staiing, and causes integrity problem, reduces rate of finished products, and this just requires before next step technology of every layer or down, must clean completely before one deck.As everyone knows, wet-cleaned is being accepted extensively on semiconductor production very early and is being used, and many wet processings have shown the performance that it is superior, but in cleaning process, has a lot of possible situations to cause because of what wet-cleaned caused and stain.So after deposit nickel, deposit one deck titanium nitride was as the barrier layer, to stop the oxidation of nickel on nickel afterwards.But there is the possibility of oxidation in wafer in the transfer process before the deposit titanium nitride, in case oxidation can cause increasing of nickel silicide resistance, reduce transistorized performance.Reduce the step of making technology, strengthened the stability of technology.
Summary of the invention
The invention discloses a kind of method that forms the nickel silicide barrier layer; The purpose of this invention is to provide a kind of nickel that prevents by the process of airborne dioxygen oxidation; In order to solve in the prior art after deposited nickel layer on the silicon substrate, there is oxidized problem easily in nickel in the transfer process before the deposit titanium nitride layer.
Above-mentioned purpose of the present invention realizes through following technical scheme:
A kind of method that forms the nickel silicide barrier layer mainly comprises following step:
Carry out clean in surface of silicon substrate, to remove the oxide of surface of silicon substrate;
Deposition one deck the first metal layer on said silicon substrate;
Said the first metal layer is carried out anti-oxidant treatment, on the first metal layer, deposit second metal level afterwards again, said first, second metal level constitutes the metal barrier of surface of silicon substrate jointly;
Described a kind of method that forms the nickel silicide barrier layer, the first metal layer of said surface of silicon deposit is nickel or NiPt;
Described a kind of method that forms the nickel silicide barrier layer, said anti-oxidant technology are to feed a kind of gas that prevents that nickel is oxidized to the first metal layer surface;
The method on described any formation nickel silicide barrier layer, said gas is preferably hydrogen;
Described a kind of method that forms the nickel silicide barrier layer, second metal level of said deposit is a kind of titaniferous compound;
Described a kind of method that forms the nickel silicide barrier layer, said second metal level is a titanium nitride;
Described a kind of method that forms the nickel silicide barrier layer, the temperature of the antioxidation processing technology of this method are that 20 ℃ to 100 ℃, pressure are 0.01 to 1Mpa, and the time is 1 second to 5 minutes.
In sum, after deposited nickel layer on the silicon substrate,, reduced the touch opportunity of oxygen and nickel dam, greatly reduced the oxidized possibility of nickel dam, thereby help the raising of wafer property owing to adopted technique scheme.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that advantage of the present invention will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Figure 1A is the structural representation that deposition one deck the first metal layer is accomplished on silicon substrate;
Figure 1B is the structural representation that on the first metal layer, feeds gas;
Fig. 1 C is the structural representation that deposition one deck the first metal layer is accomplished on silicon substrate;
Fig. 2 is the structural representation that the present invention forms the method on nickel silicide barrier layer.
Embodiment
Below in conjunction with sketch map and concrete operations embodiment the present invention is described further.
Shown in Figure 1A; On silicon substrate 1, there is one deck first metal barrier 2; Before forming first metal barrier 2, need to remove the oxide on silicon substrate 1 surface, first metal barrier 2 covers on the silicon substrate 1; First metal barrier 2 is the silicide that a kind of nickel and pasc reaction generate, and first metal barrier 2 also can be the silicide that titanium and silicon react and generates.
Shown in Figure 1B, after the first metal layer 2 forms, feed a kind of gas to the first metal layer 2 immediately; This gas is a kind of gas that is difficult for nickel generation chemical reaction, and preferred a kind of gas is hydrogen among the present invention, and the pressure of control hydrogen is 0.01 to 1Mpa; Arrange the air that contacts with the first metal layer, make hydrogen can cover the first metal layer 2 surfaces fully, the feeding of hydrogen is a continuous uninterrupted; When on the first metal layer 2, depositing second metal level 3; The time that continues feeding hydrogen is 1 second to 5 minutes, and when feeding hydrogen, the control temperature is in 20 ℃ to 100 ℃ scopes.
Shown in Fig. 1 C, deposition second metal level 3 on the first metal layer on the first metal layer 2, it is a kind of titaniferous compounds that this second metal level 3 covers the first metal layer 2, the second metal levels 3 fully, titanium nitride preferably among the present invention.
For example; In process for fabrication of semiconductor device; Said method can be applied to form in the technical process of self-aligned silicide of active area (drain region or source region) of contact semiconductor device, mainly is that silicon active region and metal reaction in the semiconductor device structure is to form silicide regions.
As shown in Figure 2; In silicon substrate 1, be formed with the active area 6 and the polysilicon gate 5 (gate oxide layers between polysilicon gate 5 and the silicon substrate 1 is also not shown in the drawings) of MOS transistor; Deposit a metal level 2 at said active area 6 and polysilicon gate 5 upper surfaces, this metal level 2 is made up of nickel.Because be deposited on the active area 6 with polysilicon gate 5 on the activity of nickel very strong; Because nickel is easy to and oxygen reaction, there is the possibility of oxidation in the active area 6 that causes polysilicon gate 5 or silicon substrate 1 to form in the transfer process before the deposit titanium nitride, in case oxidation; Can form oxide layer on the nickel dam surface; Because after first time high-temperature annealing process, nickel can with the silicon formation silicide layer 4 that reacts, so aforementioned oxide layer can be present in the surface of silicide layer 4; Can cause increasing of nickel silicide resistance, be unfavorable for the raising of transistor performance.So the present invention is after deposit nickel; Deposit one deck titanium nitride is as the barrier layer on nickel again, and stoping the oxidation of nickel, detailed process is that temperature is that 20 ℃ to 100 ℃, pressure are to feed hydrogen 1 second to 5 minutes under 0.01 to 1MPa the situation; Suction H-H reaction through nickel; Surface at nickel forms one deck hydride layer, and then the deposit titanium nitride, forms better oxygen barrier.Need to prove that the preferred version that the above-mentioned concrete parameter of enumerating is just made based on the present invention, its concrete numerical value be not as restrictive condition of the present invention, in other words, based on the present invention's spirit, above-mentioned data can also be done adaptive adjustment.
More than specific embodiment of the present invention is described in detail, but the present invention is not restricted to the specific embodiment of above description, it is just as example.To those skilled in the art, any to this equivalent modifications of carrying out and alternative also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of having done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (7)
1. method that forms the nickel silicide barrier layer is characterized in that: mainly comprise following step:
Carry out clean in surface of silicon substrate, to remove the oxide of surface of silicon substrate;
Deposition one deck the first metal layer on said silicon substrate;
Said the first metal layer is carried out anti-oxidant treatment, on the first metal layer, deposit second metal level afterwards again, said first, second metal level constitutes the metal barrier of surface of silicon substrate jointly.
2. a kind of method that forms the nickel silicide barrier layer as claimed in claim 1, the first metal layer of said surface of silicon deposit is nickel or NiPt.
3. a kind of method that forms the nickel silicide barrier layer as claimed in claim 1, said anti-oxidant technology are to feed a kind of gas that prevents that nickel is oxidized to the first metal layer surface.
4. the method on any formation nickel silicide as claimed in claim 3 barrier layer, said gas is hydrogen.
5. a kind of method that forms the nickel silicide barrier layer as claimed in claim 1, second metal level of said deposit is a kind of titaniferous compound.
6. a kind of method that forms the nickel silicide barrier layer as claimed in claim 5, said second metal level is a titanium nitride.
7. like any one described a kind of method that forms the nickel silicide barrier layer of claims 1-6, the temperature of the antioxidation processing technology of this method is that 20 ℃ to 100 ℃, pressure are 0.01 to 1Mpa, and the time is 1 second to 5 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110235220.9A CN102437034B (en) | 2011-08-17 | 2011-08-17 | Method for forming nickel silicide blocking layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110235220.9A CN102437034B (en) | 2011-08-17 | 2011-08-17 | Method for forming nickel silicide blocking layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102437034A true CN102437034A (en) | 2012-05-02 |
| CN102437034B CN102437034B (en) | 2014-05-28 |
Family
ID=45985030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110235220.9A Active CN102437034B (en) | 2011-08-17 | 2011-08-17 | Method for forming nickel silicide blocking layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102437034B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108281431A (en) * | 2018-01-04 | 2018-07-13 | 深圳市华星光电技术有限公司 | A method of being used for the wet process of thin-film transistor array base-plate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1754860A (en) * | 2004-09-29 | 2006-04-05 | 中国科学院微电子研究所 | A kind of silicide process that is applicable to that nano-device is made |
| CN101197281A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Production method for silicide contact in semiconductor element |
| CN101496172A (en) * | 2005-05-24 | 2009-07-29 | 德克萨斯仪器股份有限公司 | Nickel silicide method and structure |
-
2011
- 2011-08-17 CN CN201110235220.9A patent/CN102437034B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1754860A (en) * | 2004-09-29 | 2006-04-05 | 中国科学院微电子研究所 | A kind of silicide process that is applicable to that nano-device is made |
| CN101496172A (en) * | 2005-05-24 | 2009-07-29 | 德克萨斯仪器股份有限公司 | Nickel silicide method and structure |
| CN101197281A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Production method for silicide contact in semiconductor element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108281431A (en) * | 2018-01-04 | 2018-07-13 | 深圳市华星光电技术有限公司 | A method of being used for the wet process of thin-film transistor array base-plate |
| CN108281431B (en) * | 2018-01-04 | 2021-01-05 | Tcl华星光电技术有限公司 | Method for wet process of thin film transistor array substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102437034B (en) | 2014-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103681269B (en) | The method of selectively formed high-K dielectric layer | |
| CN108573866A (en) | Oxidation film minimizing technology and device and contact site forming method and system | |
| TWI242811B (en) | Cleaning solution and method for selectively removing layers in a silicidation process | |
| CN106653758B (en) | Method for manufacturing flash memory | |
| CN100517618C (en) | Semiconductor device and its making method | |
| CN103632976B (en) | The forming method of transistor | |
| CN110310926A (en) | Solve the method that sram cell device metal silicide defect is formed | |
| CN1457086A (en) | Base electrode producing method | |
| CN102437034B (en) | Method for forming nickel silicide blocking layer | |
| CN102983104B (en) | The manufacture method of CMOS transistor | |
| CN103137559B (en) | The removing method of dummy poly and the manufacture method of CMOS metal gates | |
| US10672774B2 (en) | Bit line gate structure of dynamic random access memory (DRAM) and forming method thereof | |
| CN105990341B (en) | Semiconductor structure and forming method thereof | |
| US8722483B2 (en) | Method for manufacturing double-layer polysilicon gate | |
| CN105304568A (en) | Method for reducing high K metal gate device threshold voltage fluctuation | |
| CN103107074B (en) | A kind of formation method of metal gates | |
| US20050158940A1 (en) | Process of forming high-k gate dielectric layer for metal oxide semiconductor transistor | |
| CN110391285A (en) | Semiconductor structure and forming method thereof | |
| CN1938825A (en) | Semiconductor device and method for fabricating the same | |
| CN102456565A (en) | Method for preventing photoresistive failure in dual stress silicon nitride technology | |
| KR101019710B1 (en) | Method of manufacturing semiconductor device | |
| CN103579077B (en) | A kind of semiconductor structure and forming method thereof | |
| CN103165441A (en) | Manufacturing method of high-k grid electrode dielectric medium\metal stack-up grid electrode | |
| CN102237270B (en) | Metal gate structure and manufacture method thereof | |
| CN103426754B (en) | The formation method of transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |