CN103426754B - The formation method of transistor - Google Patents
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- CN103426754B CN103426754B CN201210149005.1A CN201210149005A CN103426754B CN 103426754 B CN103426754 B CN 103426754B CN 201210149005 A CN201210149005 A CN 201210149005A CN 103426754 B CN103426754 B CN 103426754B
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Abstract
A formation method for transistor, comprising: provide Semiconductor substrate; High-K dielectric layer is formed at described semiconductor substrate surface; Amorphous carbon layer is formed on described high-K dielectric layer surface; Dummy gate layer is formed on described amorphous carbon layer surface; Semiconductor substrate surface in dummy gate layer both sides forms side wall; Source/drain region is formed in the Semiconductor substrate of described dummy gate layer and side wall both sides; Form mask layer on a semiconductor substrate, described mask layer upper surface flushes with dummy gate layer top; Be mask with mask layer, remove described dummy gate layer, form opening; In described opening, fill full metal, form gate electrode layer, described gate electrode layer upper surface flushes with the top of described mask layer.The transistor performance formed is good.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of transistor.
Background technology
Along with the fast development of ic manufacturing technology, impel the semiconductor device in integrated circuit, especially MOS(MetalOxideSemiconductor, Metal-oxide-semicondutor) size of device constantly reduces, and meets the miniaturization of integrated circuit development and integrated requirement with this.In the process that the scales of MOS transistor device reduces, existing technique receives challenge using silica or silicon oxynitride as the technique of gate dielectric layer.There are some problems using silica or silicon oxynitride as the transistor that gate dielectric layer is formed, comprised the diffusion of leakage current increase and impurity, thus affect the threshold voltage of transistor, and then affect the performance of semiconductor device.
For overcoming the above problems, metal is adopted to be suggested as the transistor of grid.The described transistor with metal gates adopts high K(dielectric constant) material replaces conventional silica or silicon oxynitride gate dielectric material, and while can making shrinking transistor size, reduce the generation of leakage current, and improve the performance of transistor.
Prior art forms the method with the transistor of metal gates and please refer to Fig. 1 to Fig. 5, comprising:
Please refer to Fig. 1, Semiconductor substrate 10 is provided; Insulating barrier 11 is formed on described Semiconductor substrate 10 surface; High-K dielectric layer 12 is formed on described insulating barrier 11 surface; Form protective layer 13 on described high-K dielectric layer 12 surface, the material of described protective layer 13 is titanium nitride or tantalum nitride; Dummy gate layer 14 is formed on described protective layer 13 surface.
Please refer to Fig. 2, with described dummy gate layer 14 be protective layer described in mask etching 13, high-K dielectric layer 12 and insulating barrier 11, form protective layer 13a, high-K dielectric layer 12a and insulating barrier 11a.
Please refer to Fig. 3, Semiconductor substrate 10 surface in described dummy gate layer 14 both sides forms side wall 15.
Please refer to Fig. 4, at described dummy gate layer 14(as Fig. 3) and side wall 15 both sides Semiconductor substrate 10 in formed source/drain region 16; Behind formation source/drain region 16, form mask layer 18 on Semiconductor substrate 10 surface, described mask layer 18 upper surface flushes with dummy gate layer 14 top; With described mask layer 18 for mask, remove described dummy gate layer 14, form opening 17.
It should be noted that, behind formation source/drain region 16, carry out thermal annealing, activate described source/drain region 16.
Please refer to Fig. 5, at described opening 17(as Fig. 4) in fill full metal, form gate electrode layer 19, described gate electrode layer 19 upper surface flushes with the top of described mask layer 18.
But it is comparatively large that prior art forms the leakage current with the transistor of metal gates, and threshold voltage is comparatively large, and Bias Temperature is unstable, thus causes the performance of transistor not good.
The formation method with the transistor of metal gates please refer to the U.S. patent documents that publication number is US2009/0142899A1 more.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of transistor, reduces leakage current, reduces threshold voltage, Bias Temperature is stablized thus improves the performance of transistor.
For solving the problem, the invention provides a kind of formation method of transistor, comprising:
Semiconductor substrate is provided;
High-K dielectric layer is formed at described semiconductor substrate surface;
Amorphous carbon layer is formed on described high-K dielectric layer surface;
Dummy gate layer is formed on described amorphous carbon layer surface;
Semiconductor substrate surface in dummy gate layer both sides forms side wall;
Source/drain region is formed in the Semiconductor substrate of described dummy gate layer and side wall both sides;
Behind formation source/drain region, form mask layer at semiconductor substrate surface, described mask layer upper surface flushes with dummy gate layer top;
Be mask with mask layer, remove described dummy gate layer, form opening;
In described opening, fill full metal, form gate electrode layer, described gate electrode layer upper surface flushes with the top of described mask layer.
Alternatively, the thickness of described amorphous carbon layer is
Alternatively, the technique forming amorphous carbon layer is chemical vapor deposition method or atom layer deposition process.
Alternatively, before formation amorphous carbon layer, also step is comprised: form protective layer on described high-K dielectric layer surface.
Alternatively, the material of described protective layer is titanium nitride or tantalum nitride.
Alternatively, the thickness of described protective layer is
Alternatively, the thickness of described high-K dielectric layer is
Alternatively, the material of described high-K dielectric layer is hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconia, nitrogen zirconia, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide.
Alternatively, the material of described mask layer is silica or silicon nitride.
Alternatively, before formation high-K dielectric layer is formed, also comprise: form insulating barrier on the semiconductor substrate.
Alternatively, the material of described insulating barrier is silica or silicon nitride.
Compared with prior art, technical solution of the present invention has the following advantages:
In the formation process of transistor, amorphous carbon layer is formed in described high-K dielectric layer surface, because described amorphous carbon layer is fine and close, thus can in follow-up thermal annealing process, stop that oxygen that described high-K dielectric layer decomposes goes out is to the follow-up dummy gate layer diffusion being formed at amorphous carbon layer surface, and prevent from described oxygen and described dummy gate layer from reacting forming oxide layer; Therefore, the leakage current of the transistor formed reduces, Bias Temperature is stable, performance improves.
Further, before formation amorphous carbon layer, form protective layer on described high-K dielectric layer surface, then when described protective layer can stop formed transistor charge carrier diffusion, prevent leakage current from producing; And due to the thinner thickness of described protective layer, then the threshold voltage of formed transistor is less, the performance of transistor improves.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the cross-sectional view that prior art has the forming process of the transistor of metal gates;
Fig. 6 is the schematic flow sheet of the formation method of transistor described in the embodiment of the present invention;
Fig. 7 to Figure 10 is the cross-sectional view of the forming process of transistor described in the embodiment of the present invention.
Embodiment
As stated in the Background Art, the leakage current with the transistor of metal gates that prior art is formed is comparatively large, and threshold voltage is comparatively large, and Bias Temperature is unstable, thus causes the performance of transistor not good.
The present inventor finds through research, described in have the performance of the transistor of metal gates not good be due to: when thermal annealing activates source/drain region, described high-K dielectric layer can decomposes produce oxygen; Described oxygen can spread to dummy gate layer, and the formation oxide layer that reacts in the interface of dummy gate layer; The composition of described oxide layer is comparatively complicated and be difficult to determine, is therefore difficult to remove; And defect in described oxide layer is more, easily causes leakage current; In addition, decomposite in the high-K dielectric layer after oxygen and have more Lacking oxygen, also easily cause leakage current, cause bias temperature unstable; Prior art, in order to thinning described oxide layer, can make protective layer thicken; But when described protective layer is blocked up, the transistor threshold voltage formed can be too high; Therefore formed transistor performance is bad.
In order to improve the performance of formed transistor, the present inventor provides a kind of formation method of transistor, please refer to Fig. 6, is the schematic flow sheet of the formation method of transistor described in the embodiment of the present invention, comprises step:
Step S101, provides Semiconductor substrate; High-K dielectric layer is formed at described semiconductor substrate surface; Amorphous carbon layer is formed on described high-K dielectric layer surface; Dummy gate layer is formed on described amorphous carbon layer surface;
Step S102, the semiconductor substrate surface in described dummy gate layer both sides forms side wall;
Step S103, forms source/drain region in the Semiconductor substrate of described dummy gate layer and side wall both sides;
Step S104, behind formation source/drain region, form mask layer at semiconductor substrate surface, described mask layer upper surface flushes with dummy gate layer top;
Step S105 take mask layer as mask, removes described dummy gate layer, forms opening;
Step S106, in described opening, fill full metal, form gate electrode layer, described gate electrode layer upper surface flushes with the top of described mask layer.
The present inventor finds through research, after making described high-K dielectric layer surface form amorphous carbon layer, when thermal annealing activates source/drain region, the oxygen that described high-K dielectric layer decomposes produces is difficult to by described amorphous carbon layer, thus can not form oxide layer in the interface of dummy gate layer; The threshold voltage of the transistor formed reduces; Meanwhile, the Lacking oxygen in described high-K dielectric layer reduces, defect is less, and formed transistor drain current is reduced, and the transistor performance formed is excellent.
Below with reference to accompanying drawing, the specific embodiment of the invention is described in detail, please refer to the cross-sectional view of Fig. 7 to Figure 10 for the forming process of transistor described in the embodiment of the present invention.
Please refer to Fig. 7, Semiconductor substrate 100 is provided; High-K dielectric layer 101 is formed on described Semiconductor substrate 100 surface; Amorphous carbon layer 103 is formed on described high-K dielectric layer 101 surface; Dummy gate layer 104 is formed on described amorphous carbon layer 103 surface.
Described Semiconductor substrate 100 is for providing workbench for subsequent technique, and the material of described Semiconductor substrate 100 is the III-V such as silicon, SiGe, carborundum, silicon-on-insulator, silicon nitride or GaAs.
The formation method of described high-K dielectric layer 101, amorphous carbon layer 103 and dummy gate layer 104 is: formed the high-K dielectric layer, amorphous carbon layer and the dummy gate layer (not shown) that cover Semiconductor substrate 100 surface completely successively by chemical vapor deposition method or atom layer deposition process on Semiconductor substrate 100 surface; Photoresist layer (not shown) is formed on described dummy gate layer surface; Graphical described photoresist layer, exposes the dummy gate layer surface beyond gate electrode layer correspondence position; With the photoresist layer after graphical for mask, etch the described high-K dielectric layer, amorphous carbon layer and the dummy gate layer that cover Semiconductor substrate 100 surface completely, form high-K dielectric layer 101, amorphous carbon layer 103 and dummy gate layer 104.
Described high-K dielectric layer 101 has good thermal stability and mechanical strength, can reduce the leakage current of the transistor formed, thus improve the performance of transistor, reduce the size of transistor while the diffusion reducing charge carrier; The material of described high-K dielectric layer 101 is hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconia, nitrogen zirconia, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide; The thickness of described K dielectric layer 101 is
charge carrier can be made to be difficult to, through described high-K dielectric layer 102, prevent the diffusion of charge carrier.
The material of described dummy gate layer 103 is polysilicon; Described dummy gate layer 103 is for taking up space for the metal gate electrode layer of follow-up formation, and when therefore adopting polysilicon to be material, described in subsequent technique, dummy gate layer 103 is easy to be removed.
The thickness of described amorphous carbon layer 103 is
described amorphous carbon layer 103 can when subsequent technique thermal annealing activates source/drain region, and the oxygen preventing high-K dielectric layer 101 decomposes from going out diffuses to the interface of the dummy gate layer 104 of follow-up formation, thus prevents from forming oxide layer, improves the performance of transistor.
In the present embodiment, before formation amorphous carbon layer 103, form protective layer 102 on described high-K dielectric layer 101 surface; The material of described protective layer 102 is titanium nitride or tantalum nitride; The thickness of described protective layer 102 is
when described protective layer 102 can prevent the transistor of follow-up formation, carrier diffusion through high-K dielectric layer 101, thus decreases the generation of leakage current; Owing to forming amorphous carbon layer 103 after formation protective layer 102, and described amorphous carbon layer 103 can play the effect preventing oxide layer from being formed, then the thickness of described protective layer 102 is thin compared with prior art, and does not affect protected effect; In subsequent technique, remove described amorphous carbon layer 103 and form gate electrode layer on described protective layer 102 surface, then making formed transistor threshold voltage reduction, size reduces, performance improves.
In another embodiment, directly amorphous carbon layer 103 is formed on described high-K dielectric layer 101 surface; The thickness of described amorphous carbon layer 103 is
then described amorphous carbon layer 103 can prevent from forming oxide layer in the interface of dummy gate layer 104, makes the formation process of transistor simplify simultaneously, is more suitable for producing.
In the present embodiment, before formation high-K dielectric layer 101 is formed, described Semiconductor substrate 100 forms insulating barrier 110, and the material of described insulating barrier 110 is silica; Described insulating barrier 110 is for bonding high-K dielectric layer 101 and Semiconductor substrate 100; Due to surface and high-K dielectric layer 101 out-phase mutually of Semiconductor substrate 100, described high-K dielectric layer 101 is difficult to directly be formed at Semiconductor substrate 100 surface, therefore needs insulating barrier 110 to make high-K dielectric layer 101 and Semiconductor substrate 100 bonding.
Please refer to Fig. 8, Semiconductor substrate 100 surface in described dummy gate layer 104 both sides forms side wall 105; Source/drain region 106 is formed in the Semiconductor substrate 100 of described dummy gate layer 104 and side wall 105 both sides.
The formation process of described source/drain region 106 is: before forming side wall 105, with described dummy gate layer 104 for mask, in the Semiconductor substrate 100 of described dummy gate layer 104 both sides, carry out light dope ion implantation; After formation side wall 105, with described dummy gate layer 104 and side wall 105 for mask, in the Semiconductor substrate 100 of described side wall 105 both sides of next-door neighbour, carry out heavy doping ion injection.
Described side wall 105 is made up of the laminated construction of silica, silicon nitride or silica and silicon nitride; The formation process of described side wall 105 is: form side wall layer (not shown) at described high-K dielectric layer 101, amorphous carbon layer 103, dummy gate layer 104 and Semiconductor substrate 100 surface deposition; Return the described side wall layer of etching, Semiconductor substrate 100 surface in described dummy gate layer 104 both sides forms side wall 105.
Please continue to refer to Fig. 8, thermal annealing is carried out to described source/drain region 106, activates described source/drain region 106.
In the process of thermal annealing, described high-K dielectric layer 101 can decomposes produce oxygen, and produce Lacking oxygen, and described oxygen can spread in high temperature environments in described high-K dielectric layer 101 to dummy gate layer 104 simultaneously; In the prior art, described oxygen can diffuse to protective layer 13a(as Fig. 3) with dummy gate layer 14(as Fig. 3) interface that contacts, and the formation oxide layer that reacts in described interface, makes that the threshold voltage of transistor increases, leakage current increases; And the complicated component of described oxide layer and be difficult to determine, be therefore difficult to be removed; Therefore prior art in order to make oxide layer as far as possible thinning meeting the thickness of protective layer 13a is increased, and the thickness increase of protective layer 13a can increase threshold voltage further; In addition the defect in described oxide layer is more, and described high-K dielectric layer 12a(is as Fig. 3) in there is Lacking oxygen, make charge carrier be easy to diffusion, thus easily cause that leakage current, Bias Temperature are unstable, the hydraulic performance decline of transistor.
In the present embodiment, when in the process at thermal annealing, described high-K dielectric layer 101 decomposites oxygen, and described oxygen is after dummy gate layer 104 diffusion, described amorphous carbon layer 103 can stop oxygen to diffuse to the interface of dummy gate layer 104, thus prevents the formation of oxide layer; Meanwhile, the Lacking oxygen in high-K dielectric layer 101 reduces, then the defect in high-K dielectric layer 101 reduces; Therefore formed transistor drain current reduces, bias temperature is stable, threshold voltage reduces, and the performance of transistor improves.
It should be noted that, after thermal annealing, in described source/drain region 106, form self-alignment silicide layer (not shown), and described self-alignment silicide layer surface flushes with Semiconductor substrate 100 surface; The material of described self-alignment silicide layer is nisiloy or cobalt silicon; Described self-alignment silicide layer is used for the electrode as source/drain region 106; The formation method of described self-alignment silicide layer is: at described source/drain region 106 surface coverage metal level, and the material of described metal level is nickel or cobalt; Annealing process is adopted to form self-alignment silicide layer in described source/drain region 106; Remove unreacted metal level.
Please refer to Fig. 9, behind formation source/drain region 106, form mask layer 107 at semiconductor substrate surface, described mask layer 107 upper surface flushes with dummy gate layer 104 top; With mask layer 107 for mask, remove described dummy gate layer 104, form opening 108.
The material of described mask layer 107 is silica or silicon nitride; Described mask layer 107 is for as removing dummy gate layer 104(as Fig. 8) time mask, and for the protection of side wall 105 and Semiconductor substrate 100 surface in the process removing dummy gate layer 104 from damage; The technique of described removal dummy gate layer 104 is dry etching or wet etching.
In the present embodiment, after the described dummy gate layer 104 of removal, described amorphous carbon layer 103(is removed as Fig. 8); The technique removing described amorphous carbon layer 103 is cineration technics; The temperature of described cineration technics is 80 ~ 120 DEG C, and gas is oxygen; In described cineration technics, described amorphous carbon layer 103 generates carbon dioxide or CO (carbon monoxide converter) gas with oxygen reaction, thus described amorphous carbon layer 103 is removed; Remove the size that described amorphous carbon layer 103 can reduce formed transistor, and protective layer 102 still can prevent the generation of leakage current when transistor; The thickness of described protective layer 102 is thinning to some extent compared with prior art, thus reduces the threshold voltage of transistor, makes the size of formed transistor reduce further simultaneously, is conducive to the integrated of semiconductor device.
Please refer to Figure 10, at described opening 107(as Fig. 9) in fill full metal, form gate electrode layer 109, described gate electrode layer 109 upper surface flushes with the top of described mask layer 107.
The formation process of described gate electrode layer 109 is: in described opening 107, fill metal by depositing operation; The metal higher than described mask layer 107 top is removed by CMP (Chemical Mechanical Polishing) process; Described gate electrode layer 109 is made up of one or more superpositions in aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten.
In the formation method of transistor described in the present embodiment, amorphous carbon layer 103 is formed on described high-K dielectric layer 101 surface, then activate at thermal annealing in the process of source/drain region 106, the oxygen that described high-K dielectric layer 101 decomposes produces is difficult to by described amorphous carbon layer 103, therefore oxygen is prevented to form oxide layer in the interface of dummy gate layer 104, thus reduce threshold voltage, decrease leakage current; Meanwhile, the Lacking oxygen in described high-K dielectric layer 101 reduces, and therefore further reduces the generation of formed transistor drain current; In addition, because oxygen is difficult to by amorphous carbon layer 103, the thickness of described protective layer 102 can be suitably thinning thus, further reduces threshold voltage; Therefore, the transistor drain current formed with the formation method of transistor described in the present embodiment reduces, bias temperature is stable, threshold voltage reduces, performance improves.
In sum, in the formation process of transistor, amorphous carbon layer is formed in described high-K dielectric layer surface, because described amorphous carbon layer is fine and close, thus can be blocked in follow-up thermal annealing process, the oxygen that described high-K dielectric layer decomposes goes out spreads to the dummy gate layer of follow-up formation, and prevents from described oxygen and described dummy gate layer from reacting further forming oxide layer; Therefore, the leakage current of the transistor formed reduces, Bias Temperature is stable, performance improves.
Further, before formation amorphous carbon layer, form protective layer on described high-K dielectric layer surface, then when described protective layer can stop formed transistor charge carrier diffusion, prevent leakage current from producing; And due to the thinner thickness of described protective layer, then the threshold voltage of formed transistor is less, the performance of transistor improves.
Although the embodiment of the present invention is described above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
High-K dielectric layer is formed at described semiconductor substrate surface;
Protective layer is formed on described high-K dielectric layer surface;
Amorphous carbon layer is formed at described protective layer;
Dummy gate layer is formed on described amorphous carbon layer surface;
Semiconductor substrate surface in dummy gate layer both sides forms side wall;
Source/drain region is formed in the Semiconductor substrate of described dummy gate layer and side wall both sides;
Behind formation source/drain region, form mask layer at semiconductor substrate surface, described mask layer upper surface flushes with dummy gate layer top;
Be mask with mask layer, remove described dummy gate layer, form opening;
In described opening, fill full metal, form gate electrode layer, described gate electrode layer upper surface flushes with the top of described mask layer.
2. the formation method of transistor as claimed in claim 1, it is characterized in that, the thickness of described amorphous carbon layer is
3. the formation method of transistor as claimed in claim 1, is characterized in that, the technique forming amorphous carbon layer is chemical vapor deposition method or atom layer deposition process.
4. the formation method of transistor as claimed in claim 1, it is characterized in that, the material of described protective layer is titanium nitride or tantalum nitride.
5. the formation method of transistor as claimed in claim 1, it is characterized in that, the thickness of described protective layer is
6. the formation method of transistor as claimed in claim 1, it is characterized in that, the thickness of described high-K dielectric layer is
7. the formation method of transistor as claimed in claim 1, it is characterized in that, the material of described high-K dielectric layer is hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconia, nitrogen zirconia, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide.
8. the formation method of transistor as claimed in claim 1, it is characterized in that, the material of described mask layer is silica or silicon nitride.
9. the formation method of transistor as claimed in claim 1, is characterized in that, before formation high-K dielectric layer is formed, also comprises: form insulating barrier on the semiconductor substrate.
10. the formation method of transistor as claimed in claim 9, it is characterized in that, the material of described insulating barrier is silica or silicon nitride.
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| DE102010001404B4 (en) * | 2010-01-29 | 2015-03-19 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Adjustment of transistor properties based on a late well implant |
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