CN111211055A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN111211055A
CN111211055A CN201811391839.7A CN201811391839A CN111211055A CN 111211055 A CN111211055 A CN 111211055A CN 201811391839 A CN201811391839 A CN 201811391839A CN 111211055 A CN111211055 A CN 111211055A
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layer
forming
region
dielectric layer
gate opening
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CN111211055B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a first area, a dielectric layer is arranged on the surface of the substrate in the first area, a pseudo gate opening is arranged in the dielectric layer in the first area, source and drain doped areas are arranged in the substrate on two sides of the pseudo gate opening, and the dielectric layer covers the surfaces of the source and drain doped areas; removing part of the dielectric layer until the top of the source drain doped region is exposed, and forming a contact hole in the dielectric layer; forming a metal silicide layer on the surface of the source drain doping region at the bottom of the contact hole; and after the metal silicide layer is formed, forming a first work function layer at the bottom of the dummy gate opening of the first region. The semiconductor device formed by the method has better performance.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Complementary Metal Oxide Semiconductor (CMOS) transistors, which are the most basic devices in semiconductor fabrication, are widely used in a variety of integrated circuits. The cmos is classified into NMOS transistors and PMOS transistors according to the main carriers and doping types during manufacturing. Taking the NMOS transistor as an example, the NMOS transistor includes: and source and drain doped regions.
In the conventional complementary metal oxide semiconductor process, in order to improve the contact resistance between a source-drain doped region and a plug on the source-drain doped region, a metal silicide layer is usually formed on the top surface of the source-drain doped region.
However, the performance of transistors formed by the prior art is still poor.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area, a dielectric layer is arranged on the surface of the substrate in the first area, a pseudo gate opening is arranged in the dielectric layer in the first area, source and drain doped areas are arranged in the substrate on two sides of the pseudo gate opening, and the dielectric layer covers the surfaces of the source and drain doped areas; removing part of the dielectric layer until the top surface of the source-drain doped region is exposed, and forming a contact hole in the dielectric layer; forming a metal silicide layer in the contact hole; and after the metal silicide layer is formed, forming a first work function layer at the bottom of the dummy gate opening of the first region.
Optionally, the forming method of the metal silicide layer includes: forming a metal layer on the surface of the source drain doping region at the bottom of the contact hole; and carrying out first annealing treatment to enable the metal layer to react with the top of the source drain doped region to form a metal silicide layer.
Optionally, the material of the metal layer includes nickel or titanium.
Optionally, the first annealing process includes: performing laser annealing process; the parameters of the laser annealing process comprise: 850-1000 ℃.
Optionally, when the first region is used to form an NMOS transistor, the material of the first work function layer includes titanium aluminum.
Optionally, before forming the contact hole, the forming method includes: forming a gate dielectric layer and a first sacrificial layer positioned on the surface of the gate dielectric layer at the bottom of the pseudo gate opening of the first area; forming a second sacrificial layer on the surface of the first sacrificial layer; the material of the first sacrificial layer comprises amorphous silicon; the material of the second sacrificial layer comprises amorphous silicon.
Optionally, after the forming of the gate dielectric layer and before the forming of the first sacrificial layer, the method further includes: carrying out a second annealing process; the second annealing process comprises a spike annealing process; the parameters of the spike annealing process include: 800 ℃ to 950 ℃.
Optionally, after forming the first sacrificial layer and before forming the second sacrificial layer, the forming method further includes: carrying out a third annealing process; the third annealing process comprises a spike annealing process; the parameters of the spike annealing process include: 850-1000 ℃.
Optionally, the substrate further includes a second region, the dielectric layer is further located on the surface of the substrate in the second region, the dummy gate opening is further located in the dielectric layer in the second region, and the dummy source-drain doped region is further located in the substrate on both sides of the dummy gate opening in the second region; the gate dielectric layer is also positioned at the bottom of the pseudo gate opening of the second area; after the gate dielectric layer is formed and before the first sacrificial layer is formed, the forming method further comprises: and forming a second work function film at the bottom of the first region and the second region pseudo gate opening.
Optionally, the second region is used for forming a PMOS transistor; the material of the second work function film includes titanium nitride.
Optionally, after forming the metal silicide layer and before forming the first work function layer, the forming method includes: forming a plug in the contact hole, wherein the plug is filled with a dummy gate opening; after the plug is formed, removing the second sacrificial layer and the first sacrificial layer; and after removing the second sacrificial layer and the first sacrificial layer, removing the second work function film of the first region, and forming a second work function layer at the bottom of the dummy gate opening of the second region.
Optionally, after the first work function layer is formed, the forming method includes: and forming a gate layer in the dummy gate opening, wherein the gate layer is filled in the dummy gate opening.
Accordingly, the present invention also provides a semiconductor structure comprising: the substrate comprises a first area, a dielectric layer is arranged on the surface of the substrate in the first area, a pseudo gate opening is arranged in the dielectric layer in the first area, source and drain doped areas are arranged in the substrate on two sides of the pseudo gate opening, and the dielectric layer covers the surfaces of the source and drain doped areas; the contact hole is positioned in the medium layer, and the bottom of the contact hole is exposed out of the top surface of the source drain doped region; the metal silicide layer is positioned on the top of the source drain doped region at the bottom of the contact hole; and the first work function layer is positioned on the bottom surface of the pseudo gate opening.
Optionally, the first region is used to form an NMOS transistor, and the material of the first work function layer includes titanium aluminum.
Optionally, the substrate further includes a second region, the dielectric layer is further located on the surface of the substrate in the second region, the dummy gate opening is further located in the dielectric layer in the second region, and the source-drain doped region is further located in the substrate on both sides of the dummy gate opening in the second region.
Optionally, the method further includes: the gate dielectric layers are positioned at the bottoms of the first area pseudo gate opening and the second area pseudo gate opening; the second work function layer is positioned on the surface of the second area gate dielectric layer; the second region is used for forming a PMOS transistor, and the material of the second work function layer comprises titanium nitride.
Optionally, the semiconductor structure further includes: the plug is positioned on the surface of the metal silicide layer in the contact hole and is filled in the contact hole; and the gate layer is positioned on the surface of the first work function layer at the bottom of the dummy gate opening and is filled in the dummy gate opening.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the first work function layer is formed after the metal silicide layer is formed, so that ions in the first work function layer are not influenced by high temperature in a high-temperature process of the metal silicide layer, and therefore, the ions in the first work function layer can be prevented from being diffused, and the performance of a semiconductor device can be improved.
Further, after the gate dielectric layer is formed and before the first sacrificial layer is formed, a second annealing process is performed. And the first sacrificial layer is formed before the contact hole is formed, so that the second annealing process is performed before the first work function layer is formed, ions in the first work function layer are less influenced by the second annealing process, and the diffusion of the ions in the first work function layer is further reduced.
Further, after the first sacrificial layer is formed and before the second work function layer is formed, a third annealing process is performed. Because the second work function layer is formed before the contact hole is formed, the third annealing process is performed before the first work function layer is formed, so that ions in the first work function layer are less influenced by the third annealing process, and the diffusion of the ions in the first work function layer is further reduced.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method of forming a semiconductor structure;
fig. 4 to 16 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of semiconductor devices is poor.
Fig. 1 to 3 are schematic structural diagrams of a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes an NMOS region, a dummy gate structure (not shown in the figure) is provided on a surface of the substrate 100 in the NMOS region, a source-drain doped region 101 is provided in the substrate 100 at two sides of the dummy gate structure, a dielectric layer 102 is provided on the surfaces of the substrate 100 and the source-drain doped region 101, and on a sidewall of the dummy gate structure, and the dielectric layer 102 exposes a top surface of the dummy gate structure; and removing the pseudo gate structure, and forming a pseudo gate opening 103 in the dielectric layer 102.
Referring to fig. 2, a gate dielectric layer 104 is formed on the bottom surface of the dummy gate opening 103 (see fig. 1); a first work function layer 105 and a gate layer 106 located on the surface of the first work function layer 105 are formed on the surface of the gate dielectric layer 104, and the gate layer 106 is filled in the dummy gate opening 103.
Referring to fig. 3, after the gate layer 103 is formed, removing a portion of the dielectric layer 102 until the top surface of the source-drain doped region 101 is exposed, and forming a contact hole 106 in the dielectric layer 102; and forming a metal silicide layer 107 on the surface of the source drain doped region 101 at the bottom of the contact hole 106.
In the above method, the NMOS area is used to form an NMOS transistor, the material of the first work function layer 105 includes titanium aluminum, and the first work function layer 105 is used to adjust a threshold voltage of the NMOS transistor. The method for forming the metal silicide layer 107 comprises the following steps: forming a metal layer on the side wall and the bottom surface of the contact hole 106; and annealing treatment is carried out, so that the metal layer reacts with the top of the source drain doped region 101 to form a metal silicide layer 107.
However, the annealing treatment easily drives aluminum ions to diffuse into the gate dielectric layer 104, so that the dielectric constant of the gate dielectric layer 104 is reduced, the gate dielectric layer 104 is easily broken down, and the performance of the semiconductor device is not improved.
Also, the substrate 100 may include other devices, such as: if aluminum ions diffuse into the PMOS transistor, the PMOS transistor will affect its threshold voltage, which is not good for improving its performance.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: and after the metal silicide layer is formed, forming a first work function layer on the bottom surface in the first region dummy gate opening. The method can reduce the diffusion of ions in the first work function layer and improve the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 16 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided, where the substrate 200 includes a first region a, a dummy gate structure 203 is provided on a surface of the substrate 200 of the first region a, a source-drain doped region 206 is provided in the substrate 200 at two sides of the dummy gate structure 203, dielectric layers 208 are provided on surfaces of the substrate 200 and the source-drain doped region 206, and a sidewall of the dummy gate structure 203, and the dielectric layers 208 expose a top surface of the dummy gate structure 203.
In this embodiment, the substrate 200 includes: a substrate 201 and a fin 202 on the substrate 201.
In other embodiments, when the semiconductor device is a planar MOS transistor, the substrate is a planar semiconductor substrate.
In this embodiment, the forming step of the substrate 200 includes: providing an initial substrate, wherein a first mask layer is arranged on the initial substrate, and the first mask layer exposes a part of the top surface of the initial substrate; and etching the initial substrate by taking the first mask layer as a mask to form a substrate 201 and a fin part 202 positioned on the substrate 201.
In other embodiments, the method of forming the substrate includes: providing a substrate; and epitaxially forming the fin part on the surface of the substrate.
In this embodiment, the material of the initial substrate is silicon. Accordingly, the material of the substrate 201 and the fin 202 is silicon. In other embodiments, the material of the initial substrate comprises: germanium, silicon on insulator or germanium on insulator. Accordingly, the material of the substrate comprises: germanium, silicon on insulator or germanium on insulator. The material of the fin portion includes: germanium, silicon on insulator or germanium on insulator.
The material of the first mask layer comprises silicon nitride, and the forming process of the first mask layer comprises the following steps: chemical vapor deposition process. The first mask layer is used to form a mask for the substrate 201 and the fin 202.
The process for etching the initial substrate by taking the first mask layer as a mask comprises the following steps: one or both of a dry etching process and a wet etching process.
The substrate 200 further has an isolation structure (not shown) covering a portion of the fin 202, and a top surface of the isolation structure is lower than a top surface of the fin 202 and covers a portion of sidewalls of the fin 202.
The material of the isolation structure comprises: silicon oxide. In other embodiments, the material of the isolation structure may also be silicon oxynitride or silicon nitride.
The isolation structure is used for realizing electric insulation between different devices of the semiconductor.
The first region a is used to form an NMOS transistor.
In this embodiment, the substrate 200 further includes a second region B, the second region B is used for forming a PMOS transistor, the dielectric layer 208 is further located on the surface of the substrate 200 of the second region B, the dummy gate structure 203 is further located in the second region B, and the source-drain doped region 206 is further located in the substrate 200 on both sides of the dummy gate structure 203 of the second region B.
In other embodiments, the substrate includes only the first region. The dummy gate structure 203 crosses over the fin 202, and the dummy gate structure 203 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) on a surface of the dummy gate dielectric layer.
The material of the dummy gate dielectric layer comprises silicon oxide, and the material of the dummy gate layer comprises silicon.
The sidewall of the dummy gate structure 203 has a first sidewall 204, and the first sidewall 204 is used to define the position of the lightly doped region. The material of the first side walls 204 includes silicon nitride.
The sidewall of the first sidewall 204 has a second sidewall 205, and the second sidewall 205 is used for the position of the source-drain doped region 206.
The method for forming the source/drain doped region 206 includes: forming source and drain openings in the fin portion 202 on two sides of the dummy gate structure 203, the first side wall 204 and the second side wall 205; forming an epitaxial layer in the source drain opening; doping ions into the epitaxial layer to form a source/drain doped region 206.
The material of the epitaxial layer and the conductivity type of the dopant ions are related to the type of transistor.
In this embodiment, the first region a is used to form an NMOS transistor, the material of the epitaxial layer includes silicon carbide or silicon, and the dopant ions are N-type ions. The second region B is used for forming a PMOS transistor, the epitaxial layer is made of silicon germanium or silicon, and the doped ions are P-type ions.
After the source-drain doped region 206 is formed and before the dielectric layer 208 is formed, the forming method further includes: a stop layer 207 is formed on top of the source drain doped region 206.
The material of the stop layer 207 includes silicon nitride, and the stop layer 207 is used as a stop layer for forming a contact hole in the dielectric layer 208 on the top of the source-drain doped region 206 in a subsequent step, so as to protect the top surface of the source-drain doped region 206.
In this embodiment, the stop layer 207 also covers the surface of the isolation structure and the sidewall of the second sidewall 205.
In other embodiments, the stop layer covers only the top surface of the source drain doped region.
The forming method of the dielectric layer 208 comprises the following steps: forming a dielectric film on the top surfaces of the stop layer 207 and the pseudo gate structure 203; and flattening the dielectric film until the top surface of the dummy gate layer is exposed to form a dielectric layer 208.
The material of the dielectric film comprises silicon oxide or silicon oxynitride. Correspondingly, the material of the dielectric layer 208 includes silicon oxide or silicon oxynitride. The forming process of the dielectric film comprises a physical vapor deposition process or a chemical vapor deposition process.
The process for flattening the dielectric film comprises the following steps: and (5) carrying out a chemical mechanical polishing process.
Referring to fig. 5, the dummy gate structure 203 (see fig. 4) is removed, and a dummy gate opening 209 is formed in the dielectric layer 208.
The method for removing the dummy gate structure 203 comprises the following steps: removing the dummy gate layer; and removing the dummy gate dielectric layer after removing the dummy gate layer.
The process for removing the dummy gate layer comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The process for removing the pseudo gate dielectric layer comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
The first region a dummy gate opening 209 is used for subsequently accommodating a gate dielectric layer, a first work function layer located on the gate dielectric layer, and a gate layer located on the surface of the first work function layer; the second region B dummy gate opening 209 is used for subsequently accommodating a gate dielectric layer, a second work function layer located on the surface of the gate dielectric layer, and a gate layer located on the surface of the second work function layer.
Referring to fig. 6, an interface layer (not shown) is formed on the surface of the fin 202 at the bottom of the dummy gate opening 209; and forming a gate dielectric layer 210 on the surface of the interface layer.
The material of the interfacial layer comprises silicon oxide. The forming process of the interface layer comprises a chemical oxidation process, and the parameters of the chemical oxidation process comprise: the oxidant comprises hydrogen peroxide.
The interfacial layer is used to improve the interface state between the gate dielectric layer 210 and the fin portion 202.
The gate dielectric layer 210 is made of a high dielectric constant (K is greater than 3.9). In this embodiment, the gate dielectric layer 210 is made of hafnium oxide. In other embodiments, the material of the gate dielectric layer includes: la2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4。
After the gate dielectric layer 210 is formed, a second annealing process is performed. The second annealing process comprises a spike annealing process, and parameters of the spike annealing process comprise: 800 ℃ to 950 ℃.
The interface layer formed by the chemical oxidation process has more defects, and the second annealing treatment is used for repairing the defects in the interface layer, so that the interface states between the interface layer and the gate dielectric layer 210 and between the interface layer and the fin portion 202 are good, and the performance of the semiconductor device is improved.
Referring to fig. 7, a second work function film 211 is formed on the surface of the gate dielectric layer 210.
The second work function film 211 is used to subsequently form a second work function layer on the surface of the gate dielectric layer 210 at the bottom of the dummy gate opening 209 in the second region B. The second work function layer is used for adjusting the threshold voltage of the PMOS transistor.
The material of the second work function film 211 includes titanium nitride.
Referring to fig. 8, a first sacrificial layer 212 is formed on the surface of the second work function film 211.
The material of the first sacrificial layer 212 comprises amorphous silicon, and the forming process of the first sacrificial layer 212 comprises the following steps: a chemical vapor deposition process or a physical vapor deposition process.
After the first sacrificial layer 212 is formed, the method further includes: carrying out third annealing treatment, wherein the third annealing treatment process comprises the following steps: spike annealing process, the parameters of the spike annealing process comprising: 850-1000 ℃.
The third annealing process is beneficial to the first sacrificial layer 212 to absorb oxygen in the gate dielectric layer 210, and is beneficial to ensuring the dielectric constant of the gate dielectric layer 210, so that the gate dielectric layer 210 is prevented from being broken down, and the performance of the semiconductor device is improved.
The thickness of the first sacrificial layer 212 is 35 to 110 angstroms.
The thickness of the first sacrificial layer 212 is chosen in the sense that: if the thickness of the first sacrificial layer 212 is too thin, the capability of the first sacrificial layer 212 to balance the oxygen content in the gate dielectric layer 210 is weak, so that the dielectric constant of the gate dielectric layer 210 is difficult to ensure, and therefore, the performance of the semiconductor device is not favorable; if the thickness of the first sacrificial layer 212 is too thick, the amorphous silicon material is not easy to be removed by the subsequent process because the amorphous silicon material is easy to undergo atomic agglomeration during the third annealing process.
Referring to fig. 9, a second sacrificial layer 213 is formed on the surface of the first sacrificial layer 212, and the second sacrificial layer 213 fills the dummy gate opening 209 (see fig. 8).
The method for forming the second sacrificial layer 213 includes: forming a second sacrificial film on the surface of the first sacrificial layer 212; and flattening the second sacrificial film until the top surface of the dielectric layer 208 is exposed, and forming a second sacrificial layer 213 in the dummy gate opening 209.
The material of the second sacrificial film includes amorphous silicon, and correspondingly, the material of the second sacrificial layer 213 includes amorphous silicon. The second sacrificial film forming process includes a chemical vapor deposition process or a physical vapor deposition process.
The process of planarizing the second sacrificial film includes: and (5) carrying out a chemical mechanical polishing process.
In the process of planarizing the second sacrificial film, the first sacrificial layer 212, the second work function film 211, and the gate dielectric layer 210 on the surface of the dielectric layer 208 are also removed.
Referring to fig. 10, after the second sacrificial layer 213 is formed, a portion of the dielectric layer 208 is removed until the top surface of the source/drain doped region 206 is exposed, and a contact hole 214 is formed in the dielectric layer 208.
The forming method of the contact hole 214 comprises the following steps: forming a second mask layer (not shown in the figure) on the surfaces of the dielectric layer 208 and the second sacrificial layer 213, wherein the second mask layer exposes a part of the dielectric layer 208 on the top of the source-drain doped region 206; and etching the dielectric layer 208 and the stop layer 207 by taking the second mask layer as a mask until the top surfaces of the source-drain doped regions are exposed, and forming a contact hole 214 in the dielectric layer 208 and the stop layer 207.
The material of the second mask layer includes silicon nitride or titanium nitride, and the second mask layer is used for defining the size and the position of the contact hole 214.
The contact holes 214 are used for subsequently receiving a metal silicide layer and a plug located on the surface of the metal silicide layer.
Referring to fig. 11, a metal silicide layer 215 is formed on the top of the source/drain doped region 206 at the bottom of the contact hole 214.
The method for forming the metal silicide layer 215 includes: forming a metal layer (not shown in the figure) on the surface of the source-drain doped region 206 at the bottom of the contact hole 214; a first annealing process is performed to react the metal layer with the top of the source/drain doped region 206 to form a metal silicide layer 215.
The material of the metal layer includes nickel or titanium, and correspondingly, the material of the metal silicide layer 215 includes: a nickel silicon compound or a titanium silicon compound. The metal silicide layer 215 is used to reduce the contact resistance between the subsequent plug and the source/drain doped region 206.
The forming process of the metal layer comprises the following steps: a chemical vapor deposition process or a physical vapor deposition process.
The first annealing process includes: the laser annealing process comprises the following parameters: 850-1000 ℃.
When the first annealing process is performed, the first work function layer is not formed on the surface of the dummy gate dielectric layer 210 at the bottom of the dummy gate opening 209 in the first region a, and therefore, the subsequent first work function layer is not affected by the first annealing process, so that ions in the first work function layer are not easily affected by the first annealing process, and the ions in the first work function layer are not easily diffused into the gate dielectric layer 210, which is beneficial to ensuring the dielectric constant of the gate dielectric layer 210 and preventing the gate dielectric layer 210 from being broken down. Moreover, ions in the first work function layer are not easy to diffuse into the second region B, so that the threshold voltage of the second region B device is not influenced by the ions in the first work function layer, and the performance of the second region B device is improved.
Referring to fig. 12, after the metal silicide layer 215 is formed, a plug 216 is formed in the contact hole 214 (see fig. 11), and the plug 216 fills the contact hole 214.
The method for forming the plug 216 includes: forming plug films on the surface of the dielectric layer 208 and in the contact hole 214; a portion of the plug film is removed to form the plug 216 within the contact hole 214.
The plug membrane is made of metal. The plug film is used to form the plug 216, and thus, the material of the plug 216 is metal.
In this embodiment, the plug film is made of tungsten, and correspondingly, the plug 216 is made of tungsten. In other embodiments, the material of the plug membrane comprises aluminum or copper, and correspondingly, the material of the plug comprises aluminum or copper.
The plug film forming process comprises the following steps: a chemical vapor deposition process or a physical vapor deposition process.
The process of removing a portion of the plug film includes a chemical mechanical polishing process.
Referring to fig. 13, after the plug 216 is formed, the second sacrificial layer 213 and the first sacrificial layer 212 are removed.
The process of removing the second sacrificial layer 213 and the first sacrificial layer 212 includes one or a combination of a dry etching process and a wet etching process.
The second sacrificial layer 213 and the first sacrificial layer 212 are removed to facilitate the subsequent formation of the second work function layer and the gate layer.
Referring to fig. 14, after removing the second sacrificial layer 213 and the first sacrificial layer 212, a third sacrificial layer 250 is formed in the second region B dummy gate opening 209; after the third sacrificial layer 250 is formed, the second work function film 211 on the sidewall and the bottom of the dummy gate opening 209 in the first region a is removed, and a second work function layer 251 is formed on the sidewall and the bottom of the dummy gate opening 209 in the second region B.
The material of the third sacrificial layer 250 includes a bottom anti-reflective material. The third sacrificial layer 250 is used to prevent the second work function film 211 in the second region B from being removed, which is beneficial to forming a second work function layer 251 on the surface of the gate dielectric layer 210 at the bottom of the dummy gate opening 209 in the second region B.
The process for removing the second work function film 211 on the sidewall and the bottom of the dummy gate opening 209 in the first region a includes: one or two of the dry etching process and the wet etching process are combined.
The second work function layer 251 is used to improve the threshold voltage of the second region B device.
Referring to fig. 15, a first work function layer 217 is formed on the surfaces of the second work function layer 251 and the gate dielectric layer 210.
After forming the second work function layer 251 and before forming the first work function layer 217, the forming method further includes: the third sacrificial layer 250 is removed.
The process of removing the third sacrificial layer 250 includes: and (5) ashing.
The material of the first work function layer 217 includes titanium aluminum. The first work function layer 217 is used to improve the threshold voltage of first region a devices used to form NMOS transistors.
Referring to fig. 16, a gate layer 218 is formed on the surface of the first work function layer 217, and the gate layer 218 fills the dummy gate opening 209 (see fig. 15).
The forming method of the gate layer 218 includes: forming a gate material film on the surfaces of the dielectric layer 208 and the first work function layer 217, wherein the gate material film is filled in the dummy gate opening 209; portions of the gate material film are removed until the top surface of the dielectric layer 208 is exposed, and a gate layer 218 is formed in the dummy gate opening 209.
The gate material film is made of metal, and correspondingly, the gate layer 218 is made of metal. In the present embodiment, the material of the gate material film is aluminum, and correspondingly, the material of the gate layer 218 is aluminum. In other embodiments, the material of the gate material film includes: al, Cu, Ag, Au, Ni, Ti, W, WN or WSi, and correspondingly, the material of the gate layer comprises: al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
Accordingly, the present invention further provides a semiconductor structure, please refer to fig. 15, which includes:
the substrate 200 comprises a first area A, the surface of the substrate 200 of the first area A is provided with a dielectric layer 208, a pseudo gate opening 209 is arranged in the dielectric layer 208 of the first area A, a source-drain doped region 206 is arranged in the substrate 200 at two sides of the pseudo gate opening 209, and the dielectric layer 208 covers the surface of the source-drain doped region 206;
a contact hole 214 (see fig. 11) in the dielectric layer 208, wherein the bottom of the contact hole 214 exposes the top surface of the source/drain doped region 206;
a metal silicide layer 215 positioned at the bottom of the contact hole 214 and on the top of the source/drain doped region 206;
a first work function layer 217 on a bottom surface of the dummy gate opening 209.
The first region a is used for forming an NMOS transistor, and the material of the first work function layer 217 includes titanium aluminum.
The substrate 200 further includes a second region B, the dielectric layer 208 is further located on the surface of the substrate 200 in the second region B, the dummy gate opening 209 is further located in the dielectric layer 208 in the second region B, and the source-drain doped region 206 is further located in the substrate 200 on both sides of the dummy gate opening 209 in the second region B.
Further comprising: a gate dielectric layer 210 positioned at the bottom of the first region a dummy gate opening 209 and the second region B dummy gate opening 209; a second work function layer 251 is arranged between the second region B gate dielectric layer 210 and the first work function layer 217; the second region B is used for forming a PMOS transistor, and the material of the second work function layer 211 includes titanium nitride.
The semiconductor structure further includes: a plug 216 located on the surface of the metal silicide layer 215 at the bottom of the contact hole 214; and a gate layer 218 located on the surface of the first work function layer 217 at the bottom of the dummy gate opening 209.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (17)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area, a dielectric layer is arranged on the surface of the substrate in the first area, a pseudo gate opening is arranged in the dielectric layer, source and drain doped areas are arranged in the substrate on two sides of the pseudo gate opening, and the dielectric layer covers the surfaces of the source and drain doped areas;
removing part of the dielectric layer until the top surface of the source drain doped region is exposed, and forming a contact hole in the dielectric layer;
forming a metal silicide layer on the surface of the source drain doping region at the bottom of the contact hole;
and after the metal silicide layer is formed, forming a first work function layer at the bottom of the dummy gate opening of the first region.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming the metal silicide layer comprises: forming a metal layer on the surface of the source drain doping region at the bottom of the contact hole; and carrying out first annealing treatment to enable the metal layer to react with the top of the source drain doped region to form a metal silicide layer.
3. The method of forming a semiconductor structure of claim 2, wherein a material of the metal layer comprises nickel or titanium.
4. The method of forming a semiconductor structure of claim 2, wherein the first annealing process comprises: performing laser annealing process; the parameters of the laser annealing process comprise: 850-1000 ℃.
5. The method of claim 1, wherein a material of the first work function layer comprises titanium aluminum when the first region is used to form an NMOS transistor.
6. The method of forming a semiconductor structure of claim 1, wherein prior to forming the contact hole, the method of forming comprises: forming a gate dielectric layer and a first sacrificial layer positioned on the surface of the gate dielectric layer at the bottom of the pseudo gate opening of the first area; forming a second sacrificial layer on the surface of the first sacrificial layer; the material of the first sacrificial layer comprises amorphous silicon; the material of the second sacrificial layer comprises amorphous silicon.
7. The method of forming a semiconductor structure of claim 6, wherein after forming the gate dielectric layer and before forming the first sacrificial layer, further comprising: carrying out a second annealing process; the second annealing process comprises a spike annealing process; the parameters of the spike annealing process include: 800 ℃ to 950 ℃.
8. The method of forming a semiconductor structure of claim 6, wherein after forming the first sacrificial layer and before forming the second sacrificial layer, the method further comprises: carrying out a third annealing process; the third annealing process comprises a spike annealing process; the parameters of the spike annealing process include: 850-1000 ℃.
9. The method for forming a semiconductor structure according to claim 6, wherein the substrate further comprises a second region, the dielectric layer is further located on the surface of the substrate in the second region, the dummy gate opening is further located in the dielectric layer in the second region, and the source-drain doped region is further located in the substrate on both sides of the dummy gate opening in the second region; the gate dielectric layer is also positioned at the bottom of the pseudo gate opening of the second area; after the gate dielectric layer is formed and before the first sacrificial layer is formed, the forming method further comprises: and forming a second work function film at the bottom of the first region and the second region pseudo gate opening.
10. The method of forming a semiconductor structure of claim 9, wherein the second region is used to form a PMOS transistor; the material of the second work function film includes titanium nitride.
11. The method of forming a semiconductor structure of claim 9, wherein after forming the metal silicide layer and before forming the first work function layer, the method comprises: forming a plug in the contact hole, wherein the plug is filled with a dummy gate opening; after the plug is formed, removing the second sacrificial layer and the first sacrificial layer; and after removing the second sacrificial layer and the first sacrificial layer, removing the second work function film of the first region, and forming a second work function layer at the bottom of the dummy gate opening of the second region.
12. The method of forming a semiconductor structure of claim 1, wherein after forming the first work function layer, the method of forming comprises: and forming a gate layer in the dummy gate opening, wherein the gate layer is filled in the dummy gate opening.
13. A semiconductor structure, comprising:
the substrate comprises a first area, a dielectric layer is arranged on the surface of the substrate in the first area, a pseudo gate opening is arranged in the dielectric layer in the first area, source and drain doped areas are arranged in the substrate on two sides of the pseudo gate opening, and the dielectric layer covers the surfaces of the source and drain doped areas;
the contact hole is positioned in the medium layer, and the bottom of the contact hole is exposed out of the top surface of the source drain doped region;
the metal silicide layer is positioned on the top of the source drain doped region at the bottom of the contact hole;
and the first work function layer is positioned at the bottom of the pseudo gate opening.
14. The semiconductor structure of claim 13, wherein the first region is used to form an NMOS transistor, and the material of the first work function layer comprises titanium aluminum.
15. The semiconductor structure of claim 13, wherein the substrate further comprises a second region, the dielectric layer is further located on the surface of the substrate in the second region, the dummy gate opening is also located in the dielectric layer in the second region, and the source-drain doped regions are further located in the substrate on both sides of the dummy gate opening in the second region.
16. The semiconductor structure of claim 15, further comprising: the gate dielectric layers are positioned at the bottoms of the first area pseudo gate opening and the second area pseudo gate opening; the second work function layer is positioned on the surface of the second area gate dielectric layer; the second region is used for forming a PMOS transistor, and the material of the second work function layer comprises titanium nitride.
17. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: the plug is positioned on the surface of the metal silicide layer in the contact hole and is filled in the contact hole; and the gate layer is positioned on the surface of the first work function layer at the bottom of the dummy gate opening and is filled in the dummy gate opening.
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