CN1754860A - A kind of silicide process that is applicable to that nano-device is made - Google Patents
A kind of silicide process that is applicable to that nano-device is made Download PDFInfo
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- CN1754860A CN1754860A CN 200410080409 CN200410080409A CN1754860A CN 1754860 A CN1754860 A CN 1754860A CN 200410080409 CN200410080409 CN 200410080409 CN 200410080409 A CN200410080409 A CN 200410080409A CN 1754860 A CN1754860 A CN 1754860A
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Abstract
A kind of silicide process that is applicable to that nano-device is made, its key step are cleaning, vacuum annealing processing, sputter Ni film, sputtered with Ti N film, rapid thermal annealing, selective corrosion, glass deposit, contact hole forms and metallization.The present invention adds a block layer titanium nitride on the Ni film, form the TiN/Ni/Si structure, improves purging method simultaneously, optimizes the condition of film thickness and silicification reaction, has obtained good result.Not only the sheet resistance of film obviously reduces, and thermostability is significantly improved, promptly by low-resistance NiSi high resistant NiSi in opposite directions
2The temperature of Zhuan Bianing has improved mutually, and the shallow junction leakage current improves.Compare with conventional Ti and Co silicide process, this method processing step is few, and cost is low, and device performance improves significantly, thereby very attractive.Be conventional Ti and the irreplaceable technology of Co silicide process especially in inferior 50 nanotechnologies.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process technology, particularly a kind of silicide process-nickel (Ni) silicide process that is applicable to that nano-device is made.
Background technology
For reducing the series connection dead resistance of source/leakage and narrow polysilicon gate simultaneously, be unlikely to again because the silicification reaction between refractory metal and the super shallow junction of silicon induces junction leakage simultaneously, nickel silicide is a kind of more satisfactory selection.This is that nickel (Ni) silicide (NiSi) has the advantage of following uniqueness because compare with cobalt (Co) silicide with the titanium (Ti) of routine:
1) low NiSi formation temperature and big process window;
2) low NiSi sheet resistance;
3) consumption of few silicon;
4) dwindle with live width, the NiSi sheet resistance also reduces, because fringing effect;
5) the NiSi film is low at the silicon upper stress;
6) NiSi has low contact resistance to N type and P type silicon.
But nickel silicide technology also has its shortcoming, and Ni and silicide thereof are very responsive to oxygen, because the influence of oxygen raises the sheet resistance of film, and interface roughness, the shallow junction electric leakage increases; Conventional simultaneously NiSi poor heat stability.
Summary of the invention
The purpose of this invention is to provide a kind of silicide process that is applicable to that nano-device is made, shortcoming at conventional nickel silicide technology existence, employing prepares titanium nitride (TiN) film on NiSi, form the structure of TiN/Ni/Si, improve purging method simultaneously, optimize the condition of film thickness and silicification reaction, obtain good result.Not only the sheet resistance of NiSi film obviously reduces, and its thermostability is significantly improved, promptly by low-resistance NiSi high resistant NiSi in opposite directions
2The temperature of Zhuan Bianing has improved mutually, and the shallow junction leakage current also improves.Its reason is the TiN film that the upper strata covers, and has suppressed the invasion of Sauerstoffatom in Ni surface and the NiSi forming process subsequently and the film oxidation that causes, has improved film quality and NiSi/Si rough interface degree.Compare with conventional Ti and Co silicide process simultaneously, this method processing step is few, and cost is low, and device performance improves significantly, thereby very attractive.Be conventional Ti and the irreplaceable technology of Co silicide process especially in inferior 50 nanotechnologies.Concrete processing step is as follows:
Step 1: behind the source of finishing device/leakage rapid thermal annealing, carry out improved cleaning: 3
#Liquid (H
2SO
4: H
2O
2=5: 1), cleaning temperature 120-130 ℃, the 8-12 branch uses 1 then
#Liquid cleans (NH
4OH: H
2O
2: H
2O=0.8: 1: 5), temperature 62-65 ℃, the 5-8 branch, (HF/IPA liquid is hydrofluoric acid (HF): Virahol (IPA): H at hydrofluoric acid/Virahol at last
2O=0.5%: 0.02%: 1) in the solution, floods 30-60 second under the room temperature, through deionized water rinsing and at hot N
2After middle the drying, advance immediately in the sputter vacuum lock to vacuumize, shorten the time of in air, being detained as far as possible;
Step 2: vacuum annealing is handled: base vacuum degree: (4-8) * 10
-7Torr is heated to 250-350 ℃, constant temperature 10-15 branch, and cooling treats that vacuum returns to (4-8) * 10 then
-7Torr can carry out pre-sputter 5 minutes;
Step 3: sputter Ni film: base vacuum degree (4-8) * 10
-7Torr, sputtering power 800-1000 watt, operating pressure (4-6) * 10
-7Torr; Thickness is 13-22nm;
Step 4: sputtered with Ti N film: base vacuum degree (4-8) * 10
-7Torr, sputtering power 800-1000 watt, operating pressure (4-6) * 10
-7Torr; Ar/N
2=6/1, the TiN film thickness is 8-14nm;
Step 5: successively use acetone, each ultrasonic cleaning 5-8 branch of dehydrated alcohol, deionized water rinsing then, hot N
2The middle drying;
Step 6: rapid thermal annealing (RTA): temperature 480-600 ℃, time 15-30 second;
Step 7: selective corrosion: 3# liquid, 120-130 ℃, the time is the 10-14 branch, adds the 4-6 branch, adds the 4-6 branch again, per twice all will be carried out deionized water rinsing, behind the last deionized water rinsing, at hot N
2The middle drying;
Step 8: low thermal oxidation silicon and boron-phosphorosilicate glass deposit, furnace temperature 400-420 ℃, thickness 550-650nm;
Step 9: contact hole forms and metallization.
Description of drawings
Fig. 1 has provided As
+The NiSi sheet resistance is with forming variation of temperature on the heavily doped polysilicon, and contrasted the result that TiN layer and no TiN layer are arranged.
Fig. 2 has provided As
+NiSi sheet resistance and thickness are with the long variation of grid on the heavily doped polysilicon.
Embodiment
Embodiment:
Step 1: behind the source of finishing device/leakage rapid thermal annealing, carry out improved cleaning: 3# liquid, 120 ℃, 5 minutes, deionized water rinsing is followed 1# liquid, and 62 ℃, 5 minutes, deionized water rinsing flooded 40 seconds under the room temperature in HF/IPA solution then, and deionized water rinsing is at last at hot N
2After middle the drying, advance immediately in the sputter vacuum lock to vacuumize, shorten the time of in air, being detained as far as possible.
Step 2: vacuum annealing is handled: base vacuum degree: 6 * 10
-7Torr, substrate are heated to 300 ℃, constant temperature 10 minutes, and cooling treats that vacuum returns to 6 * 10 then
-7Torr, pre-sputter 5 minutes.
Step 3: sputter Ni film: base vacuum degree 6 * 10
-7Torr, 800 watts of sputtering powers, operating pressure 5 * 10
-7Torr; Ni film thickness 16nm.
Step 4: sputtered with Ti N film: base vacuum degree 6 * 10
-7Torr, 800 watts of sputtering powers, operating pressure 5 * 10
-7Torr; Ar/N
2=6/1, TiN film thickness 11nm;
Step 5: acetone, each ultrasonic cleaning of dehydrated alcohol each 5 minutes, deionized water rinsing then, hot N
2The middle drying.
Step 6: rapid thermal annealing (RTA): 530 ℃ of temperature, 25 seconds time;
Step 7: selective corrosion: 3# liquid, 120 ℃, 12 minutes time, add 4 fens, add 4 fens again, per deionized water rinsing in the middle of twice, behind the last deionized water rinsing at hot N
2The middle drying.
Step 8: low thermal oxidation silicon and boron-phosphorosilicate glass deposit, 420 ℃, 550nm;
Step 9: contact hole forms and metallization.
The result:
Present method has the Ni silicide of block layer TiN and nothing block layer individual layer Ni silicide comparison shows that:
1. sheet resistance reduces more than 11%;
2. thermostability improves: no TiN block layer, low-resistance SiNi is high resistant NiSi in opposite directions
2Phase transition temperature is 570 ℃, and TiN block layer is arranged, and NiSi is to NiSi
2Phase transition temperature is greater than 700 ℃;
3. when polysilicon gate length dropped to 24 nanometers, heavily doped polysilicon grid sheet resistance was 2.1 Ω/mouths, and it is 4.1 Ω/mouths that sheet resistance is leaked in the source;
4. the shallow junction leakage current obviously reduces, and homogeneity improves;
The present invention is applied to inferior 25 nanometer cmos devices research, and its characteristic is fine.
Claims (6)
1. silicide process that is applicable to that nano-device is made, its key step is:
Step 1: behind the source of finishing device/leakage rapid thermal annealing, carry out improved cleaning: use scavenging solution H for the first time
2SO
4: H
2O
2=5: 1, in 120-130 ℃ of cleaning 8-12 branch, scavenging solution NH for the second time
4OH: H
2O
2: H
2O=0.8: 1: 5, clean the 5-8 branch in 62-65 ℃; At hydrofluoric acid: Virahol: H
2O=0.5%: in 0.02%: 1 solution, flood 30-60 second under the room temperature, through deionized water rinsing and hot N
2The middle drying advances in the sputter vacuum lock to vacuumize immediately;
Step 2: vacuum annealing is handled: base vacuum degree: 4-8 * 10
-7Torr is heated to 250-350 ℃, constant temperature 10-15 branch, and cooling treats that vacuum returns to 4-8 * 10 then
-7Torr, pre-sputter 3-5 branch;
Step 3: sputter Ni film: base vacuum degree 4-8 * 10
-7Torr, sputtering power 800-1000 watt, operating pressure 4-6 * 10
-7Torr; The Ni film thickness is 13-22nm;
Step 4: sputtered with Ti N film: base vacuum degree 4-8 * 10
-7Torr, sputtering power 800-1000 watt, operating pressure 4-6 * 10
-7Torr; Ar/N
2=6/1, the TiN film thickness is 8-14nm;
Step 5: successively use acetone, each ultrasonic cleaning 5-8 branch of dehydrated alcohol, deionized water rinsing then, hot N
2The middle drying;
Step 6: rapid thermal annealing: temperature 480-600 ℃, time 15-30 second;
Step 7: selective corrosion: corrosive fluid H
2SO
4: H
2O
2=5: 1, in 120-130 ℃, the time is the 10-14 branch, adds the 4-6 branch, adds the 4-6 branch again, and per twice all will be carried out deionized water rinsing, behind the last deionized water rinsing, at hot N
2The middle drying;
Step 8: cryogenic oxidation silicon and boron-phosphorosilicate glass deposit, furnace temperature 400-420 ℃, thickness 550-650nm;
Step 9: contact hole forms and metallization.
2. the technology of claim 1 is characterized in that, step 1 cleaning temperature for the first time is 120 ℃, scavenging period 10 minutes; Cleaning temperature is 62 ℃ for the second time, and scavenging period is 5 minutes; Dipping time is 40 seconds.
3. the technology of claim 1 is characterized in that, during step 2 vacuum annealing is handled, and base vacuum degree: 6 * 10
-7Torr, substrate are heated to 300 ℃, constant temperature 10 minutes, and cooling treats that vacuum returns to 6 * 10 then
-7Torr, pre-sputter 5 minutes.
4. the technology of claim 1 is characterized in that, in the step 3 sputter Ni film, and base vacuum degree 6 * 10
-7Torr, 800 watts of sputtering powers, operating pressure 5 * 10
-7Torr.
5. the technology of claim 1 is characterized in that, in the step 4 sputtered with Ti N film, and base vacuum degree 6 * 10
-7Torr, 800 watts of sputtering powers, operating pressure 5 * 10
-7Torr.
6. the technology of claim 1 is characterized in that, the temperature of step 6 rapid thermal annealing is 530 ℃, 25 seconds time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100804095A CN1296971C (en) | 2004-09-29 | 2004-09-29 | Silicide process suitable for nanometer article manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100804095A CN1296971C (en) | 2004-09-29 | 2004-09-29 | Silicide process suitable for nanometer article manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1754860A true CN1754860A (en) | 2006-04-05 |
| CN1296971C CN1296971C (en) | 2007-01-24 |
Family
ID=36688452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100804095A Expired - Fee Related CN1296971C (en) | 2004-09-29 | 2004-09-29 | Silicide process suitable for nanometer article manufacture |
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| Country | Link |
|---|---|
| CN (1) | CN1296971C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403211A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for metal silicide |
| CN102437034A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for forming nickel silicide blocking layer |
| CN102446744A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Method for removing excessive nickel after formation of nickel silicide |
| CN105097472A (en) * | 2015-07-30 | 2015-11-25 | 上海华力微电子有限公司 | Method for reducing nickel erosion |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920005242A (en) * | 1990-08-20 | 1992-03-28 | 김광호 | Method of manufacturing transistor having structure of gate-insulator-semiconductor |
| JPH11233732A (en) * | 1998-02-13 | 1999-08-27 | Toshiba Corp | Thin film capacitor |
| KR100562710B1 (en) * | 2000-02-26 | 2006-03-23 | 삼성전자주식회사 | Method for manufacturing a semiconductor device |
| CN1144266C (en) * | 2000-12-19 | 2004-03-31 | 中国科学院微电子中心 | Titanium silicide method using amorphous pre-injection of Ge or Sb and washing |
| CN1134045C (en) * | 2000-12-19 | 2004-01-07 | 中国科学院微电子中心 | Auto-aligning method for Co to silicide |
-
2004
- 2004-09-29 CN CNB2004100804095A patent/CN1296971C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403211A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for metal silicide |
| CN102403211B (en) * | 2010-09-17 | 2015-05-20 | 中芯国际集成电路制造(北京)有限公司 | Preparation method for metal silicide |
| CN102437034A (en) * | 2011-08-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for forming nickel silicide blocking layer |
| CN102446744A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Method for removing excessive nickel after formation of nickel silicide |
| CN105097472A (en) * | 2015-07-30 | 2015-11-25 | 上海华力微电子有限公司 | Method for reducing nickel erosion |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1296971C (en) | 2007-01-24 |
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Owner name: INST OF MICROELECTRONICS, C. A. S Effective date: 20130419 Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHA Free format text: FORMER OWNER: INST OF MICROELECTRONICS, C. A. S Effective date: 20130419 |
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Effective date of registration: 20130419 Address after: 201203 Shanghai SMIC international integrated circuit manufacturing (Shanghai) Co., Ltd. Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Institute of Microelectronics, Chinese Academy of Sciences Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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