CN101728257B - Preparation method of gate dielectric/ metal gate integrated structure - Google Patents
Preparation method of gate dielectric/ metal gate integrated structure Download PDFInfo
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- CN101728257B CN101728257B CN2008102249085A CN200810224908A CN101728257B CN 101728257 B CN101728257 B CN 101728257B CN 2008102249085 A CN2008102249085 A CN 2008102249085A CN 200810224908 A CN200810224908 A CN 200810224908A CN 101728257 B CN101728257 B CN 101728257B
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Abstract
The invention relates to a preparation method of HfLaON gate dielectric/ TaN metal gate integrated structure, comprising the steps of: (1) after conventional cleaning, soaking in hydrofluoric acid/ isopropanol/ aqueous solution so as to inhibit the growth of particles and natural oxide; (2) immediately using RTA to grow ultrathin interface oxide layer SiOx or oxynitride layer SiON; (3) adopting aPVD method, and utilizing magnetic control reaction sputtering technology for alternately sputtering Hf-La target and Hf target to deposit HfLaON high dielectric constant (K) gate dielectric; (4) after deposition of HfLaON, rapidly carrying out thermal annealing; (5) adopting the PVD method, and sputtering a TaN metal film by magnetic control reaction; and (6) after formation of a metal TaN electrode and back ohmic contact, carrying out alloy annealing treatment.
Description
Technical field
The invention belongs to technical field of semiconductors, refer in particular to the preparation method of a kind of high-k (K) HfLaON gate medium/TaN metal gate integrated structure, be suitable for the application of 32 nanometers and following technology generation high-performance nano cmos device.
Background technology
Over more than 40 year, integrated circuit is by the sustainable development of mole theorem rule, along with device feature size constantly dwindles, gate oxide thickness is attenuate thereupon also, when grid progress is gone into inferior 50 nanometers, gate oxide thickness will be reduced to below 1.2 nanometers, if still adopt traditional polygate electrodes and oxide layer gate medium, will face huge challenge, as grid direct Tunneling electric current exponentially rule anxious increase, the polysilicon gate depletion effect is serious, gate resistance sharply increases etc.Particularly the tunnelling leakage current of gate medium has surpassed the limit that device can bear, and for this reason, must adopt high-k (K) material as novel gate medium.For eliminating the depletion of polysilicon effect, will adopt metal gate to replace polysilicon gate simultaneously as gate electrode.Though obtained a lot of achievements in high K/ metal gate research field recent years, still has a lot of problems not resolve, prick nail problem etc. as thermal stability problems, interface problem, the Fermi of material, be applied to produce on time and still have many challenges.For overcoming the problem that conventional SiON gate medium/polysilicon grating structure can not satisfy the requirement that device size further dwindles, the present invention proposes a kind of preparation method of high-dielectric-coefficient grid medium/metal gate integrated structure, i.e. the preparation method of HfLaON gate medium/TaN metal gate integrated structure.
Summary of the invention
The object of the present invention is to provide the preparation method of a kind of HfLaON gate medium/TaN metal gate integrated structure.
For realizing said method, the present invention adopts physical vapor deposition (PVD) method, utilize the technology of alternation response sputter hafnium (Hf)-lanthanum (La) target and Hf target to prepare a kind of dielectric constant and reach 21 high-dielectric-coefficient grid medium hafnium lanthanum oxygen nitrogen (HfLaON) film, and very high thermal stability is arranged, after 1000 ℃ of high-temperature quick thermal annealing (RTA), still can keep decrystallized structure.Adopting TaN is the TaN/HfLaON grid structure of metal gate electrode, and its grid tunnelling leakage current density ratio has the poly-Si/SiO of same equivalent oxide thickness (EOT)
2Little 5 orders of magnitude of grid structure.The integrated gate work function of TaN metal gate/HfLaON structure is 4.06eV, has satisfied the demand that the high-performance nano nmos device is made admirably.
The present invention not only has above-mentioned superiority, and compares with ald (ALD), and the PVD method is easier, cost is low, and is compatible better with existing big production technology.
Key step of the present invention is as follows:
Step 1) is cleaned: after device isolation forms, carry out the cleaning before interface oxide layer forms, adopt conventional method to clean earlier, at room temperature soak the 2-10 branch with hydrofluoric acid/isopropanol mixed solution then, deionized water rinsing advances stove immediately after the drying;
Step 2) formation of boundary layer SiOx or SiON: under 600-800 ℃ of temperature, at N
2In rapid thermal annealing (RTA) 20-120 second; Wherein boundary layer SiON can adopt and inject nitrogen rapid thermal annealing formation more earlier, also can form SiOx by first rapid thermal annealing, and nitrogenize forms SiON again;
The formation of step 3) high-k (K) gate dielectric membrane: adopt the PVD method, utilize reactive magnetron sputtering technology at N
2Alternating sputtering Hf-La target and the deposit of Hf target form HfLaON in/the Ar atmosphere, change the alternately time, can obtain the film of different La and Hf ratio;
Behind the high K medium of step 4) deposit rapid thermal annealing: temperature 500-1000 ℃, time 10-120 second;
The step 5) metal gate electrode forms: adopt the PVD method, utilize reactive magnetron sputtering technology at N
2Sputtering deposit TaN metal gate in the/Ar atmosphere forms the TaN metal electrode after the etching;
Step 6) back side ohmic contact forms: adopt the PVD method, utilize direct current sputtering technology backside deposition Al-Si film 600-1000 nanometer;
Under the step 7) 380-450 ℃ of temperature, N in alloying furnace
2Middle alloy annealing 30-60 branch.
Description of drawings
Fig. 1 is HfLaON/ of the present invention interface SiO
xThe high resolution transmission electron microscope of structure (HRTEM) photo, wherein (a) is unannealed sample; (b) be 1000 ℃ of rapid thermal annealing samples.
Fig. 2 is under same equivalent oxide thickness, TaN/HfLaON/SiO of the present invention
xThe grid tunnelling leakage current of grid structure and conventional poly-Si/SiO
2The comparison of grid structure.
Embodiment
For further specifying the technology of the present invention content, elaborate below in conjunction with embodiment and accompanying drawing.
The step that the present invention prepares high-k HfLaON film/TaN metal gate integrated structure is as follows:
Step 1) is cleaned: after device isolation forms, carry out the cleaning before interface oxide layer forms, adopt conventional method to clean earlier, use hydrofluoric acid then: isopropyl alcohol: the %:(0.01-0.04 of water=(0.3-0.8)) %:1 (volume ratio) mixed solution at room temperature soaks the 2-10 branch, deionized water rinsing advances stove immediately after the drying;
Step 2) boundary layer SiOx forms: under 600-800 ℃ of temperature, at N
2In rapid thermal annealing (RTA) 20-120 second, generate
Oxide layer, shown in Fig. 1 (a);
The formation of step 3) high-k (K) gate dielectric membrane: adopt the PVD method, utilize reactive magnetron sputtering technology at N
2Alternating sputtering Hf-La target and the deposit of Hf target form HfLaON in/the Ar atmosphere, and the sputter operating pressure is 5 * 10
-3Torr, sputtering power are 100-500W, and deposit forms HfLaON high-k gate dielectric film 10-60 dust.(a) Give has gone out the high resolution transmission electron microscope cross sectional photograph of the unannealed sample of HfLaON/SiOx to Fig. 1, and wherein the HfLaON film is 19.01 dusts, and boundary layer SIOx is 7.34 dusts.
Rapid thermal annealing behind the high K medium of step 4) deposit: acetone, each ultrasonic cleaning of absolute ethyl alcohol 5 minutes, deionized water rinsing advances stove immediately after the drying, and temperature 500-1000 ℃, time 10-120 second.Fig. 1 (b) Give has gone out 1000 ℃ of HfLaON/SiOx rapid thermal annealings, the high resolution transmission electron microscope cross sectional photograph after 20 seconds, because interfacial reaction, boundary layer SIOx attenuate is 2.93 dusts;
The step 5) metal gate electrode forms: adopt the PVD method, utilize reactive magnetron sputtering technology at N
2Sputter tantalum in the/Ar atmosphere (Ta) target deposit TaN metal gate, the sputter operating pressure is 5 * 10
-3Torr, nitrogen flow are 2-8SCCM, and sputtering power is 600-1000W, and TaN thickness 10-200 nanometer adopts Cl
2Plasma etching forms the TaN metal electrode;
Step 6) back side ohmic contact forms: adopt the PVD method, utilize direct current sputtering technology backside deposition Al-Si film 600-1000 nanometer;
Under step 7) alloy: the 380-450 ℃ temperature, N in alloying furnace
2Middle alloy annealing 30-60 branch.
Fig. 2 has provided under same equivalent oxide thickness (EOT), the TaN/HfLaON/SiO of this method preparation
xThe grid tunnelling leakage current of grid structure and conventional poly-Si/SiO
2The comparison of grid structure shows that adopting TaN is the TaN/HfLaON/SiO of metal gate electrode
xThe grid structure, its grid tunnelling leakage current density ratio has the poly-Si/SiO of same equivalent oxide thickness (EOT)
2Little 5 orders of magnitude of grid structure.C-V measures and match obtains TaN metal gate/HfLaON/SiO
xThe integrated gate work function of structure is 4.06eV, and the dielectric constant that obtains HfLaON high-K gate dielectric film in conjunction with the HRTEM analytical calculation is 21.These results of study show the TaN/HfLaON/SiO of new method preparation
xGrid integrated morphology characteristic good has satisfied the needs that the high-performance nano nmos device is made admirably.
Claims (9)
1. the preparation method of HfLaON gate medium/TaN metal gate integrated structure, its key step is as follows:
Step 1) is cleaned: after device isolation forms, carry out the cleaning before interface oxide layer forms, and at room temperature soak with hydrofluoric acid/isopropanol mixed solution, deionized water rinsing advances stove immediately after the drying;
Step 2) formation of boundary layer SiOx or SiON: adopt rapid thermal annealing;
The formation of step 3) gate dielectric membrane: adopt physical vapor deposition methods, utilize reactive magnetron sputtering technology alternating sputtering Hf-La target and the deposit of Hf target to form HfLaON;
Rapid thermal annealing behind the step 4) deposit gate medium;
The step 5) metal gate electrode forms: adopt physical vapor deposition methods, utilize magnetron sputtering technique sputtering deposit TaN metal gate, form the TaN metal electrode after the etching;
Step 6) back side ohmic contact forms: adopt physical vapor deposition methods, utilize direct current sputtering technology depositing Al-Si film overleaf;
Under step 7) 380-450 ℃, N in alloying furnace
2Middle annealing 30-60 minute.
2. preparation method according to claim 1 is characterized in that, the volume ratio of hydrofluoric acid in the step 1/isopropanol mixed solution is 0.2-1.5%:0.01-0.10%:1, soaks 2-10 minute.
3. preparation method according to claim 1 is characterized in that, the rapid thermal annealing temperature is 600-800 ℃ in the step 2, time 20-120 second.
4. preparation method according to claim 1 is characterized in that, the formation of step 2 median surface layer SiON is to adopt to inject nitrogen rapid thermal annealing formation more earlier, or first rapid thermal annealing formation SiOx, and nitrogenize forms SiON again.
5. preparation method according to claim 1 is characterized in that, the gate dielectric film sputter in the step 3 is at N
2Carry out in/Ar the atmosphere, regulate and control ratio and the thickness of La and Hf by the time that changes alternating sputtering Hf-La target and Hf target.
6. preparation method according to claim 1 is characterized in that, the rapid thermal annealing temperature is 600-1050 ℃ in the step 4, and the time is 4-120 second.
7. preparation method according to claim 1 is characterized in that, depositing metal grid film is at N in the step 5
2Reactive sputtering Ta target forms in/Ar the atmosphere, or in Ar atmosphere sputter TaN target.
8. preparation method according to claim 1 is characterized in that, the TaN metal gate electrode is to adopt Cl base plasma etching to form in the step 5, or forms with chemical wet etching.
9. preparation method according to claim 1 is characterized in that, the Al-Si film thickness of back spatter deposition is the 600-1000 nanometer in the step 6.
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| CN102386079B (en) * | 2010-09-02 | 2013-05-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of high K grid dielectric layer and method for forming MOS (Metal Oxide Semiconductor) transistor |
| CN102361006B (en) * | 2011-10-25 | 2016-08-24 | 上海集成电路研发中心有限公司 | A kind of preparation method of low stress tantalum nitrogen film |
| CN102437040A (en) * | 2011-11-17 | 2012-05-02 | 大连大学 | Method for preparing hafnium lanthanum oxide (HfLaO) high-dielectric gate dielectric film |
| CN105609412A (en) * | 2016-03-23 | 2016-05-25 | 云南大学 | Rapid annealing preparation method of Al-Si<+> ohmic contact electrode |
| JP6774800B2 (en) * | 2016-07-06 | 2020-10-28 | 株式会社Ｓｃｒｅｅｎホールディングス | Manufacturing method of semiconductor devices |
| US10008386B2 (en) | 2016-09-12 | 2018-06-26 | International Business Machines Corporation | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device |
| CN115029599A (en) * | 2022-06-24 | 2022-09-09 | 江西中锡金属材料有限公司 | La-Hf alloy target and preparation method thereof |
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| CN1841666A (en) * | 2005-03-31 | 2006-10-04 | 中国科学院微电子研究所 | Substitution grid preparation method |
| CN101217112A (en) * | 2007-01-04 | 2008-07-09 | 中国科学院微电子研究所 | A preparation method of nanometer scale W/TiN compound refractory metal bar |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1841666A (en) * | 2005-03-31 | 2006-10-04 | 中国科学院微电子研究所 | Substitution grid preparation method |
| CN101217112A (en) * | 2007-01-04 | 2008-07-09 | 中国科学院微电子研究所 | A preparation method of nanometer scale W/TiN compound refractory metal bar |
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Owner name: BEIJING YANDONG MICROELECTRNIC CO.,LTD. Free format text: FORMER OWNER: INST OF MICROELECTRONICS, C. A. S Effective date: 20150708 |
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