CN1841666A - Substitution grid preparation method - Google Patents

Substitution grid preparation method Download PDF

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CN1841666A
CN1841666A CN 200510011506 CN200510011506A CN1841666A CN 1841666 A CN1841666 A CN 1841666A CN 200510011506 CN200510011506 CN 200510011506 CN 200510011506 A CN200510011506 A CN 200510011506A CN 1841666 A CN1841666 A CN 1841666A
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CN100369207C (en
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徐秋霞
李瑞钊
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Beijing Yandong Microelectronic Co., Ltd.
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Institute of Microelectronics of CAS
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Abstract

The invention relates to a method for preparing for the semi-conductor component mental griddle CMOS with super depth and the following characteristic sizes in the field of displacing griddle preparing technology. It uses mental as griddle electrode. The main technology is a suit of displacing griddle preparing technology which comprises: choosing for the displacing griddle materials, forming the exquisite displacing griddle graph and exorcizing the flat and displacing griddle.

Description

A kind of preparation method of alternative gate
Technical field
The invention belongs to sub-micro and following characteristic size semiconductor device technology, relate to a kind of preparation method of alternative gate, relate to particularly and be used for a kind of alternative gate preparation method that sub-micro metal gate CMOS (CMOS (Complementary Metal Oxide Semiconductor)) makes.
Technical background
When narrowing down to inferior 0.1 μ m and gate oxide thickness, polysilicon gate cmos device grid length is thinned to 2.5nm when following, the barrier that polysilicon gate depletion effect, serious day by day boron penetration effects and too high gate resistance have become further raising cmos device performance, make the doped polysilicon gate that dominates at microelectronics technology for a long time face great challenge, emerging refractory metal bar (metal gate) then becomes present most promising substitute technology.Make gate electrode with metal, can fundamentally eliminate grid depletion effect and B penetration effect, obtain low-down gate electrode sheet resistance simultaneously.
Summary of the invention
The object of the present invention is to provide a kind of alternative gate preparation method.
For achieving the above object, the present invention adopts embedded metal gate CMOS technology (being alternative gate preparation technology) to realize a kind of metal gate CMOS technology of novelty.Of the present invention successfully is the key and one of basis of the Si technology sustainable development of ULSI from now on, has broad application prospects.
Preparation process of the present invention comprises:
1) after carrying out local oxide isolation or shallow-trench isolation and tuned grid injection, carries out alternative gate oxidation: N 2Protect following 600 ℃ to advance boat, be warming up to 750-870 ℃, N 2Constant temperature 10 minutes; Under the same temperature, N 2/ O 2=5: 1 ambient oxidation, oxidization time 60-120 minute; Then 750-870 ℃, N 2Annealed 20-60 minute; Last N 2Be cooled to 600 ℃ under the protection, go out boat;
2) chemical vapor deposition silicon nitride: temperature 760-820 ℃, pressure 250-300 milli torr, SiH 2Cl 225-35sccm, NH 380-100sccm, film thickness 220-260nm;
3) reactive ion etching forms silicon nitride alternative gate electrode: power 130-200W, etchant gas CHF 35-10sccm, SF 620-40sccm, He 100sccm mixes, pressure 300-500 millitorr;
Tetraethoxysilane thermal decomposition TEOS SiO then 2-1 film: temperature 720-760 ℃, thickness 90-150nm;
4) reactive ion etching TEOS SiO 2-1, form side wall-1: pressure 200-250m τ, RF (radio frequency) power 250-350W, CHF 3/ CF 4/ Ar=40-60sccm/5-16sccm/200-300sccm, no over etching, soft etching 5-10 second;
5) source/drain extension region low energy is injected: PMOS: 47BF 2, energy 5-8Kev, dosage 3-6 * 10 14Cm -2NMOS: 75As, energy 5-8Kev, dosage 3-6 * 10 14Cm -2
6) tetraethoxysilane thermal decomposition SiO 2-2: temperature 710-750 ℃, thickness 200-260nm;
Reactive ion etching SiO then 2-2, form side wall-2: pressure 200-250m τ, RF power 250-350W, CHF 3/ CF 4/ Ar=40-60sccm/5-16sccm/200-300sccm;
7) source/leakage is injected and rapid thermal annealing: PMOS: 47BF 2, energy 25-35Kev, dosage 1.5-3 * 10 15Cm -2NMOS: 75As, energy 40-55Kev, dosage 2-4 * 10 15Cm -21000-1020 ℃ of rapid thermal annealing temperature, time 4-8 second, formation source/drain junction;
8) source/drain region cobalt silicide forms: the sputter of cobalt/titanium compound film, spatter titanium film 4-7nm earlier, and spatter cobalt film 9-15nm again; Sputtering power is 700-900W all, and spattering the titanium operating pressure is 4-6 * 10 -3Torr, spattering cobalt is 5-7 * 10 -3Torr;
Twice rapid thermal annealing adds and carry out selective etching therebetween then: for the first time the rapid thermal annealing temperature is 630-670 ℃, time 15-30 second; 870-910 ℃ of rapid thermal annealing temperature for the second time after the selective etching, time 6-12 branch;
9) chemical vapor deposition cryogenic oxidation silicon and boron-phosphorosilicate glass: first chemical vapor deposition cryogenic oxidation silicon: temperature 350-450 ℃, film thickness 200-250nm; Chemical vapor deposition boron-phosphorosilicate glass: temperature 350-450 ℃ then, film thickness 700-800nm;
10) boron-phosphorosilicate glass refluxes: 750-800 ℃, and N 2, time 20-30 minute;
11) SOG (spin-on-glass promptly is coated with one deck solvent on substrate) coating for the first time and heat treatment: the coating condition is a room temperature, thickness 360-400nm; Heat-treat condition: 350-420 ℃, N 2, 30-50 minute;
12) return SOG-1:RF power 150-250W at quarter, pressure 250-350 milli torr, CF 420-30sccm, CHF 340-60sccm, O 22sccm, Ar 250-350sccm;
13) SOG coating for the second time and heat treatment: condition is with 13 steps;
14) return and carve SOG-2, return quarter with following condition earlier, i.e. RF power 150-250W, pressure 200-260 is torr in the least, CF 420-32sccm, CHF 318-30sccm, Ar 250-350sccm returns quarter with following condition, i.e. CF again when SOG-2 returns when having carved 415-25sccm, Ar 200-250sccm, RF power 250-350W, pressure 180-220 milli torr all exposes until alternative gate;
15) corrosion grid groove, the clean silicon nitride alternative gate of wet etching: H 3PO 4, 160-170 ℃, the grid groove forms;
16) float alternative gate silica: HF: H 2O=1: 20 rinse the alternative gate silica;
17) clean: with soaking 1-10 minute under the HF/IPA solution room temperature, the water flushing dries stove to 3# (routine)-1# (routine) again and again;
18) gate oxidation: N 2Protect following 600 ℃ to advance boat, be warming up to 750-850 ℃, N 2Constant temperature 10 minutes; Under the same temperature, N 2/ O 2=5: 1 ambient oxidation, oxidization time 10-50 minute; N 2Atmosphere, 750-850 ℃ of annealing, 15-60 minute; N 2Be cooled to 600 ℃, N under the protection 2Boat is pulled out in protection down slowly;
19) sputtering refractory metals, W/TiN=100-150nm/30-45nm, and reactive ion etching forms metal gate electrode.
Wherein the oxide thickness of the carrying out local oxide isolation in the step 1 is 350-420nm, and the oxide thickness of alternative gate oxidation is 5-7nm.
3 in the step 17 wherein #Liquid is H 2SO 4: H 2O 2=5: 1,120 ℃, 10 minutes; 1 #Liquid is NH 4OH: H 2O 2: H 2O=0.8: 1: 5,60 ℃, 5 minutes; HF/IPA liquid is HF: isopropyl alcohol (IPA): H 2O=0.5%: 0.02%: 1, dipping was 35 seconds under the room temperature.
Wherein the flushing of the water in the step 17 is a washed with de-ionized water.
Wherein step 18 gate oxide film thickness is the 15-35 dust.
Wherein the order of sputtering refractory metals is first sputtered with Ti N film in the step 19, back sputter W film.
Wherein the thickness after Overheating Treatment is 300-360nm in the step 11.
Wherein the etch rate of boron-phosphorosilicate glass is 2 times of SOG-1 in the step 12.
Wherein return in the step 14 and carve SOG-2, return quarter with the BPSG condition identical with the SOG-2 etch rate earlier, second step was used BPSG and LTO SiO again 2The condition that etch rate is identical is returned quarter.
Characteristics of the present invention are:
1, source/leakage (S/D) forms earlier, forms behind the grid.Avoided metal gate reactive ion etching (RIE) and source/leakage to inject the damage that causes gate medium, avoided the damage of high-temperature thermal annealing metal gate;
2, developed planarization with the conventional cmos process compatible, utilized the BPSG hot reflux to add the BPSG/SOG-1 speed difference and eat-back and add SOG-2/ low temperature SiO 2Constant speed is returned and is only carved extremely false grid exposure, has realized good planarization;
3, the formation technology of the removal of alternative gate electrode and groove;
4, the lithographic technique of tungsten/titanium nitride (W/TiN) composition metal grid adopts two step RIE etchings, optimizes experimental parameter, has reached satisfied effect.
Description of drawings
Fig. 1 is the structural representation of alternative gate of the present invention.Wherein: Fig. 1 a is the section of structure after silicide forms, symbol 1-alternative gate Si 3N 4, 2-side wall, 6-field silica, 15-CoSi; Fig. 1 b is that false grid are removed schematic diagram after the planarization, symbol 1-alternative gate Si 3N 44-alternative gate silica, 16-grid groove; Fig. 1 c is reactive ion etching W/TiN lamination metal grid, forms T shape gate electrode, symbol 11-W, 12-TiN, 13-three silica.
Fig. 2 is alternative gate preparation method's of the present invention schematic flow sheet.Wherein: symbol 1-alternative gate Si 3N 42-side wall-1; 3-side wall-2; 4-alternative gate silica; 5-source/drain extension region; 6-field silica; 7-SOG-1; 8-BPSG; 9-LTO SiO 210-SOG-2; 11-W; 12-TiN; 13-three silica; 14-PE SiO 2
Embodiment
In embedded metal gate CMOS technology of the present invention, one of main key is the technology of preparing of a cover alternative gate, and it comprises choosing of alternative gate material, the shaping of meticulous alternative gate figure, the removal of planarization and false grid.In this process, point of the present invention is:
1. chosen silicon nitride as an alternative grid material replace common polysilicon gate material, alternative gate can be removed with wet etching after the planarization like this.Select ratio because the wet etching silicon nitride has than higher corrosion silica, therefore can not cause especially plasma damage of chemistry, and adopt the reactive ion etching silicon nitride can obtain the steep gate figure of meticulousr section the silicon under it.
2. in the research of refractory metal bar, generally adopt chemico-mechanical polishing (CMP) technology to finish planarization in the world.We are off the beaten track, first stand-alone development a kind of and traditional more compatible planarization of CMOS technology, utilize BPSG (boron-phosphorosilicate glass) hot reflux to add BPSG/SOG (rotary coating glass)-1 speed difference and eat-back and add SOG-2/ low temperature SiO 2Constant speed is returned and is only carved extremely false grid exposure, has realized good planarization.Saved the expensive cost of configuration CMP main equipment.Simultaneously cleaner, compatible better.
Embodiment
Alternative gate structure of the present invention is referring to Fig. 1.
The preparation flow of alternative gate of the present invention is referring to Fig. 2.
The step that the present invention prepares alternative gate is:
1) LOCOS (selective oxidation) isolates or STI (shallow slot) isolation, an oxide thickness 380nm;
2) tuned grid injects;
3) alternative gate oxidation: big flow N 2Protect following 600 ℃ to advance boat, be warming up to 830 ℃ then, N 2Constant temperature 10 minutes; Under the same temperature, N 2/ O 2=5: 1 ambient oxidation, oxidization time 85 minutes; N 2Atmosphere, 830 ℃ of annealing, 30 minutes; N 2Be cooled to 600 ℃ under the protection, again at big flow N 2Boat is pulled out in protection down slowly;
4) chemical vapor deposition (LPCVD) silicon nitride: 790 ℃ of temperature, pressure 275 milli torrs, SiH 2Cl 229sccm, NH 390sccm, film thickness 240nm;
5) reactive ion etching forms silicon nitride alternative gate electrode: power 150W, etchant gas CHF 37sccm, SF 630sccm, He 100sccm mixes, air pressure 400 milli torrs; Tetraethoxysilane thermal decomposition SiO then 2-1 (TEOS-1) film: 740 ℃ of temperature, thickness 120nm;
6) reactive ion etching TEOS0-1 forms side wall-1: pressure 200 milli torrs, RF power 300W, CHF 3/ CF 4/ Ar=50sccm/10sccm/250sccm, no over etching, soft etching 7 seconds;
7) source/drain extension region low energy is injected: PMOS: 47BF 2, energy 7Kev, dosage 4 * 10 14Cm -2NMOS: 75As, energy 5Kev, dosage 5 * 10 14Cm -2
8) tetraethoxysilane thermal decomposition SiO 2-2 (TEOS-2): 740 ℃ of temperature, thickness 220nm; Reactive ion etching TEOS-2 then: pressure 200 milli torrs, RF power 300W, CHF 3/ CF 4/ Ar=50sccm/10sccm/250sccm, no over etching, soft etching 7 seconds; Form side wall-2;
9) source/leakage is injected and rapid thermal annealing (RTA): PMOS: 47BF 2, energy 25Kev, dosage 3 * 10 15Cm -2NMOS: 75As, energy 50Kev, dosage 4 * 10 15Cm -21010 ℃ of RTA temperature, 5 seconds time, formation source/drain junction;
10) source/drain region cobalt silicide forms: the sputter of cobalt/titanium compound film, spatter titanium film 5nm earlier, and spatter cobalt film 11nm again; Sputtering power is 800W all, and the operating pressure of spattering titanium is 5 * 10 -3Torr, spattering cobalt is 6.2 * 10 -3Torr; Twice rapid thermal annealing adds and carries out selective etching therebetween: rapid thermal annealing for the first time: 650 ℃ of temperature, 20 seconds time; Rapid thermal annealing for the second time after the selective etching: 900 ℃ of temperature, 7 minutes time; Finish device profile behind the silicide process shown in Fig. 2 (1);
11) chemical vapor deposition cryogenic oxidation silicon (LTO) and boron-phosphorosilicate glass (BPSG): chemical vapor deposition LTO: 400 ℃ of temperature, film thickness 200-250nm; Chemical vapor deposition BPSG temperature is 400 ℃ then, film thickness 700-800nm;
12) BPSG refluxes: 750 ℃, and N 2, 20 minutes time;
13) SOG coating for the first time and heat treatment: room temperature, thickness 360-400nm, this moment, the SOG-1 that fill the lowest point of figure was much thicker than the SOG-1 of the covering on step top owing to the flowability of SOG-1, and shoulder height is reduced; Heat treatment: 400 ℃, N 2, 40 minutes; After the heat treatment, thickness drops to 300-360nm; Shown in Fig. 2 (2);
14) return SOG-1:RF power 200W at quarter, pressure 300 milli torrs, CF 425sccm, CHF 350sccm, O 22sccm, Ar 300sccm, above-mentioned time quarter condition little, therefore the BPSG etch rate is 2 times of SOG-1, can effectively reduce the step of figure, this moment, the SOG-1 of the lowest point was corroded only, part BPSG reservation is shown in Fig. 2 (3);
15) SOG coating for the second time and heat treatment: condition is with step 13.Further reduced shoulder height, shown in Fig. 2 (4);
16) return and carve SOG-2, return quarter with the BPSG condition identical earlier with the SOG-2 etch rate, i.e. RF power 200W, pressure 230 is torrs in the least, CF 426sccm, CHF 324sccm, Ar 300sccm; When SOG-2 returns when having carved, use BPSG and LTO SiO again 2The condition that etch rate is identical is returned quarter, i.e. RF power 300W, pressure 200 milli torrs, CF 419sccm, Ar 250sccm; All expose until alternative gate, shown in Fig. 2 (5);
17) corrosion grid groove, the clean silicon nitride alternative gate of wet etching: H 3PO 4, 160 ℃, the grid groove forms;
18) float alternative gate silica: HF: H 2O=1: 20 rinse the alternative gate silica, shown in Fig. 2 (6);
19) clean: 3# (routine)-1# (routine)-more at room temperature soaked 5 minutes with the solution of hydrogen fluorine ester/isopropanol=0.5%/0.02%/1, and deionized water rinsing dries and advances stove immediately;
20) gate oxidation: big flow N 2Protect following 600 ℃ to advance boat, push away slowly, big flow N 2Protection; Be warming up to 830 ℃, N 2Constant temperature 10 minutes; Under the same temperature, N 2/ O 2=5: 1 ambient oxidation, oxidization time 20 minutes; N 2Atmosphere, 830 ℃ of annealing, 30 minutes; N 2Be cooled to 600 ℃ under the protection, again at big flow N 2Boat is pulled out in protection down slowly; Gate oxidation thickness 25 dusts;
21) sputtering refractory metals (W/TiN=100nm/35nm) is shown in Fig. 2 (7); And reactive ion etching formation metal gate electrode, shown in Fig. 2 (8).

Claims (9)

1. the preparation method of an alternative gate may further comprise the steps:
1) after carrying out local oxide isolation or shallow-trench isolation and tuned grid injection, carries out alternative gate oxidation: N 2Protect following 600 ℃ to advance boat, be warming up to 750-870 ℃, N 2Constant temperature 10 minutes; Under the same temperature, N 2/ O 2=5: 1 ambient oxidation, oxidization time 60-120 minute; Then 750-870 ℃, N 2Annealed 20-60 minute; Last N 2Be cooled to 600 ℃ under the protection, go out boat;
2) chemical vapor deposition silicon nitride: temperature 760-820 ℃, pressure 250-300 milli torr, SiH 2Cl 225-35sccm, NH 380-100sccm, film thickness 220-260nm;
3) reactive ion etching forms silicon nitride alternative gate electrode: power 130-200W, etchant gas CHF 35-10sccm, SF 620-40sccm, He 100sccm mixes, pressure 300-500 millitorr;
Tetraethoxysilane thermal decomposition TEOS SiO then 2-1 film: temperature 720-760 ℃, thickness 90-150nm;
4) reactive ion etching TEOS SiO 2-1, form side wall-1: pressure 200-250m τ, radio-frequency power 250-350W, CHF 3/ CF 4/ Ar=40-60sccm/5-16sccm/200-300sccm, no over etching, soft etching 5-10 second;
5) source/drain extension region low energy is injected: PMOS: 47BF 2, energy 5-8Kev, dosage 3-6 * 10 14Cm -2NMOS: 75As, energy 5-8Kev, dosage 3-6 * 10 14Cm -2
6) tetraethoxysilane thermal decomposition SiO 2-2: temperature 710-750 ℃, thickness 200-260nm;
Reactive ion etching SiO then 2-2, form side wall-2: pressure 200-250m τ, RF power 250-350W, CHF 3/ CF 4/ Ar=40-60sccm/5-16sccm/200-300sccm;
7) source/leakage is injected and rapid thermal annealing: PMOS: 47BF 2, energy 25-35Kev, dosage 1.5-3 * 10 15Cm -2NMOS: 75As, energy 40-55Kev, dosage 2-4 * 10 15Cm -21000-1020 ℃ of rapid thermal annealing temperature, time 4-8 second, formation source/drain junction;
8) source/drain region cobalt silicide forms: the sputter of cobalt/titanium compound film, spatter titanium film 4-7nm earlier, and spatter cobalt film 9-15nm again; Sputtering power is 700-900W all, and spattering the titanium operating pressure is 4-6 * 10 -3Torr, spattering cobalt is 5-7 * 10 -3Torr;
Twice rapid thermal annealing adds and carry out selective etching therebetween then: for the first time the rapid thermal annealing temperature is 630-670 ℃, time 15-30 second; 870-910 ℃ of rapid thermal annealing temperature for the second time after the selective etching, time 6-12 branch;
9) chemical vapor deposition cryogenic oxidation silicon and boron-phosphorosilicate glass: first chemical vapor deposition cryogenic oxidation silicon: temperature 350-450 ℃, film thickness 200-250nm; Chemical vapor deposition boron-phosphorosilicate glass: temperature 350-450 ℃ then, film thickness 700-800nm;
10) boron-phosphorosilicate glass refluxes: 750-800 ℃, and N 2, time 20-30 minute;
11) SOG coating for the first time and heat treatment: the coating condition is a room temperature, thickness 360-400nm; Heat-treat condition: 350-420 ℃, N 2, 30-50 minute;
12) return SOG-1:RF power 150-250W at quarter, pressure 250-350 milli torr, CF 420-30sccm, CHF 340-60sccm, O 22sccm, Ar 250-350sccm;
13) SOG coating for the second time and heat treatment: condition is with 13 steps;
14) return and carve SOG-2, return quarter with following condition earlier, i.e. RF power 150-250W, pressure 200-260 is torr in the least, CF 420-32sccm, CHF 318-30sccm, Ar 250-350sccm; When SOG-2 returns when having carved, return quarter with following condition again, i.e. CF 415-25sccm, Ar 200-250sccm, RF power 250-350W, pressure 180-220 milli torr all exposes until alternative gate;
15) corrosion grid groove, the clean silicon nitride alternative gate of wet etching: H 3PO 4, 160-170 ℃, the grid groove forms;
16) float alternative gate silica: HF: H 2O=1: 20 rinse the alternative gate silica;
17) clean: with soaking 1-10 minute under the HF/ aqueous isopropanol room temperature, the water flushing dries stove to the conventional 1#-of conventional 3#-again;
18) gate oxidation: N 2Protect following 600 ℃ to advance boat, be warming up to 750-850 ℃, N 2Constant temperature 10 minutes; Under the same temperature, N 2/ O 2=5: 1 ambient oxidation, oxidization time 10-50 minute; N 2Atmosphere, 750-850 ℃ of annealing, 15-60 minute; N 2Be cooled to 600 ℃, N under the protection 2Boat is pulled out in protection down slowly;
19) sputtering refractory metals, W/TiN=100-150nm/30-45nm, and reactive ion etching forms metal gate electrode.
2. according to claim 1, it is characterized in that the oxide thickness of the carrying out local oxide isolation in the step 1 is 350-420nm, the oxide thickness of alternative gate oxidation is 5-7nm.
3. according to the preparation method of claim 1, it is characterized in that 3 in the step 17 #Liquid is H 2SO 4: H 2O 2=5: 1,120 ℃, 10 minutes; 1 #Liquid is NH 4OH: H 2O 2: H 2O=0.8: 1: 5,60 ℃, 5 minutes; The HF/ aqueous isopropanol is HF: isopropyl alcohol: H 2O=0.5%: 0.02%: 1, dipping was 35 seconds under the room temperature.
4. according to the preparation method of claim 1, it is characterized in that the water flushing in the step 17 is a washed with de-ionized water.
5. according to the preparation method of claim 1, it is characterized in that step 18 gate oxide film thickness is the 15-35 dust.
6. according to the preparation method of claim 1, it is characterized in that the order of sputtering refractory metals is first sputtered with Ti N film in the step 19, back sputter W film.
7. according to the preparation method of claim 1, it is characterized in that the thickness in the step 11 after Overheating Treatment is 300-360nm.
8. according to the preparation method of claim 1, it is characterized in that in the step 12, the etch rate of boron-phosphorosilicate glass is 2 times of SOG-1.
9. according to the preparation method of claim 1, it is characterized in that, in the step 14, return and carve SOG-2 that return quarter with the BPSG condition identical with the SOG-2 etch rate earlier, second step was used BPSG and LTO SiO again 2The condition that etch rate is identical is returned quarter.
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Family Cites Families (6)

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US6248675B1 (en) * 1999-08-05 2001-06-19 Advanced Micro Devices, Inc. Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant using lowered temperatures
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CN102856180A (en) * 2011-06-30 2013-01-02 中国科学院微电子研究所 Integration method for replacement gate of semiconductor device
CN102856180B (en) * 2011-06-30 2016-05-25 中国科学院微电子研究所 A kind of alternative gate integrated approach of semiconductor devices
CN103094111A (en) * 2011-10-31 2013-05-08 无锡华润上华科技有限公司 Double diffusion metal oxide semi-conductor (DMOS) device and manufacturing method thereof
CN103854966A (en) * 2012-11-30 2014-06-11 中国科学院微电子研究所 Planarization processing method
US9406549B2 (en) 2012-11-30 2016-08-02 Institute of Microelectronics, Chinese Academy of Sciences Planarization process
CN103854966B (en) * 2012-11-30 2016-08-24 中国科学院微电子研究所 Planarization processing method

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