CN102779751B - Method for manufacturing semiconductor device - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title claims description 55
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000004528 spin coating Methods 0.000 claims abstract description 7
- 239000011521 glass Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 30
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000007711 solidification Methods 0.000 claims description 4
- 230000008023 solidification Effects 0.000 claims description 4
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 3
- 125000003698 tetramethyl group Chemical group [H]C([H])([H])* 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000008569 process Effects 0.000 description 18
- 238000005530 etching Methods 0.000 description 14
- 239000004020 conductor Substances 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000008485 antagonism Effects 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007850 degeneration Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229940043379 ammonium hydroxide Drugs 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 tetramethyl aqua ammonia Chemical compound 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application discloses a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate; forming a gate stack on the semiconductor substrate, wherein the gate stack comprises a gate dielectric layer and a sacrificial gate electrode layer, the gate dielectric layer is positioned on the semiconductor substrate, and the sacrificial gate electrode layer is positioned on the gate dielectric layer; forming a side wall around the gate stack; forming source/drain regions on two sides of the gate stack and embedded in the semiconductor substrate; forming SiO on the semiconductor substrate2Layer of said SiO2Spin-coating spin-on glass (SOG) on the layer, and flattening until the sacrificial gate electrode layer is exposed; removing the sacrificial gate electrode layer to form an opening in the side wall; a replacement gate electrode is formed within the opening.
Description
Technical field
The present invention relates to sub-micro technical field of semiconductor device, particularly relate to the alternative gate preparation method of a kind of high-k gate dielectric/metal-gate structures semiconductor device, the method adopts sacrifices polygate electrodes as false gate electrode, after flatening process, remove and sacrifice polycrystalline silicon dummy gate electrode, form metal gate electrode.
Background technology
Over more than 40 year, integrated circuit technique is by Moore's Law sustainable development, and characteristic size constantly reduces, and integrated level improves constantly, and function is more and more stronger.At present, the characteristic size of mos field effect transistor (MOSFET) enters sub-50 nm.With the continuous reduction of device feature size, if still adopt traditional polysilicon gate, poly-Si depletion effect will be more and more serious, and polysilicon resistance also will increase thereupon, the boron penetration phenomenon of PMOS can be more remarkable, and these obstacles are by the further raising of serious limiting device performance.In order to overcome above difficulty, industrial quarters starts to adopt high-k, and (high k) gate dielectric/metal gate structure replaces traditional silica/polysilicon grating structure.
In the preparation of high-k gate dielectric/metal gate semiconductor device, if still adopt the preparation technology similar to standard CMOS process flow, namely source/drain is prepared after first preparing metal gate electrode, although technique is simple, mutually compatible with standard CMOS process, and some techniques conventional in standard CMOS process also can adopt in first grid technique, be conducive to saving cost, but there is the shortcoming that some are difficult to overcome in this method: be first the electrology characteristic that ion penetration that metal gate electrode is easily injected into source/drain affects device; Next is that the high-temperature technology activating source/drain impurity can have a great impact the work function of metal gate, and most of metal gate material its work function after the high temperature anneal to forbidden band central mobile, can cause the degeneration of device performance.
Summary of the invention
Main purpose of the present invention is the manufacture method providing a kind of semiconductor device, and the method comprises: provide Semiconductor substrate; Form grid on the semiconductor substrate stacking, described grid are stacking comprises gate dielectric layer and sacrificial gate dielectric layer, and wherein, described gate dielectric layer is positioned in described Semiconductor substrate, and described sacrificial gate dielectric layer is positioned on described gate dielectric layer; Around the stacking formation side wall of described grid; In the stacking both sides of described grid and embed described Semiconductor substrate formed source/drain region; Form SiO on the semiconductor substrate
2layer, at described SiO
2spin coating SOG (Spin On Glass, spin on glass dielectric layer) on layer, and carry out being planarized to described sacrificial gate dielectric layer and expose; Remove described sacrificial gate dielectric layer to form opening in described side wall; Alternative gate electrode is formed in described opening.
According to the manufacture method of this semiconductor device provided by the invention, first form high-k gate dielectric/false gate electrode structure, after completing source/drain injection and activation technology, false gate electrode is removed by planarization, form grid groove, then depositing metal grid again, complete the preparation of high-k gate dielectric/metal gate semiconductor device.The advantage of this rear grid technique is that metal gate electrode is formed after source/drain activation heat annealing process, avoid the impact of high-temperature technology on metal gate characteristic, make device obtain very high stability and consistency, be conducive to forming high performance high-k gate dielectric/metal gate semiconductor device and circuit.
According to embodiments of the invention, adopt SiO
2+ SOG technique realizes planarization.Such as, first, LTO technique is adopted to form SiO
2dielectric layer, can realize preliminary planarization, reduces the difference in height between the stacking and source/drain of grid; Then, SOG is adopted to carry out planarization further.Liquid SOG has good flattening effect, can effectively fill and reduce the difference in height between the stacking and source/drain of grid, reach desirable flattening effect.SiO can be formed after SOG annealing solidification
2dielectric layer, the SiO formed with LTO
2dielectric layer is mutually compatible, is conducive to later stage employing dry etch process and obtains desirable flattening effect.
According to embodiments of the invention, TMAH is adopted to remove polycrystalline silicon dummy gate electrode process.Such as, first, HF acid is adopted to remove the oxide layer of polycrystalline silicon dummy gate top of electrodes; Then, TMAH wet corrosion technique is adopted to remove remaining polysilicon gate electrode.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the embodiment of the present invention, above-mentioned and other objects of the present invention, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1-10 shows the sectional view manufacturing the device architecture that each step obtains in the flow process of semiconductor device according to the embodiment of the present invention;
Figure 11 and 12 shows the electrology characteristic of the HfSiON/TaN/W high-k gate dielectric layer/work-function layer/metal gate conductor structure nMOSFET prepared according to the embodiment of the present invention;
Figure 13 and 14 shows the HfSiAlON/AlN prepared according to the embodiment of the present invention
xthe electrology characteristic of the pMOSFET of/Mo high-k gate dielectric layer/work-function layer/metal gate conductor structure.
Description of reference numerals:
1000 Semiconductor substrate;
1001 channel regions;
1002 high-k gate dielectric layers;
1004 sacrificial gate dielectric layer;
1006 hard mask layer (SiO
2);
1008 first side wall (Si
3n
4);
1009 source and drain extension areas;
1010 second side wall (SiO
2);
1012 source/drain regions;
1014 metal silicides;
1016SiO
2dielectric layer;
1018 spin on glass (SOG);
1022 workfunction metal gate electrode layers;
1024 metal gate conductor layers;
1026 isolation (LOCOS).
Embodiment
Below, by the specific embodiment shown in accompanying drawing, the present invention is described.But should be appreciated that, these describe just exemplary, and do not really want to limit the scope of the invention.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring concept of the present invention.
Rotating fields schematic diagram according to the embodiment of the present invention shown in the drawings.These figure not draw in proportion, wherein for purposes of clarity, are exaggerated some details, and may eliminate some details.The shape of the various regions shown in figure, layer and the relative size between them, position relationship are only exemplary, in reality may due to manufacturing tolerance or technical limitations deviation to some extent, and those skilled in the art can design the regions/layers with difformity, size, relative position in addition needed for actual.
Fig. 1 ~ 10 show in detail the sectional view manufacturing the device architecture that each step obtains in semiconductor device flow process according to the embodiment of the present invention.Below, with reference to these accompanying drawings, each step according to the embodiment of the present invention is described in detail.
First, as shown in Figure 1, Semiconductor substrate 1000 is provided.Substrate 1000 can comprise any applicable semiconductor substrate materials, can be specifically but be not limited to silicon, germanium, SiGe, SOI (semiconductor-on-insulator), carborundum, GaAs or any III/V compound semiconductor etc.In addition, Semiconductor substrate 1000 can comprise epitaxial loayer alternatively, can by stress changes to strengthen the property.
Semiconductor substrate 1000 can be formed with isolation structure 1026, preferably adopt carrying out local oxide isolation (Local Oxidation of Silicon, LOCOS).Also can adopt other isolation structures in an embodiment of the present invention, isolation structure and purport of the present invention have nothing to do, and repeat no more here.
Then, Semiconductor substrate 1000 forms grid stacking.
For this reason, such as shown in Figure 2, Semiconductor substrate 1000 forms high-k gate dielectric layer 1002.Particularly, Semiconductor substrate 1000 can be cleaned, such as, adopt HF+IPA+H
2o removes natural oxidizing layer.Then, preferably, can adopt rapid thermal anneal process substrate surface formed 5 to
siO
2(this layer is very thin, therefore this SiO is not clearly shown in figure for boundary layer
2boundary layer), and adopt magnetron sputtering technique at SiO
2deposit high-k gate dielectric on boundary layer.Such as, for nMOSFET, can deposit HfSiON high-k gate dielectric; For pMOSFET, can deposit HfSiAlON high-k gate dielectric.Then, carry out quick thermal annealing process to high-k gate dielectric, annealing temperature is 700 DEG C to 900 DEG C, thus forms high-k gate dielectric layer 1002.
Then, high-k gate dielectric layer 1002 forming sacrificial gate dielectric layer 1004, such as, can be polysilicon layer.Particularly, LPCVD (Low-Pressure Chemical Vapor Deposition, low-pressure chemical vapor phase deposition) mode can be adopted to form sacrifice polysilicon layer, the thickness of sacrificing polysilicon layer can be 150nm to 190nm.
Then, sacrificial gate dielectric layer 1004 continuing form hard mask layer 1006, such as, can be SiO
2layer.Particularly, LTO (Low-temperature oxidation, low-temperature oxidation) mode can be adopted to form SiO
2hard mask layer, SiO
2hard mask layer thickness can be 40-70nm.At this, the selection of thickness is determined according to the etching of polysilicon gate and side wall below, requires after the etching through grid heap superimposition side wall, SiO
2hard mask layer thickness needs to remain 10-20nm, forms silicide to prevent sacrificing polysilicon layer top.
Then, as shown in Figure 3, patterning etching is carried out to grid structure.Particularly, anti-etching dose of spin coating, antagonism etching agent carries out patterning, is shelter etching SiO with anti-etching dose
2hard mask layer 1006, then removes anti-etching dose, with SiO
2hard mask layer is shelter etching polysilicon layer 1004 and high-k gate dielectric layer 1002, thus it is stacking to form grid.
Then, as shown in Figures 4 and 5, in the stacking both sides of grid around the stacking formation sidewall structure of grid.According to embodiments of the invention, double layer side wall construction or three layers of sidewall structure can be formed.
Such as, first as shown in Figure 4, in the stacking both sides of grid such as, around grid stacking formation first side wall 1008, Si
3n
4side wall.Particularly, PECVD (Plasma-Enhanced Chemical Vapor Deposition, plasma-reinforced chemical vapor deposition) mode can be adopted to form one deck Si
3n
4layer, thickness can be 50-90nm, then adopts dry etch process, such as, be RIE (Reactive-Ion Etching, the reactive ion etching) Si to deposit
3n
4layer etches, and only retains it and is positioned at part on the stacking sidewall of grid, to form Si
3n
4side wall.After formation first side wall 1008, ion implantation can be adopted to form source/drain extension area 1009.Such as, for nMOSFET, As or Sb can be injected; For pMOSFET, BF can be injected
2or In.
Then, as shown in Figure 5, the second side wall 1010, such as SiO is formed at the first side wall 1008 outer ring around the first side wall 1008
2side wall.Particularly, LTO mode can be adopted to form one deck SiO
2layer, thickness can be 80-120nm, then adopts dry etch process to the SiO formed
2layer etches, and only retains it and is positioned at part on the first side wall 1008 sidewall, to form SiO
2side wall.After formation second side wall 1010, ion implantation can be adopted to form source-drain area 1012.Such as, for nMOSFET, As or Sb can be injected; For pMOSFET, BF can be injected
2or In.
According to other embodiments of the invention, can also at the outer formation further of the second side wall 1010 the 3rd side wall, the material of the 3rd side wall preferably includes Si
3n
4.3rd side wall is not shown in figure.
Then, silicide 1014 can be formed on source-drain area.According to embodiments of the invention, silicide can select Ni silicide.
Then, as shown in Figure 6, the Semiconductor substrate being formed with device architecture shown in Fig. 5 forms dielectric layer 1016, such as SiO
2.According to embodiments of the invention, LTO mode can be adopted to form SiO
2dielectric layer, SiO
2thickness of dielectric layers is at 600 to 800nm.
Then, spin coating spin on glass (SOG) 1018.Liquid state SOG can fill the sunk part of wafer surface, reaches the object of device surface planarization.Then to SOG annealing solidification, after making the solvent evaporates in SOG, SiO can be formed
2layer.
Then, as shown in Figure 7, to SiO
2dielectric layer 1016 and SOG layer 1018 carry out further planarization, to expose altered sacrificial gate electrode, to carry out alternative gate process subsequently.Particularly, dry etch process such as can be adopted to etch SOG 1018 to SOG and SiO
2dielectric layer 1016 interface.Then, according to SOG and SiO
2etch rate ratio is 1: 1.2 to 1: 2 dry etching SOG and SiO
2dielectric layer exposes to altered sacrificial gate electrode, now, at source-drain area residue SiO
2thickness of dielectric layers is 50nm to 150nm.
Then, as shown in Figure 8, sacrifice polygate electrodes is removed.Such as, diluted hydrofluoric acid (volume ratio HF: H can be adopted
2o=1: 50 ~ 1: 10) solution corrosion sacrifices the residual oxide layer at polygate electrodes top; Then, adopt tetramethyl aqua ammonia (Tetramethy ammoniumhydroxide, TMAH) solution corrosion to sacrifice polygate electrodes, in side wall, form opening.Preferably, the concentration of TMAH solution is 5%-20% (volume ratio), and temperature is 50-80 DEG C.
Then, as shown in Figure 9, in side wall opening, metal gate is formed.Particularly, high-k gate dielectric 1002 forms workfunction metal gate electrode layer 1022.Such as, for nMOSFET, it can be TaN metal gate electrode layer; For pMOSFET, can be AlN
xmetal gate electrode layer.Depositing metal grid conductor layer 1024 on workfunction metal gate electrode layer 1022.Such as, for nMOSFET, it can be W metal gate conductor layer; For pMOSFET, it can be Mo metal gate conductor layer.
Then, as shown in Figure 10, patterning is carried out to metal gate conductor layer 1024 and workfunction metal gate electrode layer 1022, to form final grid structure.Particularly, such as anti-etching dose of spin coating on metal gate conductor layer 1024, antagonism etching agent carries out patterning, and then using plasma dry etching metal gate conductor layer 1024 and workfunction metal gate electrode layer 1022, to form metal-gate structures.At this, preferably anti-etching dose of patterning will cover side wall open outer side 0.5 to 4 μm, thus forms T-shaped metal-gate structures.
In addition, for completing whole device, the electrical contact with source/drain region is formed.Such as, photoetching source/drain through hole, fills Ti/TiN/Al interconnect metallization lines wherein, and patterned etching forms source and drain contact site (not shown).
In the above description, the ins and outs such as composition, etching for each layer are not described in detail.But it will be appreciated by those skilled in the art that and by various means of the prior art, the layer of required form, region etc. can be formed.In addition, in order to form same structure, those skilled in the art can also design the not identical method with method described above.
It is the electrology characteristic of the HfSiON/TaN/W high-k gate dielectric layer/work-function layer/metal gate conductor structure nMOSFET adopting the present invention to prepare shown in Figure 11 and 12.The threshold voltage of this example device is 0.24V, and saturation current is 1.17 × 10
-4a/ μm (| V
gS|=| V
dS|=1.5V).
The HfSiAlON/AlN adopting the present invention to prepare shown in Figure 13 and 14
xthe electrology characteristic of the pMOSFET of/Mo high-k gate dielectric layer/work-function layer/metal gate conductor structure.The threshold voltage of this example device is-1.29V, and saturation current is 1.38 × 10
-4a/ μm (| V
gS|=| V
dS|=2.5V).
The manufacture method of this semiconductor device provided by the invention adopts sacrifices polygate electrodes as false gate electrode, effectively avoids first grid technique high-temperature annealing process on the impact of high-k gate dielectric/metal-gate structures electrology characteristic.In concrete preparation technology, what can adopt in following multinomial technology is one or more to improve device performance, comprising:
-adopt double layer side wall construction (as Si
3n
4/ SiO
2) or three layers of sidewall structure (as Si
3n
4/ SiO
2/ Si
3n
4)
Such as, Si is being adopted near metal gate side
3n
4first side wall can effectively prevent high-k gate dielectric and metal gate oxidized, avoid the increase of high-k gate dielectric equivalent oxide thickness and the degeneration of metal gate characteristic.
-adopt SiO
2+ SOG flatening process
First, SiO is formed
2dielectric layer (such as, adopt LTO technique), can realize preliminary planarization, reduces the difference in height between the stacking and source/drain of grid; Then, SOG is adopted to carry out planarization further.Liquid SOG has good flattening effect, can effectively fill and reduce the difference in height between the stacking and source/drain of grid, reach desirable flattening effect.SiO can be formed after SOG annealing solidification
2dielectric layer, the SiO formed with LTO
2dielectric layer is mutually compatible, is conducive to later stage employing dry etch process and obtains desirable flattening effect.
-adopt TMAH wet corrosion technique to be conducive to improving sacrifice polysilicon gate to the Selection radio of high-k gate dielectric
Because TMAH has very high Selection radio for oxide layer and polysilicon, namely very thin oxide layer can stop TMAH to the corrosion of polysilicon, therefore, before TMAH wet corrosion technique, adopt hydrofluoric acid solution to remove sacrifice the residual oxide layer at polysilicon gate top or the oxide layer of self-assembling formation, to reduce the impact of oxide layer on TMAH wet corrosion technique.
With reference to embodiments of the invention, explanation is given to the present invention above.But these embodiments are only used to the object illustrated, and are not intended to limit the scope of the invention.Scope of the present invention is by claims and equivalents thereof.Do not depart from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall within the scope of the present invention.
Claims (11)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided;
Form grid on the semiconductor substrate stacking, described grid are stacking comprises gate dielectric layer and sacrificial gate dielectric layer, and wherein, described gate dielectric layer is positioned in described Semiconductor substrate, and described sacrificial gate dielectric layer is positioned on described gate dielectric layer;
Around the stacking formation side wall of described grid, described side wall comprises the first side wall and the second side wall, and wherein the material of the first side wall is Si
3n
4;
In the stacking both sides of described grid and embed described Semiconductor substrate formed source/drain region;
Low-temperature oxidation is adopted to form SiO on the semiconductor substrate
2layer, at described SiO
2spin coating spin on glass SOG layer on layer, and pass through according to SOG layer and SiO
2layer etch rate ratio is 1: 1.2 to 1: 2 dry etching SOG layer and SiO
2layer carries out being planarized to described sacrificial gate dielectric layer and exposes;
Remove described sacrificial gate dielectric layer to form opening in described side wall;
In described opening, form alternative gate electrode, the grid that wherein said alternative gate electrode and described gate dielectric layer form semiconductor device are stacking.
2. method according to claim 1, wherein, the step forming grid stacking on the semiconductor substrate comprises:
Form gate dielectric layer, sacrificial gate dielectric layer and hard mask layer successively on the semiconductor substrate;
Patterning is carried out to hard mask layer, forms gate pattern;
Described sacrificial gate dielectric layer and gate dielectric layer are etched for sheltering with hard mask layer, stacking to form grid.
3. method according to claim 1 and 2, wherein, described gate dielectric layer comprises high-k gate dielectric layer.
4. method according to claim 1, wherein, described sacrificial gate dielectric layer comprises polysilicon gate electrode layer.
5. method according to claim 1, wherein, described second side wall is by SiO
2formed.
6. method according to claim 5, wherein, the step forming the second side wall around described first side wall comprises:
Low-temperature oxidation mode is adopted to form SiO on the semiconductor substrate
2layer;
To described SiO
2pattern layers, to form the second side wall around the first side wall.
7. method according to claim 5, wherein, the step around the stacking formation side wall of described grid comprises further:
The 3rd side wall is formed around described second side wall;
Wherein said 3rd side wall is by Si
3n
4formed.
8. method according to claim 1, wherein, at described SiO
2on layer after spin coating SOG, described method comprises further:
Annealing solidification is carried out to SOG.
9. method according to claim 4, wherein, described removal sacrificial gate dielectric layer comprises with the step forming opening in described side wall: adopt tetramethyl aqua ammonia TMAH wet etching sacrificial gate dielectric layer.
10. method according to claim 9, wherein, before described employing TMAH wet etching sacrificial gate dielectric layer, described method comprises further: adopt hydrofluoric acid wet etching to remove the oxide layer of sacrificial gate dielectric layer top layer.
11. methods according to claim 1, wherein, the described step forming alternative gate electrode in described opening comprises: in described opening, form metal gate electrode.
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| CN102543696A (en) * | 2010-12-17 | 2012-07-04 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
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| US20020142531A1 (en) * | 2001-03-29 | 2002-10-03 | Hsu Sheng Teng | Dual damascene copper gate and interconnect therefore |
| JP5282419B2 (en) * | 2007-04-18 | 2013-09-04 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
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|---|---|---|---|---|
| CN1841666A (en) * | 2005-03-31 | 2006-10-04 | 中国科学院微电子研究所 | Preparation method of replacement gate |
| CN102543696A (en) * | 2010-12-17 | 2012-07-04 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
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| CN102779751A (en) | 2012-11-14 |
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