CN1225799C - MOSFET and its manufacture - Google Patents
MOSFET and its manufacture Download PDFInfo
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- CN1225799C CN1225799C CN 02118191 CN02118191A CN1225799C CN 1225799 C CN1225799 C CN 1225799C CN 02118191 CN02118191 CN 02118191 CN 02118191 A CN02118191 A CN 02118191A CN 1225799 C CN1225799 C CN 1225799C
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Abstract
The present invention relates to a metallic oxide semiconductor field effect transistor (MOSFET) and a manufacturing method thereof. The metallic oxide semiconductor field effect transistor is characterized in that a trench is arranged in a semiconductor substrate; a channel area is a doped semiconductor layer crossing the trench; grid electrodes are positioned in the trench and on the trench, and surround the channel area with a grid dielectric layer in between; a gap wall and an insulation layer are respectively separated between the grid electrodes and the side wall and the bottom of the trench. The manufacturing method has the following steps that firstly, the trench which is filled by an insulation layer is formed on the semiconductor substrate; after the upper layer of the insulation layer is removed, the gap wall is formed on the side wall of the trench, and the trench is filled by a sacrificial layer. The doped semiconductor layer is formed and defined on the substrate to form a device area crossing the sacrificial layer. The sacrificial layer is removed, and a grid dielectric layer is formed on the surface of the device area. A conducting layer is formed on the semiconductor substrate, and is filled in the trench. The conducting layer is redefined to form the grid electrodes which are formed in the trench and on the trench. A source electrode and a drain electrode are formed on both sides of the grid electrodes.
Description
Technical field
The present invention relates to structure and the manufacture method thereof of a kind of semiconductor device (Semiconductor Device), particularly a kind of mos field effect transistor (MOSFET) and manufacture method thereof.
Background technology
Along with the live width (Line width) of metal-oxide semiconductor (MOS) conductor (MOS) manufacture method is dwindled day by day, the leakage current of locating away from grid (Gate) between source electrode (Source) and drain electrode (Drain) (Leakage Current) therefore increases.Though this leakage current can borrow the gate dielectric layer (Gate Dielectric) of thinner thickness to be reduced, but reduce to 0.1 μ m when following when the manufacture method live width, even if the gate dielectric layer of very thin thickness also can't reduce leakage current.For this problem, the Hu Zhengming of U.S. Berkeley University of California (Chermling Hu, transliteration) professor points out that two kinds of solution party adopt the thickness semiconductor-based end as thin as a wafer to make MOSFET to, the first, no longer include in the substrate away from the grid part like this, and thoroughly eliminated herein leakage current; It two is to form double gate (DoubleGate) structure, and it gets up the channel region double team across gate dielectric layer, makes whole channel region all be subjected to the grid electric field effects, and the firing current of the device that is increased (On-current), and reduce leakage current.
Therefore, forefathers proposed a kind of fin-shaped field-effect transistor in conjunction with above-mentioned two ideas (Fin FET, FinFET), its structure is shown in Fig. 1-1,1-2,1-3, wherein Fig. 1-2/1-3 is the profile of line of cut I-I '/II-II ' of Fig. 1-1.On the other hand, the formation step of this fin-shaped field-effect transistor is as follows: at first providing has silicon (Si) substrate 100 on the insulating barrier, and wherein the thickness of the silicon layer on the insulating barrier 105 (icon not, but be body before the number in the figure) is 100nm.Then making this silicon layer thinning with thermal oxidation method is 50nm, on silicon layer, form the curtain layer of hard hood 110 of cryogenic oxidation silicon (LTO) material then, carry out the little shadow manufacture method of electron beam (Electron Beam) of 100keV and anisotropic etching (Anisotropic Etching) manufacture method again with definition curtain layer of hard hood 110 and this silicon layer, thereby form the fin-shaped silicon layer 120 about width 20nm--50nm, its narrow degree is asked for an interview Fig. 1-1 and 1-3.Then in substrate 100, become one polysilicon-germanium (Poly Si-Ge) layer (icon not in regular turn, but be body before number in the figure 140 and 150) with the curtain layer of hard hood 130 of cryogenic oxidation silicon material, define again this two to form lifting source electrode 140 and drain electrode 150, its thickness is much larger than fin-shaped silicon layer 120.
Please continue with reference to Fig. 1-1,1-2,1-3 the then conformal silicon nitride layer of deposition (not icon, but be number in the figure body before) on silicon base 100, anisotropic etching and form clearance wall 160 in addition again.In this anisotropic etching step, behind the complete etching off of the silicon nitride layer on the curtain layer of hard hood 130, still proceeded etching (Over-etch), so that the silicon nitride of very little fin-shaped silicon layer 120 sidewalls of thickness is by etching off fully, and lifting source electrode 140 is still possessed clearance wall 160 with the sidewall of drain electrode 150, shown in Fig. 1-1,1-2.Then the two side of oxidation fin-shaped silicon layer 120 to be to form gate oxide 170, deposition one polycrystalline silicon-germanium layer (not icon, but be number in the figure body before) on silicon base 100 again, and insert in the slit 190 between two clearance walls 160.Then define this polycrystalline silicon-germanium layer to form grid 180.
Because above-mentioned FinFET manufacture method uses the little shadow manufacture method of electron beam to define fin-shaped silicon layer 120,, and prevented leakage current so the width of fin-shaped silicon layer 120 can be reduced to about 20nm--50nm.In addition, shown in Fig. 1-1 and 1-3, because the electric field that grid 180 is caused all can be responded in the two side of fin-shaped silicon layer 120, so the firing current of device (On-current) is bigger.Yet common methods reaches but has some problems with its made FinFET, outlines as follows.One must use silicon base in the common methods, and its price is higher.They are two years old, between the lifting source electrode that forms FinFET and drain electrode sidewall during the wall of crack, the spacer material (silicon nitride) of fin-shaped silicon layer sidewall is to cross the etching method removing, so fin-shaped silicon layer side-walls can produce defective, that is the surface nature of channel region can variation, and then influences the usefulness of device.Its three, for reducing lifting source electrode and the drain electrode that source electrode and drain resistance adopted of FinFET, the condition of its manufacture method also is not easy control.Its four because FinFET is a kind of device of vertical stratification, so planarization manufacture method thereafter is difficult for carrying out.Its five because the width of the fin-shaped silicon layer 120 of FinFET must be very narrow, reaching the purpose that reduces leakage current, so need to use the little shadow technology of electron beam that now also not can manufacture to define, and thereafter non-etc. also is not easy to control to the etching manufacture method.
Summary of the invention
The objective of the invention is to propose a kind of structure of mos field effect transistor, its leakage current is lower, and firing current is higher, and can avoid the problem of above-mentioned FinFET device simultaneously.
Another object of the present invention is the manufacture method that proposes a kind of mos field effect transistor, with the leakage current of minimizing device, and the firing current of increase device, and the problem that can avoid above-mentioned FinFET device and preparation method thereof to be caused simultaneously.
Mos field effect transistor proposed by the invention has semiconductor substrate, an insulating barrier, a clearance wall, a doping semiconductor layer, a gate dielectric layer, a grid, and an one source pole and a drain electrode.Wherein, a raceway groove is arranged at semiconductor-based the end, insulating barrier and clearance wall lay respectively at the bottom and the sidewall of raceway groove, and doping semiconductor layer is positioned at this raceway groove top, but the profile of this doping semiconductor layer is not contained this raceway groove fully.Gate dielectric layer is positioned at the surface of doping semiconductor layer, and grid is arranged in the top of raceway groove and raceway groove, and across gate dielectric layer that the doping semiconductor layer of raceway groove top is surrounded, this by gate loop around the doping semiconductor layer of part promptly as a channel region.This grid is separated by with aforementioned clearance wall and trench sidewalls, and is separated by with aforementioned insulating barrier and trench bottom.When this gate level ground during around doping semiconductor layer, promptly during the gate dielectric layer of the two and the semiconductor-based end surperficial parallel, this grid spy be called the horizontal circle grid (Horizontal Surround Gate, HSG).In addition, source/drain electrode is positioned at the both sides of grid.
The manufacture method step of mos field effect transistor of the present invention is as follows: at first form a raceway groove that fills up with insulating barrier in the semiconductor substrate, and after the top section of removing insulating barrier, sidewall at this raceway groove forms a clearance wall, fills up this raceway groove with a sacrifice layer afterwards.Then forming a doping semiconductor layer on the semiconductor-based end, for example is a doped crystal semiconductor layer, defines this doping semiconductor layer again to form a device region.This device region is covered in the sacrifice layer top, and exposes the sacrifice layer of part, and the device region of raceway groove top is as a channel region.Remove sacrifice layer with the isotropic etching method then, come out with lower surface with the device region above the raceway groove.Form a gate dielectric layer on the surface that device region exposes afterwards, on gate dielectric layer, form a conductive layer again, and insert in the raceway groove.Next define this conductive layer, be arranged in a grid of raceway groove and raceway groove top with formation, its sidewall with aforementioned clearance wall and raceway groove is separated by, and across gate dielectric layer that the device region above the raceway groove is surrounded.Then, form an one source pole and a drain electrode in the grid both sides.
In addition, in the manufacture method of the mos field effect transistor of the invention described above, source electrode also can form with ion implantation before doping semiconductor layer forms with drain electrode, and this moment, sacrifice layer and clearance wall promptly can be used to isolate source electrode and drain electrode.
Mos field effect transistor of the invention described above and manufacture method thereof can reduce the leakage current of device, increase firing current, its reason division is as follows: one, because the present invention can form very thin doping semiconductor layer with as channel region, so no longer include zone in the channel region, and be able to thoroughly eliminate leakage current away from the grid place away from grid.Its two because the gate loop in the mos field effect transistor of the present invention is around the channel region of raceway groove top, so the levels of channel region all can be subjected to the grid electric field effects, and the firing current of the device that is increased, and the minimizing leakage current.
And mos field effect transistor of the present invention and manufacture method thereof can be avoided the problem of above-mentioned FinFET device simultaneously, and its reason division is as follows.One, the present invention can form very thin doping semiconductor layer with as channel region, thus can replace silicon thin film, and needn't use higher-priced silicon base.Its two, the surface of doping semiconductor layer of the present invention, promptly the surface of its channel region is not subjected to the destruction of dry ecthing, so can not influence the usefulness of device.Its three, the doping way that source electrode of the present invention and drain electrode can be general forms, so its manufacture method condition is controlled easily.Its four because mos field effect transistor of the present invention is a kind of device (channel region surface parallel with substrate surface) of horizontal structure, so planarization manufacture method is thereafter carried out easily.Its five because the present invention decides the thickness of channel region with the formation thickness of doping semiconductor layer,, and do not have the unmanageable problem of anisotropic etching manufacture method so needn't use the required little shadow technology of electron beam of fin-shaped silicon layer of manufacturing the FinFET device.
In addition, can make source/drain region and the substrate of grid owing to be positioned at the clearance wall of trench sidewalls and grid, so the parasitic capacitance between the substrate of grid and source/drain region and raceway groove side is unlikely excessive away from the raceway groove side.Simultaneously, the insulating barrier that is positioned at trench bottom can make the substrate of grid away from the raceway groove below, so the parasitic capacitance between the substrate of grid and raceway groove below is also unlikely excessive.
Description of drawings
Fig. 1-1,1-2,1-3 are the structure of common Fin FET device, and wherein Fig. 1-2/1-3 is the profile of line of cut I-I '/II-II ' of Fig. 1-1;
Fig. 2--9 is the manufacturing process profile of the mos field effect transistor of preferred embodiment of the present invention;
Fig. 2-1,5-1,6-1,8-1 are respectively Fig. 2,5,6,8 vertical view, and Fig. 2,5,6,8 is respectively the profile of the line of cut III-III ' of Fig. 2-1,5-1,6-1,8-1;
Fig. 8-2 is the profile of the line of cut IV-IV ' of Fig. 8-1; And
Figure 10 is the variation of Fig. 8, the situation the when part that is arranged in raceway groove for grid is not filled up this raceway groove.
Among the figure:
100: silicon (silicon) substrate 105 is arranged: insulating barrier on the insulating barrier
110,130: curtain layer of hard hood 120: fin-shaped silicon layer (Fin Si-film)
140/150: lifting source/drain electrode (Raised S/D)
160: silicon nitride gap wall (SiN Spacer)
170: gate oxide 180: the slit between 190: two clearance walls 160 of grid
200: the semiconductor-based end 210,220: the shallow trench isolation of shallow trench isolation, device channel region
220a: raceway groove 221: clearance wall 222: sacrifice layer 226: slit
230,230a: non-crystalline semiconductor layer, crystalline semiconductor layer
233: the channel ion injects 230b: device region 240: gate dielectric layer
250,250a: conductive layer, horizontal circle grid 260: ion injects
261,262: source area, drain region 273: hole
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. is described in detail below:
Please refer to Fig. 2--9, be the manufacturing process profile of the mos field effect transistor of preferred embodiment of the present invention; And please refer to Fig. 2-1,5-1,6-1,8-1, and it is respectively Fig. 2,5,6,8 vertical view, and promptly Fig. 2,5,6,8 is respectively the profile of the line of cut III-III ' of Fig. 2-1,5-1,6-1,8-1.Fig. 8-2 is the profile of the line of cut IV-IV ' of Fig. 8-1 in addition.
Please refer to Fig. 2,2-1, the semiconductor-based end 200, at first be provided, it for example is a monolith-type (Bulky) silicon base, form shallow trench isolation 210 (the Shallow Trench Isolation of round more thereon, STI) and the shallow trench isolation 220 of device channel region (Channel Region), its material for example is with the formed silica of high density plasma CVD method (HDP-CVD).Then carry out little shadow and etching manufacture method, with the insulating barrier of shallow trench isolation 220 top section of removal devices channel region, and shallow trench isolation 210 medium and small partial insulating layer, and form a raceway groove 220a.The relative both sides of this raceway groove 220a extend in the shallow trench isolation 210 of round, and the degree of depth of this raceway groove 220a is between 0.05 μ m to 0.3 μ m.
Please refer to Fig. 3, sidewall at raceway groove 220a forms a clearance wall 221 then, its material for example is a silica, the formation method is to deposit the conformal silicon oxide layer of one deck earlier, this conformal silicon oxide layer of etching anisotropically again, wherein conformal silicon oxide layer for example uses Low Pressure Chemical Vapor Deposition (LPCVD) to form.Then fill up raceway groove 220a with a sacrifice layer (Sacrificial Layer) 222, the material of this sacrifice layer 222 and shallow trench isolation 210,220 and clearance wall 221 are different, for example are silicon nitrides.The method that forms this sacrifice layer 222 is exemplified below: at first use chemical vapour deposition technique (CVD) to form one deck expendable material on the semiconductor-based end 200, and fill up raceway groove 220a; Then use chemical mechanical milling method (Chemical Mechanical Polishing, CMP) expendable material except that dechannelling.Next, on the semiconductor-based end 200 and raceway groove 220a, form non-crystalline semiconductor layer 230, for example be-amorphous silicon layer.The formation method of this amorphous silicon layer for example is a Low Pressure Chemical Vapor Deposition (LPCVD), and its thickness is between between the 1nm to 50nm.
Please refer to Fig. 4, then carry out a solid phase epitaxy step (Solid Phase Epitaxy, SPE) so that non-crystalline semiconductor layer 230 becomes a crystalline semiconductor layer 230a; Because crystalline semiconductor layer 230a and substrate 200 belong to identical material, so the two is integrated among Fig. 4 herein.When non-crystalline semiconductor layer 230 was an amorphous silicon layer, the temperature of this solid phase epitaxy step was between 500 ℃ to 600 ℃, and the time of carrying out is between 1 hour to 6 hours.Next carry out a channel ion implantation step, come to inject ion 233 in crystalline semiconductor layer 230a, the part that wherein is positioned at the raceway groove top among the crystalline semiconductor layer 230a is promptly as channel region, and the implantation dosage of ion 233 is between 1 * 10
12/ cm
2To 6 * 10
13/ cm
2Between.So device is a NMOS, and then ion 233 is P type ion, for example is the boron ion; Otherwise then being N type ion, for example is phosphonium ion or arsenic ion.
In addition, desire forms above-mentioned doped crystal semiconductor layer 230a, also can adopt the method for original position (insitu), promptly when partly leading alms bowl layer 230, the deposited amorphous body mixes simultaneously, carry out the solid phase epitaxy step afterwards again, so that the non-crystalline semiconductor layer 230 that mixes becomes doped crystal semiconductor layer 230a.
Please refer to Fig. 5,5-1, then define crystalline semiconductor layer 230a, to form device region 230b.This device region 230b crosses over the mid portion of sacrifice layer 222, has so then crossed two slits 226 by clearance wall 221 with device region 230b, and it exposes the marginal portion of sacrifice layer 222.
Please refer to Fig. 6,6-1, Fig. 6 is the profile of the line of cut III-III ' of Fig. 6-1, but does not draw the gate dielectric layer of label 240 among Fig. 6-1.Shown in Fig. 6-1, then use isotropic etching method etching off sacrifice layer 222, make device region 230b soar aloft to cross in raceway groove 220a top, wherein etchant passes two slits 226 and removes sacrifice layer 222 fully, and etchant is extremely low to the etch-rate of shallow trench isolation 210 and clearance wall 221.Above-mentioned isotropic etching rule is wet etch method in this way, and when the material of sacrifice layer 222 was silicon nitride, its etchant was hot phosphoric acid (phosphoricacid).Then, as shown in Figure 6, on the surface that raceway groove 220a and device region 230b expose, form gate dielectric layer 240, for example be a gate oxide or a silicon nitride oxide layer (nitrified gateoxide layer), wherein the formation method of gate oxide can be thermal oxidation method (ThermalOxidation), and the silicon nitride oxide layer is then carried out nitrogenize again and got after gate oxide forms.
Please refer to Fig. 7, then on the semiconductor-based end 200, form a conductive layer 250, and fill up raceway groove 220a, the material of this conductive layer 250 can be polysilicon,, polysilicon-germanium, metal silicide, or metal, its formation method can be Low Pressure Chemical Vapor Deposition (LPCVD).
Please refer to Fig. 8-8-2, Fig. 8 is the profile of the line of cut III-III ' of Fig. 8-1, and Fig. 8-2 is the profile of the line of cut IV-IV ' of Fig. 8-1, but does not draw gate dielectric layer 240 among Fig. 8-1.Shown in Fig. 8-8-2, follow patterned conductive layer 250, to form grid 250a, it is arranged in raceway groove 220a and raceway groove 220a top, and and be separated by with clearance wall 221 between the raceway groove 220a sidewall, and the device region 230b above gate dielectric layer 240 horizontal circle raceway groove 220a, and the device region 230b of this part is promptly as a channel region.
Please refer to Fig. 9, serves as that the cover curtain carries out ion injection 260 with grid 250a then, to form source area 261 and drain region 262 in the semiconductor-based end 200 of grid 250a both sides.But, the method that forms source area 261 and drain region 262 is not limited to ion implantation, other doping method also can, for example be the diffusion type doping method.
In addition, please refer to Figure 10, and while comparison chart 7,8.As shown in figure 10, because as long as on the gate dielectric layer 240 of device region 230b lower surface, form conductive layer 250 and gate pole 250a, can cause counter-rotating (Inversion) in device region 230b lower floor, so conductive layer 250 does not fill up raceway groove 220a, also can and in raceway groove 220a, form hole 273, like this then the part of grid 250a position in raceway groove 220a is a hollow bulk, but not original solid bulk.
In addition, please refer to Fig. 3--5, source/drain region also can use ion implantation to form before amorphism semiconductor layer 230 forms, and this moment, expendable material 222 can be separated source area and drain region with clearance wall 221.
The mos field effect transistor of preferred embodiment of the present invention and manufacture method thereof, can reduce the leakage current of device, increase firing current, its reason division is as follows: one, because the present invention can form very thin doping semiconductor layer as channel region, so channel region no longer includes the zone away from grid, and be able to thoroughly eliminate leakage current away from the grid place.
Its two because the gate level in the mos field effect transistor of the present invention is around the channel region of raceway groove top, so the levels of channel region all can be subjected to the grid electric field effects, and the firing current of the device that is increased, and the minimizing leakage current.
In addition, the metal oxide semiconductcor field effect of preferred embodiment of the present invention also can be avoided simultaneously the problem of common FinFET device to transistor and manufacture method thereof, and its reason division is as follows.One, the present invention can use very thin doped crystal semiconductor layer, for example is that silicon epitaxial layers is used as channel region, thus can replace silicon thin film, and needn't use higher-priced silicon base, manufacturing cost is minimized.
Its two, different with the fin-shaped silicon layer 120 (Fig. 1-1 and 1-3) of common FinFET device is because the surface of doped crystal semiconductor layer of the present invention, promptly the surface of its channel region is not subjected to the destruction of dry ecthing, so can not influence the usefulness of device.
Its three, the doping way that source electrode of the present invention and drain electrode can be general forms, and must adopt the technology of lifting source/drain electrode to form as common FinFET device, so manufacture method condition of the present invention is easier to control.
Its four because mos field effect transistor of the present invention is a kind of device (channel region surface parallel with substrate surface) of horizontal structure, so planarization manufacture method thereafter is easier to carry out.
Its five because the present invention decides the thickness of channel region with the formation thickness of doped crystal semiconductor layer,, and do not have the unmanageable problem of anisotropic etching manufacture method so needn't use the required little shadow technology of electron beam of fin-shaped silicon layer of manufacturing the FinFET device.
In addition, please refer to Fig. 9, clearance wall 221 between raceway groove 220a sidewall and grid 250a can make the source/drain region 261/262 and substrate 200 of grid 250a away from raceway groove 220a side, so the parasitic capacitance between the substrate 200 of grid 250a and source/drain region 261/262 and raceway groove 220a side is unlikely too high.Simultaneously, the insulating barrier 220 that is positioned at raceway groove 220a bottom can make the substrate 200 of grid 250a away from insulating barrier 220 belows, so the parasitic capacitance between the substrate 200 of grid 250a and insulating barrier 220 belows is also unlikely excessive.
Though the present invention with a preferred embodiment openly as above; right its is not in order to qualification the present invention, any those of ordinary skill in the art, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking claim.
Claims (17)
1. mos field effect transistor is characterized in that it comprises:
The semiconductor substrate has a raceway groove on it;
One insulating barrier, it is positioned at the bottom of described raceway groove;
One clearance wall, it is positioned at the sidewall on described raceway groove four limits;
One doping semiconductor layer, it is positioned at described raceway groove top, but the profile of described doping semiconductor layer does not cover described raceway groove fully;
One gate dielectric layer, it is positioned at the surface of described doping semiconductor layer;
One grid, it is positioned at described raceway groove and described raceway groove top, and across described gate dielectric layer around described doping semiconductor layer, and be separated by with described clearance wall between described grid and the described trench sidewalls;
An one source pole and a drain electrode, it is positioned at described grid both sides.
2. mos field effect transistor as claimed in claim 1, it is characterized in that, described gate level ground is around described doping semiconductor layer, and the described gate dielectric layer between promptly described grid and the described doping semiconductor layer is surperficial parallel with the described semiconductor-based end.
3. mos field effect transistor as claimed in claim 1 is characterized in that the thickness of described doping semiconductor layer is between between the 1nm to 50nm.
4. mos field effect transistor as claimed in claim 1, it is characterized in that, also has an isolated area at described the semiconductor-based end, and described raceway groove has four limits, wherein one group of relative both sides lays respectively at described source electrode and drain side, and other one group of relative both sides extend in the described isolated area.
5. mos field effect transistor as claimed in claim 4 is characterized in that, described isolated area is surrounded by described raceway groove, described source electrode and the described drain electrode zone that the three formed.
6. mos field effect transistor as claimed in claim 1 is characterized in that described doping semiconductor layer is crossed over the mid portion of described raceway groove, and does not cover two marginal portions of described raceway groove.
7. mos field effect transistor as claimed in claim 1 is characterized in that, the distance between a upper surface of described insulating barrier and a lower surface of described doping semiconductor layer is between 0.05 μ m to 0.3 μ m.
8. the manufacture method of a mos field effect transistor is characterized in that, comprises the following steps:
The semiconductor substrate is provided;
Form a raceway groove on the described semiconductor-based end, described raceway groove fills up with an insulating barrier;
Remove the top section of described insulating barrier;
Sidewall on described raceway groove four limits forms a clearance wall;
Fill up described raceway groove with a sacrifice layer;
On the described semiconductor-based end and described sacrifice layer, cover a doping semiconductor layer;
Define described doping semiconductor layer to form a device region, described device region is covered in described sacrifice layer top, and exposes the described sacrifice layer of part;
Remove described sacrifice layer;
Form a gate dielectric layer on the surface of described device region;
On described gate dielectric layer, form a conductive layer, and insert in the described raceway groove;
Define described conductive layer, be arranged in described raceway groove and described raceway groove top with formation, and across the grid of described gate dielectric layer around described device region; And
Form an one source pole and a drain electrode in described grid both sides.
9. the manufacture method of mos field effect transistor as claimed in claim 8, it is characterized in that, described gate level ground is around described doping semiconductor layer, and the described gate dielectric layer between promptly described grid and the described doping semiconductor layer is surperficial parallel with the described semiconductor-based end.
10. the manufacture method of mos field effect transistor as claimed in claim 8 is characterized in that, the method for filling up described raceway groove with described sacrifice layer comprises the following steps:
Deposition one expendable material on the described semiconductor-based end, and fill up described raceway groove; And
Remove described raceway groove described expendable material in addition.
11. the manufacture method of mos field effect transistor as claimed in claim 8 is characterized in that, described doping semiconductor layer comprises a doped crystal semiconductor layer.
12. the manufacture method of mos field effect transistor as claimed in claim 11 is characterized in that, the formation method of described doped crystal semiconductor layer comprises the following steps:
In the mode of original position, promptly the mode with deposition and doping simultaneously forms a doping non-crystalline semiconductor layer on the described semiconductor-based end; And
Carry out a solid phase epitaxy step, so that described doping non-crystalline semiconductor layer becomes described doped crystal semiconductor layer.
13. the manufacture method of mos field effect transistor as claimed in claim 11 is characterized in that, the formation method of described doped crystal semiconductor layer comprises the following steps:
On the described semiconductor-based end and described sacrifice layer, form a non-crystalline semiconductor layer;
Carry out a solid phase epitaxy step, so that described non-crystalline semiconductor layer becomes a crystalline semiconductor layer; And
In described crystalline semiconductor layer, mix.
14. the manufacture method of mos field effect transistor as claimed in claim 11 is characterized in that, the semi-conductive thickness of described doped crystal is between between the 1nm to 50nm.
15. the manufacture method of mos field effect transistor as claimed in claim 8, it is characterized in that, be formed with an isolated area at described the semiconductor-based end, and described raceway groove has four limits, wherein one group of relative both sides lays respectively at described source electrode and drain side, and other one group of relative both sides extend in the described isolated area.
16. the manufacture method of mos field effect transistor as claimed in claim 15 is characterized in that, described isolated area is surrounded by described raceway groove, described source electrode and the described drain electrode zone that the three formed.
17. the manufacture method of mos field effect transistor as claimed in claim 8 is characterized in that, described device region is crossed over the mid portion of described sacrifice layer, and exposes two marginal portions of described sacrifice layer.
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|---|---|---|---|
| CN 02118191 CN1225799C (en) | 2002-04-24 | 2002-04-24 | MOSFET and its manufacture |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02118191 CN1225799C (en) | 2002-04-24 | 2002-04-24 | MOSFET and its manufacture |
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| CN1225799C true CN1225799C (en) | 2005-11-02 |
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| CN111863949A (en) * | 2019-04-30 | 2020-10-30 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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