CN100369207C - Preparation method of replacement gate - Google Patents
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- CN100369207C CN100369207C CNB2005100115063A CN200510011506A CN100369207C CN 100369207 C CN100369207 C CN 100369207C CN B2005100115063 A CNB2005100115063 A CN B2005100115063A CN 200510011506 A CN200510011506 A CN 200510011506A CN 100369207 C CN100369207 C CN 100369207C
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- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 33
- 230000003647 oxidation Effects 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 239000011521 glass Substances 0.000 claims description 22
- 239000011248 coating agent Substances 0.000 claims description 19
- 238000000576 coating method Methods 0.000 claims description 19
- 238000001020 plasma etching Methods 0.000 claims description 17
- 238000004151 rapid thermal annealing Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 239000010941 cobalt Substances 0.000 claims description 12
- 229910017052 cobalt Inorganic materials 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 10
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 239000003870 refractory metal Substances 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000010792 warming Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000010992 reflux Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 238000011010 flushing procedure Methods 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 239000008367 deionised water Substances 0.000 claims description 3
- 239000000243 solution Substances 0.000 claims description 3
- 150000003609 titanium compounds Chemical class 0.000 claims description 3
- 239000000428 dust Substances 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000013021 overheating Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 230000035515 penetration Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- -1 hydrogen fluorine ester Chemical class 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Abstract
The invention belongs to a method for preparing a semiconductor device with ultra-deep submicron and following characteristic dimensions, and particularly relates to a replacement gate preparation technology for manufacturing an ultra-deep submicron metal gate CMOS. By using metal as the gate electrode, the gate depletion effect and boron penetration phenomenon can be fundamentally eliminated, and simultaneously, very low gate electrode sheet resistance can be obtained. The invention realizes a novel metal gate CMOS technology by adopting an embedded metal gate CMOS technology (namely, a replacement gate preparation technology). In the embedded metal gate CMOS process, one of the main key technologies is a set of replacement gate preparation technology, which comprises selection of replacement gate materials, formation of fine replacement gate patterns, planarization and removal of replacement gates.
Description
Technical field
The invention belongs to sub-micro and following characteristic size semiconductor device technology, relate to a kind of preparation method of alternative gate, relate to particularly and be used for a kind of alternative gate preparation method that sub-micro metal gate CMOS (CMOS (Complementary Metal Oxide Semiconductor)) makes.
Technical background
When narrowing down to inferior 0.1 μ m and gate oxide thickness, polysilicon gate cmos device grid length is thinned to 2.5nm when following, the barrier that polysilicon gate depletion effect, serious day by day boron penetration effects and too high gate resistance have become further raising cmos device performance, make the doped polysilicon gate that dominates at microelectronics technology for a long time face great challenge, emerging refractory metal bar (metal gate) then becomes present most promising substitute technology.Make gate electrode with metal, can fundamentally eliminate grid depletion effect and B penetration effect, obtain low-down gate electrode sheet resistance simultaneously.
Summary of the invention
The object of the present invention is to provide a kind of alternative gate preparation method.
For achieving the above object, the present invention adopts embedded metal gate CMOS technology (being alternative gate preparation technology) to realize a kind of metal gate CMOS technology of novelty.Of the present invention successfully is the key and one of basis of the Si technology sustainable development of ULSI from now on, has broad application prospects.
Preparation process of the present invention comprises:
1) after carrying out local oxide isolation or shallow-trench isolation and tuned grid injection, carries out alternative gate oxidation: N
2Protect following 600 ℃ to advance boat, be warming up to 750-870 ℃, N
2Constant temperature 10 minutes; Under the same temperature, N
2/ O
2=5: 1 ambient oxidation, oxidization time 60-120 minute; Then 750-870 ℃, N
2Annealed 20-60 minute; Last N
2Be cooled to 600 ℃ under the protection, go out boat;
2) cvd silicon nitride: temperature 760-820 ℃, pressure 250-300 milli torr, SiH
2Cl
225-35sccm, NH
380-100sccm, film thickness 220-260nm;
3) reactive ion etching forms silicon nitride alternative gate electrode: power 130-200W, etchant gas CHF
35-10sccm, SF
620-40sccm, He 100sccm mixes, pressure 300-500 millitorr;
Tetraethoxysilane thermal decomposition TEOS SiO then
2-1 film: temperature 720-760 ℃, thickness 90-150nm;
4) reactive ion etching TEOS SiO
2-1, form side wall-1: pressure 200-250m τ, RF (radio frequency) power 250-350W, CHF
3/ CF
4/ Ar=40-60sccm/5-16sccm/200-300sccm, no over etching, soft etching 5-10 second;
5) source/drain extension region low energy is injected: PMOS:
47BF
2, energy 5-8Kev, dosage 3-6 * 10
14Cm
-2NMOS:
75As, energy 5-8Kev, dosage 3-6 * 10
14Cm
-2
6) tetraethoxysilane thermal decomposition SiO
2-2: temperature 710-750 ℃, thickness 200-260nm;
Reactive ion etching SiO then
2-2, form side wall-2: pressure 200-250m τ, RF power 250-350W, CHF
3/ CF
4/ Ar=40-60sccm/5-16sccm/200-300sccm;
7) source/leakage is injected and rapid thermal annealing: PMOS:
47BF
2, energy 25-35Kev, dosage 1.5-3 * 10
15Cm
-2NMOS:
75As, energy 40-55Kev, dosage 2-4 * 10
15Cm
-21000-1020 ℃ of rapid thermal annealing temperature, time 4-8 second, formation source/drain junction;
8) source/drain region cobalt silicide forms: the sputter of cobalt/titanium compound film, spatter titanium film 4-7nm earlier, and spatter cobalt film 9-15nm again; Sputtering power is 700-900W all, and spattering the titanium operating pressure is 4-6 * 10
-3Torr, spattering cobalt is 5-7 * 10
-3Torr;
Twice rapid thermal annealing adds and carry out selective etching therebetween then: for the first time the rapid thermal annealing temperature is 630-670 ℃, time 15-30 second; 870-910 ℃ of rapid thermal annealing temperature for the second time after the selective etching, time 6-12 branch;
9) chemical vapor deposition cryogenic oxidation silicon and boron-phosphorosilicate glass: first chemical vapor deposition cryogenic oxidation silicon: temperature 350-450 ℃, film thickness 200-250nm; Chemical vapor deposition boron-phosphorosilicate glass: temperature 350-450 ℃ then, film thickness 700-800nm;
10) boron-phosphorosilicate glass refluxes: 750-800 ℃, and N
2, time 20-30 minute;
11) SOG (spin-on-glass promptly is coated with one deck solvent on substrate) coating for the first time and heat treatment: the coating condition is a room temperature, thickness 360-400nm; Heat-treat condition: 350-420 ℃, N
2, 30-50 minute;
12) return the SOG:RF power 150-250W that carves the coating first time, pressure 250-350 milli torr, CF
420-30sccm, CHF
340-60sccm, O
22sccm, Ar250-350sccm;
13) SOG coating for the second time and heat treatment: condition is with 11 steps;
14) return and carve the SOG of coating for the second time, return quarter with following condition earlier, i.e. RF power 150-250W, pressure 200-260 is torr in the least, CF
420-32sccm, CHF
318-30sccm, Ar 250-350sccm; When the SOG that applies when the second time returns and carved, return quarter with following condition again, i.e. CF
415-25sccm, Ar 200-250sccm, RF power 250-350W, pressure 180-220 milli torr all exposes until alternative gate;
15) corrosion grid groove, the clean silicon nitride alternative gate of wet etching: H
3PO
4, 160-170 ℃, the grid groove forms;
16) float alternative gate silica: HF: H
2O=1: 20 rinse the alternative gate silica;
17) clean: H
2SO
4: H
2O
2=5: 1,120 ℃, cleaned 10 fens, use NH then
4OH: H
2O
2: H
2O=0.8: 1: 5,60 ℃, cleaned 5 fens, use HF/IPA solution (HF: isopropyl alcohol (IPA): H again
2O=0.5%: 0.02: 1), soaked 1-10 minute under the room temperature, the water flushing dries stove;
18) gate oxidation: N
2Protect following 600 ℃ to advance boat, be warming up to 750-850 ℃, N
2Constant temperature 10 minutes; Under the same temperature, N
2/ O
2=5: 1 ambient oxidation, oxidization time 10-50 minute; N
2Atmosphere, 750-850 ℃ of annealing, 15-60 minute; N
2Be cooled to 600 ℃, N under the protection
2Boat is pulled out in protection down slowly;
19) sputtering refractory metals, W/TiN=100-150nm/30-45nm, and reactive ion etching forms metal gate electrode.
Wherein the oxide thickness of the carrying out local oxide isolation in the step 1 is 350-420nm, and the oxide thickness of alternative gate oxidation is 5-7nm.
Wherein the flushing of the water in the step 17 is a washed with de-ionized water.
Wherein step 18 gate oxide film thickness is the 15-35 dust.
Wherein the order of sputtering refractory metals is first sputtered with Ti N film in the step 19, back sputter W film.
Wherein the thickness after Overheating Treatment is 300-360nm in the step 11.
Wherein the etch rate of boron-phosphorosilicate glass is 2 times of SOG of coating for the first time in the step 12.
Wherein return in the step 14 and carve the SOG of coating for the second time, return quarter with the boron-phosphorosilicate glass condition identical with the SOG etch rate of coating for the second time earlier, second step was returned quarter with the boron-phosphorosilicate glass condition identical with the low-temperature oxidation silicon etch rate again.
Characteristics of the present invention are:
1, source/leakage (S/D) forms earlier, forms behind the grid.Having avoided metal gate reactive ion etching (RIE) and source/leakage to inject draws. and play damage, avoided the damage of high-temperature thermal annealing metal gate to gate medium;
2, developed planarization with the conventional cmos process compatible, utilized the BPSG hot reflux to add the BPSG/SOG-1 speed difference and eat-back and add SOG-2/ low temperature SiO2 constant speed and return to carve to expose and end, realized good planarization to false grid;
3, the formation technology of the removal of alternative gate electrode and groove;
4, the lithographic technique of tungsten/titanium nitride (W/TiN) composition metal grid adopts two step RIE etchings, optimizes experimental parameter, has reached satisfied effect.
Description of drawings
Fig. 1 is the structural representation of alternative gate of the present invention.Wherein: Fig. 1 a is the section of structure after silicide forms, symbol 1-alternative gate Si
3N
4, 2-side wall, 6-field silica, 15-CoSi
2Fig. 1 b is that false grid are removed schematic diagram after the planarization, symbol 1-alternative gate Si
3N
44-alternative gate silica, 16-grid groove; Fig. 1 c is reactive ion etching W/TiN lamination metal grid, forms T shape gate electrode, symbol 11-W, 12-TiN, 13-gate oxidation silicon.
Fig. 2 is alternative gate preparation method's of the present invention schematic flow sheet.Wherein: symbol 1-alternative gate Si
3N
42-side wall-1; 3-side wall-2; 4-alternative gate silica; 5-source/drain extension region; 6-field silica; 7-SOG-1; 8-BPSG; 9-LTO SiO
210-SOG-2; 11-Wi; 12-TiN; 13-gate oxidation silicon; 14-PE SiO
2
Embodiment
In embedded metal gate CMOS technology of the present invention, one of main key is the technology of preparing of a cover alternative gate, and it comprises choosing of alternative gate material, the shaping of meticulous alternative gate figure, the removal of planarization and false grid.In this process, point of the present invention is:
1. chosen silicon nitride as an alternative grid material replace common polysilicon gate material, alternative gate can be removed with wet etching after the planarization like this.Select ratio because the wet etching silicon nitride has than higher corrosion silica, therefore can not cause especially plasma damage of chemistry, and adopt the reactive ion etching silicon nitride can obtain the steep gate figure of meticulousr section the silicon under it.
2. in the research of refractory metal bar, generally adopt chemico-mechanical polishing (CMP) technology to finish planarization in the world.We are off the beaten track, first stand-alone development a kind of and traditional more compatible planarization of CMOS technology, utilize BPSG (boron-phosphorosilicate glass) hot reflux to add BPSG/SOG (rotary coating glass)-1 speed difference and eat-back and add SOG-2/ low temperature SiO
2Constant speed is returned and is only carved extremely false grid exposure, has realized good planarization.Saved the expensive cost of configuration CMP main equipment.Simultaneously cleaner, compatible better.
Embodiment
Alternative gate structure of the present invention is referring to Fig. 1.
The preparation flow of alternative gate of the present invention is referring to Fig. 2.
The step that the present invention prepares alternative gate is:
1) LOCOS (selective oxidation) isolates or STI (shallow slot) isolation, and an oxide thickness 380nm sees " 6 " and Fig. 1 (a) " 6 " of Fig. 2 (1);
2) tuned grid injects;
3) alternative gate oxidation is seen Fig. 2 (1) " 4 ": big flow N
2Protect following 600 ℃ to advance boat, be warming up to 830 ℃ then, N
2Constant temperature 10 minutes; Under the same temperature, N
2/ O
2=5: 1 ambient oxidation, oxidization time 85 minutes; N
2Atmosphere, 830 ℃ of annealing, 30 minutes; N
2Be cooled to 600 ℃ under the protection, again at big flow N
2Boat is pulled out in protection down slowly;
4) chemical vapor deposition (LPCVD) silicon nitride: 790 ℃ of temperature, pressure 275 milli torrs, SiH
2Cl
229sccm, NH
390sccm, film thickness 240nm;
5) reactive ion etching forms silicon nitride alternative gate electrode, sees " 1 " and Fig. 1 of Fig. 2 (1)
(a) " 1 ": power 150W, etchant gas CHF
37sccm, SF
630sccm, He 100sccm mixes, air pressure 400 milli torrs; Tetraethoxysilane thermal decomposition SiO then
2-1 (TEOS-1) film: 740 ℃ of temperature, thickness 120nm;
6) reactive ion etching TEOS0-1 forms side wall-1, sees " 2 " of Fig. 2 (1) and " 2 " of Fig. 1 (a): pressure 200 milli torrs, RF power 300W, CHF
3/ CF
4/ Ar=50sccm/10sccm/250sccm, no over etching, soft etching 7 seconds;
7) source/drain extension region low energy is injected, and sees " 5 " of Fig. 2 (1): PMOS:
47BF
2, energy 7Kcv, dosage 4 * 10
14Cm
-2NMOS:
75As, energy 5Kev, dosage 5 * 10
14Cm
-2
8) tetraethoxysilane thermal decomposition SiO
2-2 (TEOS-2): 740 ℃ of temperature, thickness 220nm; Reactive ion etching TEOS-2 then: pressure 200 milli torrs, RF power 300W, CHF
3/ CF
4/ Ar=50sccm/10scc/250sccm, no over etching, soft etching 7 seconds; Form side wall-2, see " 3 " and Fig. 1 (a) " 3 " of Fig. 2 (1);
9) source/leakage is injected and rapid thermal annealing (RTA): PMOS:
47BF
2, energy 25Kev, dosage 3 * 10
15Cm
-2NMOS:
75As, energy 50Kev, dosage 4 * 10
15Cm
-21010 ℃ of RTA temperature, 5 seconds time, formation source/drain junction;
10) source/drain region cobalt silicide forms, and sees shown in Fig. 1 (a) " 15 ": the sputter of cobalt/titanium compound film, spatter titanium film 5nm earlier, and spatter cobalt film 11nm again; Sputtering power is 800W all, and the operating pressure of spattering titanium is 5 * 10
-3Torr, spattering cobalt is 6.2 * 10
-3Torr; Twice rapid thermal annealing adds and carries out selective etching therebetween: rapid thermal annealing for the first time: 650 ℃ of temperature, 20 seconds time; Rapid thermal annealing for the second time after the selective etching: 900 ℃ of temperature, 7 minutes time; Finish device profile behind the silicide process shown in Fig. 2 (1);
11) chemical vapor deposition cryogenic oxidation silicon (LTO) and boron-phosphorosilicate glass (BPSG) are seen " 9 " and " 8 " of Fig. 2 (2): chemical vapor deposition LTO: 400 ℃ of temperature, film thickness 200-250nm; Chemical vapor deposition boron-phosphorosilicate glass then, 400 ℃ of temperature, film thickness 700-800nm;
12) boron-phosphorosilicate glass refluxes: 750 ℃, and N
2, 20 minutes time;
13) SOG applies and heat treatment for the first time, sees " 7 " of Fig. 2 (2): room temperature, and thickness 360-400nm, this moment, the SOG that fill the lowest point of figure was much thicker than the SOG of the covering on step top owing to the flowability of SOG, made the shoulder height reduction; Heat treatment: 400 ℃, N
2, 40 minutes; After the heat treatment, thickness drops to 300-360nm;
14) return the SOG:RF power 200W that carves the coating first time, pressure 300 milli torrs, CF
425sccm, CHF
350sccm, O
22sccm, Ar 300sccm, above-mentioned time quarter condition little, the boron-phosphorosilicate glass etch rate is 2 times of SOG of coating for the first time, therefore can effectively reduce the step of figure, and this moment, the SOG of the lowest point was corroded only, stay part of boron phosphorosilicate glass and cryogenic oxidation silicon, see " 8 " and " 9 " of Fig. 2 (3);
15) SOG applies and heat treatment for the second time, and see " 10 " of Fig. 2 (4): condition is with step 13.Further reduced shoulder height;
16) return and carve SOG-2, return quarter with boron-phosphorosilicate glass with the identical condition of the SOG etch rate second time earlier, i.e. RF power 200W, pressure 230 is torrs in the least, CF
426sccm, CHF
324sccm, Ar 300sccm; SOG returns when having carved when the second time, returns quarter with the boron-phosphorosilicate glass condition identical with the low-temperature oxidation silicon etch rate again, i.e. RF power 300W, pressure 200 milli torrs, CF
419sccm, Ar 250sccm; All expose until alternative gate, see Fig. 2 (5);
17) corrosion grid groove is seen Fig. 2 (6), and the clean silicon nitride alternative gate of first wet etching is seen Fig. 1 (b) " 1 ": H
3PO
4, 160 ℃, the grid groove forms;
18) float the alternative gate silica again, see Fig. 2 (6) and Fig. 1 (b) " 4 ": HF: H
2O=1: 20 rinse the alternative gate silica, shown in Fig. 2 (6);
19) clean: 3# (H
2SO
4: H
2O
2=5: 1)-1# (NH
4OH: H
2O
2: H
2O=0.8: 1: 5)-again the solution with hydrogen fluorine ester/isopropanol=0.5%/0.02%/1 at room temperature soaked 5 minutes, and deionized water rinsing dries and advances stove immediately;
20) gate oxidation is seen " 13 " and Fig. 1 (c) " 13 " of Fig. 2 (7): big flow N
2Protect following 600 ℃ to advance boat, push away slowly, big flow N
2Protection; Be warming up to 830 ℃, N
2Constant temperature 10 minutes; Under the same temperature, N
2/ O
2=5: 1 ambient oxidation, oxidization time 20 minutes; N
2Atmosphere, 830 ℃ of annealing, 30 minutes; N
2Be cooled to 600 ℃ under the protection, again at big flow N
2Boat is pulled out in protection down slowly; Gate oxidation thickness 25 dusts;
21) sputtering refractory metals W/TiN, see " 11 "/" 12 " of Fig. 2 (7): (W/TiN=100nm/35nm), and reactive ion etching forms metal gate electrode, sees " 11 "/" 12 " and Fig. 1 (c) " 11 " and " 12 " of Fig. 2 (8).Cover plasma-reinforced chemical vapor deposition silica (PE SiO then
2), see Fig. 2 (8) " 14 ".
Claims (8)
1. the preparation method of an alternative gate may further comprise the steps:
1) after carrying out local oxide isolation or shallow-trench isolation and tuned grid injection, carries out alternative gate oxidation: N
2Protect following 600 ℃ to advance boat, be warming up to 750-870 ℃, N
2Constant temperature 10 minutes; Under the same temperature, N
2/ O
2=5: 1 ambient oxidation, oxidization time 60-120 minute; Then 750-870 ℃, N
2Annealed 20-60 minute; Last N
2Be cooled to 600 ℃ under the protection, go out boat;
2) cvd silicon nitride: temperature 760-820 ℃, pressure 250-300 milli torr, SiH
2Cl
225-35sccm, NH
380-100sccm, film thickness 220-260nm;
3) reactive ion etching forms silicon nitride alternative gate electrode: power 130-200W, etchant gas CHF
35-10sccm, SF
620-40sccm, He 100sccm mixes, pressure 300-500 milli torr;
Tetraethoxysilane thermal decomposition TEOS SiO then
2-1 film: temperature 720-760 ℃, thickness 90-150nm;
4) reactive ion etching TEOS SiO
2-1, form side wall-1: pressure 200-250m τ, radio-frequency power 250-350W, CHF
3/ CF
4/ Ar=40-60sccm/5-16sccm/200-300sccm, no over etching, soft etching 5-10 second;
5) source/drain extension region low energy is injected: PMOS:
47BF
2, energy 5-8Kev, dosage 3-6 * 10
14Cm
-2NMOS:
75As, energy 5-8Kev, dosage 3-6 * 10
14Cm
-2
6) tetraethoxysilane thermal decomposition SiO
2-2: temperature 710-750 ℃, thickness 200-260nm;
Reactive ion etching SiO then
2-2, form side wall-2: pressure 200-250m τ, RF power 250-350W, CHF
3/ CF
4/ Ar=40-60sccm/5-16sccm/200-300sccm;
7) source/leakage is injected and rapid thermal annealing: PMOS:
47BF
2, energy 25-35Kev, dosage 1.5-3 * 10
15Cm
-2NMOS:
75As, energy 40-55Kev, dosage 2-4 * 10
15Cm
-21000-1020 ℃ of rapid thermal annealing temperature, time 4-8 second, formation source/drain junction;
8) source/drain region cobalt silicide forms: the sputter of cobalt/titanium compound film, spatter titanium film 4-7nm earlier, and spatter cobalt film 9-15nm again; Sputtering power is 700-900W all, and spattering the titanium operating pressure is 4-6 * 10
-3Torr, spattering cobalt is 5-7 * 10
-3Torr;
Twice rapid thermal annealing adds and carry out selective etching therebetween then: for the first time the rapid thermal annealing temperature is 630-670 ℃, time 15-30 second; 870-910 ℃ of rapid thermal annealing temperature for the second time after the selective etching, time 6-12 second;
9) chemical vapor deposition cryogenic oxidation silicon and boron-phosphorosilicate glass: first chemical vapor deposition cryogenic oxidation silicon: temperature 350-450 ℃, film thickness 200-250nm; Chemical vapor deposition boron-phosphorosilicate glass: temperature 350-450 ℃ then, film thickness 700-800nm;
10) boron-phosphorosilicate glass refluxes: 750-800 ℃, and N
2, time 20-30 minute;
11) SOG coating for the first time and heat treatment: the coating condition is a room temperature, thickness 360-400nm; Heat-treat condition: 350-420 ℃, N
2, 30-50 minute;
12) return the SOG:RF power 150-250W that carves the coating first time, pressure 250-350 milli torr, CF
420-30sccm, CHF
340-60sccm, O
22sccm, Ar 250-350sccm;
13) SOG coating for the second time and heat treatment: condition is with 11 steps;
14) return and carve the SOG of coating for the second time, return quarter with following condition earlier, i.e. RF power 150-250W, pressure 200-260 is torr in the least, CF
420-32sccm, CHF
318-30sccm when the SOG that Ar 250-350sccm applied when the second time returns and carved, returns quarter with following condition, i.e. CF again
415-25sccm, Ar 200-250sccm, RF power 250-350W, pressure 180-220 milli torr all exposes until alternative gate;
15) corrosion grid groove, the clean silicon nitride alternative gate of wet etching: H
3PO
4, 160-170 ℃, the grid groove forms;
16) float alternative gate silica: HF: H
2O=1: 20 rinse the alternative gate silica;
17) clean: H
2SO
4: H
2O
2=5: 1,120 ℃, cleaned 10 fens, use NH then
4OH: H
2O
2: H
2O=0.8: 1: 5 solution, 60 ℃, cleaned 5 fens, use HF again: isopropyl alcohol: H
2O=0.5%: 0.02%: 1, to soak 1-10 minute under the room temperature, the water flushing dries stove;
18) gate oxidation: N
2Protect following 600 ℃ to advance boat, be warming up to 750-850 ℃, N
2Constant temperature 10 minutes; Under the same temperature, N
2/ O
2=5: 1 ambient oxidation, oxidization time 10-50 minute; N
2Atmosphere, 750-850 ℃ of annealing, 15-60 minute; N
2Be cooled to 600 ℃, N under the protection
2Boat is pulled out in protection down slowly;
19) sputtering refractory metals, W/TiN=100-150nm/30-45nm, and reactive ion etching forms metal gate electrode.
2. according to claim 1, it is characterized in that the oxide thickness of the carrying out local oxide isolation in the step 1 is 350-420nm, the oxide thickness of alternative gate oxidation is 5-7nm.
3. according to the preparation method of claim 1, it is characterized in that the water flushing in the step 17 is a washed with de-ionized water.
4. according to the preparation method of claim 1, it is characterized in that step 18 gate oxide film thickness is the 15-35 dust.
5. according to the preparation method of claim 1, it is characterized in that the order of sputtering refractory metals is first sputtered with Ti N film in the step 19, back sputter W film.
6. according to the preparation method of claim 1, it is characterized in that the thickness in the step 11 after Overheating Treatment is 300-360nm.
7. according to the preparation method of claim 1, it is characterized in that in the step 12, the etch rate of boron-phosphorosilicate glass is 2 times of SOG of coating for the first time.
8. according to the preparation method of claim 1, it is characterized in that, in the step 14, return and carve the SOG of coating for the second time, return quarter with the boron-phosphorosilicate glass condition identical with the SOG etch rate of coating for the second time earlier, second step was returned quarter with the boron-phosphorosilicate glass condition identical with the low-temperature oxidation silicon etch rate again.
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| CN101728257B (en) * | 2008-10-24 | 2011-02-16 | 中国科学院微电子研究所 | Preparation method of gate dielectric/metal gate integrated structure |
| CN102543696B (en) * | 2010-12-17 | 2014-12-17 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN102543838B (en) * | 2010-12-22 | 2014-01-29 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN102779751B (en) * | 2011-05-11 | 2015-09-09 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN102856180B (en) * | 2011-06-30 | 2016-05-25 | 中国科学院微电子研究所 | Replacement gate integration method of semiconductor device |
| CN103094111B (en) * | 2011-10-31 | 2016-04-06 | 无锡华润上华科技有限公司 | DMOS device and manufacture method thereof |
| CN103854966B (en) * | 2012-11-30 | 2016-08-24 | 中国科学院微电子研究所 | Planarization processing method |
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