CN102386079B - Manufacturing method of high K grid dielectric layer and method for forming MOS (Metal Oxide Semiconductor) transistor - Google Patents
Manufacturing method of high K grid dielectric layer and method for forming MOS (Metal Oxide Semiconductor) transistor Download PDFInfo
- Publication number
- CN102386079B CN102386079B CN 201010275175 CN201010275175A CN102386079B CN 102386079 B CN102386079 B CN 102386079B CN 201010275175 CN201010275175 CN 201010275175 CN 201010275175 A CN201010275175 A CN 201010275175A CN 102386079 B CN102386079 B CN 102386079B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- gate
- gate openings
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a manufacturing method of a high K grid dielectric layer and a method for forming an MOS (Metal Oxide Semiconductor) transistor. The manufacturing method comprises the following steps of: providing a semiconductor substrate, wherein a dielectric protective layer is formed on the semiconductor substrate, a grid opening is formed in the dielectric protective layer, and the grid opening exposes the semiconductor substrate; sequentially forming an initial dielectric layer and a sacrificial layer in the grid opening, wherein the initial dielectric layer and the sacrificial layer conformally cover the grid opening; vertically injecting metal ions into the grid opening, and respectively converting the initial dielectric layer and the sacrificial layer at the bottom of the grid opening into a high-K dielectric layer and an alloy layer. In the invention, the metal ions are injected into the initial dielectric layer in the grid opening to form the high K grid dielectric layer, and the metal ion injecting direction is vertical to the bottom surface of the grid opening, thus the initial dielectric layer on the vertical side wall of the grid opening can not form the high K dielectric layer with higher dielectric coefficient, higher parasitic capacitance can be avoided from being formed at two sides of a metal grid and performances of a device can not be influenced.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to the manufacture method of high K gate dielectric layer and the method for formation MOS transistor.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more less.Constantly dwindle in the situation in the MOS transistor characteristic size, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, the gate stack structure of high K gate dielectric layer and metal gates is introduced in the MOS transistor.
Be the impact on other structures of transistor of the gate metal material of avoiding metal gates, the gate stack structure of described metal gates and high K gate dielectric layer usually adopts grid to substitute (replacement gate) technique and makes.In this technique, before source-drain area injects, at first form the dummy grid that is consisted of by polysilicon in gate electrode position to be formed, described dummy grid is used for autoregistration and forms the PROCESS FOR TREATMENT such as source-drain area.And after forming source-drain area, can remove described dummy grid and form gate openings in the position of dummy grid, afterwards, in described gate openings, fill successively higher K gate dielectric layer and metal gates.Because metal gates is made after the source-drain area injection is finished again, this has been avoided the gate metal material to be unsuitable for carrying out the problem of high-temperature process so that the quantity of subsequent technique reduces.
Yet, adopt above-mentioned gate replacement technique to make MOS transistor and still exist challenge.Along with further dwindling of grid length, this problem is more serious.In the gate stack structure that this technique forms, be coated with equally high K gate dielectric layer on the vertical sidewall of described gate openings, this causes the parasitic capacitance between source-drain area and metal gates to increase.And the unnecessary parasitic capacitance increase of metal gates can affect devices switch speed.
For solving the larger problem of described metal gates parasitic capacitance, US Patent No. 6864145 discloses a kind of by reduce the method for described gate dielectric layer dielectric coefficient at the gate dielectric layer Implanted Silicon ion of gate openings vertical sidewall.Yet described silicon ion not only is infused in the gate dielectric layer of gate openings vertical sidewall, also can be injected into simultaneously in the gate dielectric layer of gate openings bottom, and this can destroy the dielectric property of gate openings bottom gate dielectric layer, and then affects device performance.7148099 of US Patent No. disclose the method for another kind of reduction gate dielectric layer dielectric coefficient.In the method, need in gate openings, to fill up in advance polysilicon or gate metal material, again with certain angle Implanted Silicon ion, owing to have polysilicon or gate metal material to do to stop in the gate openings, the dielectric property of gate openings bottom gate dielectric layer are not subjected to inject to be affected afterwards.Yet described polysilicon or gate metal material also stop Si ion implantation simultaneously in the gate dielectric layer of gate openings vertical sidewall, so that the gate dielectric layer of this position only has the dielectric coefficient of subregion to be minimized, the grid parasitic capacitance still is difficult to effectively reduce.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of high K gate dielectric layer and forms the method for MOS transistor, when not reducing metal gates bottom gate dielectric layer dielectric property, effectively reduce the dielectric coefficient of metal gates both sides gate dielectric layer, reduced the parasitic capacitance of grid.
For addressing the above problem, the invention provides a kind of manufacture method of high K gate dielectric layer, comprising:
Semiconductor substrate is provided, is formed with dielectric protection layer on the described Semiconductor substrate, be formed with gate openings in the described dielectric protection layer, described gate openings so that Semiconductor substrate expose;
In described gate openings, form successively initial dielectric layer and sacrifice layer, described initial dielectric layer and sacrifice layer conformal cover gate opening;
The vertical metal ion that injects changes respectively initial dielectric layer and sacrifice layer bottom the gate openings into high k dielectric layer and alloy-layer in described gate openings.
Compared with prior art, the present invention has the following advantages:
High K gate dielectric layer is to form by injecting metal ion at the initial dielectric layer in gate openings, and the injection direction of described metal ion is perpendicular to the gate openings bottom surface, this also affects device performance with regard to having been avoided forming larger parasitic capacitance in the metal gates both sides so that the initial dielectric layer of gate openings vertical sidewall can not form the high K gate dielectric layer with higher dielectric coefficient.
Description of drawings
Fig. 1 is the schematic flow sheet of an embodiment of the high K gate dielectric layer of the present invention manufacture method.
Fig. 2 to Fig. 6 is based on the generalized section that the high K gate dielectric layer of the present invention manufacture method forms MOS transistor the first embodiment.
Fig. 7 to Fig. 9 is based on the generalized section that the high K gate dielectric layer of the present invention manufacture method forms MOS transistor the second embodiment.
Figure 10 to Figure 12 is based on the generalized section that the high K gate dielectric layer of the present invention manufacture method forms MOS transistor the 3rd embodiment.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, in the high K gate dielectric layer manufacture method of prior art, in order to reduce the dielectric coefficient of gate openings vertical sidewall gate dielectric layer, need to be in described gate dielectric layer the Implanted Silicon ion.Yet the injection of described silicon ion may reduce the dielectric property of gate openings bottom gate dielectric layer, or owing to stopping of gate openings packing material and so that the gate openings vertical sidewall only has the dielectric coefficient of part gate dielectric layer to be lowered.
For the problems referred to above, the present inventor provides a kind of manufacture method of high K gate dielectric layer, in the method, high K gate dielectric layer is to form by injecting metal ion at the initial dielectric layer in gate openings, and the injection direction of described metal ion is perpendicular to the gate openings bottom surface, this has also just been avoided in the larger parasitic capacitance of metal gates both sides formation so that the initial dielectric layer of gate openings vertical sidewall can not form the high K gate dielectric layer with higher dielectric coefficient.
With reference to figure 1, show the flow process of an embodiment of the high K gate dielectric layer of the present invention manufacture method, comprising:
Execution in step S102 provides Semiconductor substrate, is formed with dielectric protection layer on the described Semiconductor substrate, is formed with gate openings in the described dielectric protection layer, described gate openings so that Semiconductor substrate expose;
Execution in step S104 forms initial dielectric layer and sacrifice layer successively in described gate openings, described initial dielectric layer and sacrifice layer conformal cover gate opening;
Execution in step S106, the vertical metal ion that injects changes respectively initial dielectric layer and sacrifice layer bottom the gate openings into high k dielectric layer and alloy-layer in described gate openings.
The high k dielectric layer of described gate openings bottom is high K gate dielectric layer.After described high K gate dielectric layer forms, need to continue in described gate openings, to fill metal material, to form metal gates.
Next, in conjunction with specific embodiments, the manufacture method of the high K gate dielectric layer of the present invention and the method for formation MOS transistor are further detailed.
The first embodiment
Fig. 2 to Fig. 6 the present invention is based on the generalized section that the high K gate dielectric layer of the present invention manufacture method forms MOS transistor the first embodiment.
As shown in Figure 2, provide Semiconductor substrate 201, be formed with dielectric protection layer 203 on the described Semiconductor substrate 201, described dielectric protection layer 203 covers Semiconductor substrate 201 surfaces.Also be formed with gate openings 207 in the described dielectric protection layer 203, described gate openings 207 so that its bottom Semiconductor substrate 201 surfaces expose.In the present embodiment, also be formed with the first clearance wall 205 in the dielectric protection layer of described gate openings 207 both sides.Described the first clearance wall 205 adopts silicon nitride or other dielectric materials.
As shown in Figure 3, form successively initial dielectric layer 209 and sacrifice layer 211 in described dielectric protection layer 203 and gate openings 207, described initial dielectric layer 209 covers described gate openings 207 with sacrifice layer 211 conformals.Described conformal covers and refers to for the degree of depth and width of gate openings 207, initial dielectric layer 209 is less with the thickness of sacrifice layer 211, can not fill completely described gate openings 207, so that described gate openings 207 still keeps and do not form the front similarly shape of film.
In the present embodiment, described initial dielectric layer 209 comprises the non-high-k dielectric materials such as silica or silicon oxynitride.For described silica, can adopt chemical gas-phase deposition method to form; For described silicon oxynitride, can adopt first chemical vapor deposition to form silica, carry out again Rapid Thermal Nitrided (RTN) and process the described silicon oxynitride of formation; Described sacrifice layer 211 is polysilicon or amorphous silicon, adopts the chemical gaseous phase electrode method to form described polysilicon or amorphous silicon.Described sacrifice layer 211 is used for stopping the metal ion of follow-up injection, avoids injecting because of metal ion the change in dielectric constant inequality of the inhomogeneous initial dielectric layer 209 that causes.
The thickness of described initial dielectric layer 209 is less than 6 nanometers, and the thickness of described sacrifice layer 211 is 30 nanometer to 150 nanometers.
As shown in Figure 4, to the described Semiconductor substrate 201 vertical metal ions that inject, in the initial dielectric layer 209 and sacrifice layer 211 of described metal ion mixing to gate openings 207 bottoms and gate openings 207, form respectively high k dielectric layer 213 and alloy-layer 215 at correspondence position.Wherein, the high k dielectric layer 213 that is positioned at gate openings 207 bottoms is high K gate dielectric layer.
Described metal ion comprises: Hf, Zr, La, Ti, Ta etc., the oxide of described metal ion or nitrogen oxide have the dielectric coefficient that is higher than silica.The implantation dosage of described metal ion is 1E16 to 1E17/ square centimeter, and the energy of ion is 1keV to 10keV.Why the energy of ion is lower, is to consider that the metal ion of described injection need to concentrate on the position of initial dielectric layer 209, and higher energy may so that metal ion is injected in the Semiconductor substrate 201, and cause the dielectric layer break-through.
Take described metal ion as example as Hf, when described initial dielectric layer 209 was silica, described high k dielectric layer 213 was HfSiO, and when described initial dielectric layer 209 was silicon oxynitride, described high k dielectric layer 213 was HfSiON.Described alloy-layer 215 then is the alloy of Si and Hf.
Inject perpendicular to the direction of the bottom of gate openings 207 because described metal ion is the edge, the initial dielectric layer 209 on gate openings 207 vertical sidewalls can't be doped into metal ion, also just can not change high-k dielectric material into.
As shown in Figure 5, after injecting metal ion, remove described alloy-layer, and the sacrifice layer of gate openings 207 vertical sidewalls, initial dielectric layer 209 and high k dielectric layer 213 exposed.In the present embodiment, described sacrifice layer is that silicon, described alloy-layer are the alloy of silicon and metal material, therefore, adopt TMAH solution to remove the alloy of described silicon or silicon, the mass fraction of TMAH is 10% to 30% in described TMAH (tetramethyl aqua ammonia) solution.
Then, adopt rapid thermal oxidation (RTO) and/or Rapid Thermal Nitrided (RTN) to form buffer dielectric layer 217 at described initial dielectric layer 209 and high k dielectric layer 213.In the present embodiment, the reaction temperature of described rapid thermal oxidation and Rapid Thermal Nitrided is 800 degrees centigrade to 1100 degrees centigrade, and the reaction time is 30 seconds to 3 minutes.After described rapid thermal oxidation and/or processed by rapid thermal nitridation, the buffer dielectric layer 217 of formation is silica, silicon nitride or silicon oxynitride, and thickness is less than 20 nanometers.Particularly, the buffer dielectric layer 217 that adopts rapid thermal oxidation to form is silica, and the buffer dielectric layer 217 that adopts Rapid Thermal Nitrided to form is silicon nitride, and the buffer dielectric layer 217 that adopts rapid thermal oxidation and Rapid Thermal Nitrided to form is silicon oxynitride.
As shown in Figure 6, in described gate openings, fill metal material to form metal gates 219.In the present embodiment, described gate metal material can adopt W, Co, Cu or other metal materials.
Above-mentioned technique has formed the grid structure with high K gate dielectric layer and metal gates after carrying out, and the gate dielectric layer of described metal gates both sides has lower dielectric coefficient, thereby has reduced the grid parasitic capacitance, has improved device performance.
The second embodiment
As shown in Figure 4, after metal ion injects, high k dielectric layer 213 and alloy-layer 215 have been formed in the gate openings 207.Different with first embodiment of the invention, in a second embodiment, described alloy-layer 215 and sacrifice layer 211 need not to remove, but utilize this bi-material to continue to make metal silicide.Accordingly, the method for described formation MOS transistor is as follows:
Fig. 7 to Fig. 9 the present invention is based on the generalized section that the high K gate dielectric layer of the present invention manufacture method forms MOS transistor the second embodiment.Wherein, the manufacture method of Fig. 7 is to implement after the flow process of Fig. 2 to Fig. 4, and the handling process of described Fig. 2 to Fig. 4 repeats no more.
As shown in Figure 7; be formed with dielectric protection layer 203 on the described Semiconductor substrate 201; be formed with the gate openings 207 of exposing Semiconductor substrate 201 in the described dielectric protection layer layer 203; be formed with initial dielectric layer 209 and sacrifice layer 211 on the vertical sidewall of described gate openings 207, also be formed with high k dielectric layer 213 and alloy-layer 215 on the bottom of described gate openings 207 and the dielectric protection layer 203.
Then, form metal level 321 at described alloy-layer 215 and sacrifice layer 211, described metal level 321 comprises Ti, Ta, Ni, Co or other metal materials.
As shown in Figure 8, described Semiconductor substrate 201 being carried out short annealing processes.Institute's short annealing processing is so that metal level and its lower siliceous alloy-layer and sacrifice layer reaction, form metal silicide 323, described metal silicide 323 covers whole gate openings 207, and described metal silicide 323 is used for as the workfunction layers of regulating the MOS transistor threshold voltage.
As shown in Figure 9, in described gate openings, fill the gate metal material to form metal gates 319.In the present embodiment, described gate metal material can adopt W, Co, Cu or other metal materials.
The 3rd embodiment
As shown in Figure 4, after metal ion injects, high k dielectric layer 213 and alloy-layer 215 have been formed in the gate openings 207.Different with first embodiment of the invention, in the 3rd embodiment, can utilize the formation technique of similar clearance wall further to increase the medium thickness of described gate openings 207 vertical sidewall positions, to reduce the grid parasitic capacitance.Accordingly, the method for described formation MOS transistor is as follows:
Figure 10 to Figure 12 is based on the generalized section that the high K gate dielectric layer of the present invention manufacture method forms MOS transistor the 3rd embodiment.Wherein, the manufacture method of Figure 10 is to implement after the flow process of Fig. 2 to Fig. 4, and the handling process of described Fig. 2 to Fig. 4 repeats no more.
As shown in figure 10, after the vertical injection of metal ion, remove sacrifice layer and alloy-layer.Afterwards, continue to form laying 425 at described high k dielectric layer 213 and initial dielectric layer 209, described laying 425 conformals cover described gate openings 207.In the present embodiment, described laying 425 adopts silica or silicon oxynitride, and thickness is less than 10 nanometers.
Then, as shown in figure 11, continue to form the clearance wall dielectric layer at laying 425, described clearance wall dielectric layer conformal cover gate opening 207, described clearance wall dielectric layer can adopt silicon nitride.Afterwards, described clearance wall dielectric layer is carried out isotropic dry etch, remove the outer clearance wall dielectric layer of gate openings 207 bottoms and gate openings 207, form the second clearance wall 427 at the vertical sidewall of described gate openings 207.
Described the second clearance wall 427 further dwindles the width of gate openings 207, thereby so that the spacing of the metal gates of follow-up formation and source-drain area further increase, and then so that the grid parasitic capacitance reduced.
As shown in figure 12, fill the gate metal material to form metal gates 419 in described gate openings, the both sides of described metal gates 419 are connected with the second clearance wall 427.In the present embodiment, described gate metal material can adopt W, Co, Cu or other metal materials.
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (18)
1. the manufacture method of a high K gate dielectric layer is characterized in that, comprising:
Semiconductor substrate is provided, is formed with dielectric protection layer on the described Semiconductor substrate, be formed with gate openings in the described dielectric protection layer, described gate openings so that Semiconductor substrate expose;
In described gate openings, form successively initial dielectric layer and sacrifice layer, described initial dielectric layer and sacrifice layer conformal cover gate opening;
The vertical metal ion that injects changes respectively initial dielectric layer and sacrifice layer bottom the gate openings into high k dielectric layer and alloy-layer in described gate openings.
2. manufacture method as claimed in claim 1 is characterized in that, described initial dielectric layer comprises silica or silicon oxynitride.
3. manufacture method as claimed in claim 2 is characterized in that, the thickness of described initial dielectric layer is less than 6 nanometers.
4. manufacture method as claimed in claim 1 is characterized in that, described sacrifice layer adopts polysilicon or amorphous silicon.
5. manufacture method as claimed in claim 4 is characterized in that, the thickness of described sacrifice layer is 30 nanometer to 150 nanometers.
6. manufacture method as claimed in claim 1 is characterized in that, the metal ion of described injection comprises Hf, Zr, La, Ti or Ta.
7. manufacture method as claimed in claim 1 is characterized in that, the injection condition of described metal ion is: implantation dosage 1E16 to 1E17/ square centimeter, Implantation Energy are 1keV to 10keV.
8. the manufacture method of an application rights requirement 1 forms the method for MOS transistor, comprising: after forming high k dielectric layer and alloy-layer,
Remove sacrifice layer and alloy-layer in the described gate openings, expose high k dielectric layer and initial dielectric layer;
In described gate openings, fill the gate metal material to form metal gates.
9. the method for formation MOS transistor as claimed in claim 8 wherein, before forming described metal gates, also comprises: form buffer dielectric layer at described high k dielectric layer and initial dielectric layer, described buffer dielectric layer conformal covers described gate openings.
10. the method for formation MOS transistor as claimed in claim 9, wherein, described buffer dielectric layer adopts silica or silicon oxynitride.
11. the method for formation MOS transistor as claimed in claim 10 wherein, when described buffer dielectric layer is silica, adopts the method for rapid thermal oxidation to form described silica; When described buffer dielectric layer is silicon oxynitride, adopt first rapid thermal oxidation again the method for Rapid Thermal Nitrided form described silicon oxynitride.
12. such as the method for each described formation MOS transistor of claim 8 to 11, wherein, described metal gates adopts W, Co or Cu to form.
13. the manufacture method of an application rights requirement 4 forms the method for MOS transistor, comprising: after forming high k dielectric layer and alloy-layer,
Form metal level at described sacrifice layer and alloy-layer;
Described Semiconductor substrate is carried out short annealing process, so that described sacrifice layer and alloy-layer change metal silicide into;
In described gate openings, fill the gate metal material to form metal gates.
14. the method for formation MOS transistor as claimed in claim 13, wherein, described metal level comprises Ti, Ta, Ni or Co.
15. such as the method for claim 13 or 14 described formation MOS transistor, wherein, described metal gates adopts W, Co or Cu to form.
16. the manufacture method of an application rights requirement 1 forms the method for MOS transistor, comprising: after forming high k dielectric layer and alloy-layer,
Remove sacrifice layer and alloy-layer in the described gate openings, expose high k dielectric layer and initial dielectric layer;
On described high k dielectric layer and initial dielectric layer, form successively laying and clearance wall dielectric layer;
The described clearance wall dielectric layer of anisotropic etching removes the outer clearance wall dielectric layer bottom gate openings of gate openings, forms the second clearance wall at the vertical sidewall of gate openings.
17. the method for formation MOS transistor as claimed in claim 16, wherein, described laying comprises silica or silicon oxynitride, and described clearance wall dielectric layer adopts silicon nitride.
18. the method such as claim 16 or 17 described formation MOS transistor is characterized in that, described metal gates adopts W, Co or Cu to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010275175 CN102386079B (en) | 2010-09-02 | 2010-09-02 | Manufacturing method of high K grid dielectric layer and method for forming MOS (Metal Oxide Semiconductor) transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010275175 CN102386079B (en) | 2010-09-02 | 2010-09-02 | Manufacturing method of high K grid dielectric layer and method for forming MOS (Metal Oxide Semiconductor) transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102386079A CN102386079A (en) | 2012-03-21 |
| CN102386079B true CN102386079B (en) | 2013-05-29 |
Family
ID=45825374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010275175 Active CN102386079B (en) | 2010-09-02 | 2010-09-02 | Manufacturing method of high K grid dielectric layer and method for forming MOS (Metal Oxide Semiconductor) transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102386079B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087231A (en) * | 1999-08-05 | 2000-07-11 | Advanced Micro Devices, Inc. | Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant |
| US6812106B1 (en) * | 2003-01-14 | 2004-11-02 | Advanced Micro Devices, Inc. | Reduced dopant deactivation of source/drain extensions using laser thermal annealing |
| US6864145B2 (en) * | 2003-06-30 | 2005-03-08 | Intel Corporation | Method of fabricating a robust gate dielectric using a replacement gate flow |
| US7148099B2 (en) * | 2004-06-24 | 2006-12-12 | Intel Corporation | Reducing the dielectric constant of a portion of a gate dielectric |
| CN101728257A (en) * | 2008-10-24 | 2010-06-09 | 中国科学院微电子研究所 | Preparation method of gate dielectric/ metal gate integrated structure |
-
2010
- 2010-09-02 CN CN 201010275175 patent/CN102386079B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087231A (en) * | 1999-08-05 | 2000-07-11 | Advanced Micro Devices, Inc. | Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant |
| US6812106B1 (en) * | 2003-01-14 | 2004-11-02 | Advanced Micro Devices, Inc. | Reduced dopant deactivation of source/drain extensions using laser thermal annealing |
| US6864145B2 (en) * | 2003-06-30 | 2005-03-08 | Intel Corporation | Method of fabricating a robust gate dielectric using a replacement gate flow |
| US7148099B2 (en) * | 2004-06-24 | 2006-12-12 | Intel Corporation | Reducing the dielectric constant of a portion of a gate dielectric |
| CN101728257A (en) * | 2008-10-24 | 2010-06-09 | 中国科学院微电子研究所 | Preparation method of gate dielectric/ metal gate integrated structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102386079A (en) | 2012-03-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11257951B2 (en) | Method of making semiconductor device having first and second epitaxial materials | |
| KR100868649B1 (en) | Semiconductor device and method of fabricating the same | |
| US9070759B2 (en) | Semiconductor device and method of making same | |
| US20130181265A1 (en) | Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer | |
| US20140191301A1 (en) | Transistor and fabrication method | |
| US20110263092A1 (en) | Method for fabricating a semiconductor device | |
| US8765586B2 (en) | Methods of forming metal silicide regions on semiconductor devices | |
| JP2004128505A (en) | Nonvolatile memory device and its manufacturing method | |
| US20100244155A1 (en) | Maintaining integrity of a high-k gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy | |
| US8748281B2 (en) | Enhanced confinement of sensitive materials of a high-K metal gate electrode structure | |
| US20090294807A1 (en) | Methods of Fabricating Transistors and Structures Thereof | |
| CN102737992B (en) | The method be used for producing the semiconductor devices | |
| CN102386234A (en) | Strained asymmetric source/drain | |
| CN103681337A (en) | Fin type field effect transistor and forming method thereof | |
| CN103094214B (en) | Manufacturing method for semiconductor device | |
| CN100477093C (en) | Method for forming semiconductor device | |
| US8039342B2 (en) | Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal | |
| CN102983104B (en) | The manufacture method of CMOS transistor | |
| CN102386083B (en) | MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer | |
| CN107045981B (en) | The forming method of semiconductor structure | |
| CN104681440A (en) | Semiconductor device and preparation method thereof | |
| CN105990341B (en) | Semiconductor structure and forming method thereof | |
| KR100752201B1 (en) | Manufacturing method of semiconductor device | |
| US8536053B2 (en) | Method for restricting lateral encroachment of metal silicide into channel region | |
| CN102386079B (en) | Manufacturing method of high K grid dielectric layer and method for forming MOS (Metal Oxide Semiconductor) transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20121108 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |