Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Said as the background technology part, in the high K gate dielectric layer manufacture method of prior art,, need in said gate dielectric layer, inject silicon ion in order to reduce the dielectric coefficient of gate openings vertical sidewall gate dielectric layer.Yet the injection of said silicon ion may reduce the dielectric property of gate openings bottom gate dielectric layer, or owing to stopping of gate openings packing material makes the gate openings vertical sidewall only have the dielectric coefficient of part gate dielectric layer to be lowered.
To the problems referred to above; Inventor of the present invention provides a kind of manufacture method of high K gate dielectric layer; In the method, high K gate dielectric layer is to form through injecting metal ion at the initial dielectric layer in gate openings, and the injection direction of said metal ion is perpendicular to the gate openings bottom surface; This makes the initial dielectric layer of gate openings vertical sidewall can not form the high K gate dielectric layer with higher dielectric coefficient, has also just avoided the bigger parasitic capacitance of formation in the metal gates both sides.
With reference to figure 1, show the flow process of an embodiment of the high K gate dielectric layer of the present invention manufacture method, comprising:
Execution in step S102 provides Semiconductor substrate, is formed with dielectric protection layer on the said Semiconductor substrate, is formed with gate openings in the said dielectric protection layer, and said gate openings makes Semiconductor substrate expose;
Execution in step S104 forms initial dielectric layer and sacrifice layer successively in said gate openings, said initial dielectric layer and sacrifice layer conformal cover gate opening;
Execution in step S106, the vertical metal ion that injects changes initial dielectric layer and sacrifice layer bottom the gate openings into high k dielectric layer and alloy-layer respectively in said gate openings.
The high k dielectric layer of said gate openings bottom is high K gate dielectric layer.After said high K gate dielectric layer forms, need to continue in said gate openings, to fill metal material, to form metal gates.
Next, in conjunction with concrete embodiment, the manufacture method of the high K gate dielectric layer of the present invention and the method for formation MOS transistor are further explained.
First embodiment
Fig. 2 to Fig. 6 the present invention is based on the generalized section that the high K gate dielectric layer of the present invention manufacture method forms MOS transistor first embodiment.
As shown in Figure 2, Semiconductor substrate 201 is provided, be formed with dielectric protection layer 203 on the said Semiconductor substrate 201, said dielectric protection layer 203 covers Semiconductor substrate 201 surfaces.Also be formed with gate openings 207 in the said dielectric protection layer 203, said gate openings 207 makes Semiconductor substrate 201 surfaces of its bottom expose.In the present embodiment, also be formed with first clearance wall 205 in the dielectric protection layer of said gate openings 207 both sides.Said first clearance wall 205 adopts silicon nitride or other dielectric materials.
As shown in Figure 3, in said dielectric protection layer 203 and gate openings 207, form initial dielectric layer 209 and sacrifice layer 211 successively, said initial dielectric layer 209 covers said gate openings 207 with sacrifice layer 211 conformals.Said conformal covers and is meant for the degree of depth and width of gate openings 207; Initial dielectric layer 209 is less with the thickness of sacrifice layer 211; Can not fill completely said gate openings 207, make said gate openings 207 still keep and do not form before the film similarly shape.
In the present embodiment, said initial dielectric layer 209 comprises non-high-k dielectric materials such as silica or silicon oxynitride.For said silica, can adopt chemical gas-phase deposition method to form; For said silicon oxynitride, can adopt first chemical vapor deposition to form silica, carry out Rapid Thermal Nitrided (RTN) again and handle the said silicon oxynitride of formation; Said sacrifice layer 211 is polysilicon or amorphous silicon, adopts the chemical gaseous phase electrode method to form said polysilicon or amorphous silicon.Said sacrifice layer 211 is used to stop the metal ion of follow-up injection, avoids injecting because of metal ion the change in dielectric constant inequality of the inhomogeneous initial dielectric layer 209 that causes.
The thickness of said initial dielectric layer 209 is less than 6 nanometers, and the thickness of said sacrifice layer 211 is 30 nanometer to 150 nanometers.
As shown in Figure 4; To the said Semiconductor substrate 201 vertical metal ions that inject; In the initial dielectric layer 209 and sacrifice layer 211 outside said metal ion mixing to gate openings 207 bottoms and the gate openings 207, form high k dielectric layer 213 and alloy-layer 215 respectively at correspondence position.Wherein, the high k dielectric layer 213 that is positioned at gate openings 207 bottoms is high K gate dielectric layer.
Said metal ion comprises: Hf, Zr, La, Ti, Ta etc., the oxide of said metal ion or nitrogen oxide have the dielectric coefficient that is higher than silica.The implantation dosage of said metal ion is 1E16 to a 1E17/ square centimeter, and the injection energy of ions is 1keV to 10keV.It is lower why to inject energy of ions, be to consider that the metal ion of said injection need concentrate on the position of initial dielectric layer 209, and higher energy may make metal ion be injected in the Semiconductor substrate 201, and cause the dielectric layer break-through.
With said metal ion is that Hf is an example, and when said initial dielectric layer 209 was silica, said high k dielectric layer 213 was HfSiO, and when said initial dielectric layer 209 was silicon oxynitride, said high k dielectric layer 213 was HfSiON.Said alloy-layer 215 then is the alloy of Si and Hf.
Because said metal ion is to inject along the direction perpendicular to the bottom of gate openings 207, the into metal ion that can't mix of the initial dielectric layer 209 on gate openings 207 vertical sidewalls just can not change high-k dielectric material into yet.
As shown in Figure 5, after injecting metal ion, remove said alloy-layer, and the sacrifice layer of gate openings 207 vertical sidewalls, expose initial dielectric layer 209 and high k dielectric layer 213.In the present embodiment, said sacrifice layer is that silicon, said alloy-layer are the alloy of silicon and metal material, therefore, adopts TMAH solution to remove the alloy of said silicon or silicon, and the mass fraction of TMAH is 10% to 30% in said TMAH (tetramethyl aqua ammonia) solution.
Then, adopt rapid thermal oxidation (RTO) and/or Rapid Thermal Nitrided (RTN) on said initial dielectric layer 209 and high k dielectric layer 213, to form buffer dielectric layer 217.In the present embodiment, the reaction temperature of said rapid thermal oxidation and Rapid Thermal Nitrided is 800 degrees centigrade to 1100 degrees centigrade, and the reaction time is 30 seconds to 3 minutes.After said rapid thermal oxidation and/or processed by rapid thermal nitridation, the buffer dielectric layer 217 of formation is silica, silicon nitride or silicon oxynitride, and thickness is less than 20 nanometers.Particularly, the buffer dielectric layer 217 that adopts rapid thermal oxidation to form is a silica, and the buffer dielectric layer 217 that adopts Rapid Thermal Nitrided to form is a silicon nitride, and the buffer dielectric layer 217 that adopts rapid thermal oxidation and Rapid Thermal Nitrided to form is a silicon oxynitride.
As shown in Figure 6, in said gate openings, fill metal material to form metal gates 219.In the present embodiment, said gate metal material can adopt W, Co, Cu or other metal materials.
Above-mentioned technology has formed the grid structure with high K gate dielectric layer and metal gates after carrying out, and the gate dielectric layer of said metal gates both sides has lower dielectric coefficient, thereby has reduced the grid parasitic capacitance, has improved device performance.
Second embodiment
As shown in Figure 4, after metal ion injects, formed high k dielectric layer 213 and alloy-layer 215 in the gate openings 207.Different with first embodiment of the invention, in a second embodiment, said alloy-layer 215 and sacrifice layer 211 need not to remove, but utilize these two kinds of materials to continue to make metal silicide.Accordingly, the method for said formation MOS transistor is following:
Fig. 7 to Fig. 9 the present invention is based on the generalized section that the high K gate dielectric layer of the present invention manufacture method forms MOS transistor second embodiment.Wherein, the manufacture method of Fig. 7 is after the flow process of Fig. 2 to Fig. 4, to implement, and the handling process of said Fig. 2 to Fig. 4 repeats no more.
As shown in Figure 7; Be formed with dielectric protection layer 203 on the said Semiconductor substrate 201; Be formed with the gate openings 207 of exposing Semiconductor substrate 201 in the said dielectric protection layer layer 203; Be formed with initial dielectric layer 209 and sacrifice layer 211 on the vertical sidewall of said gate openings 207, also be formed with high k dielectric layer 213 and alloy-layer 215 on the bottom of said gate openings 207 and the dielectric protection layer 203.
Then, on said alloy-layer 215 and sacrifice layer 211, form metal level 321, said metal level 321 comprises Ti, Ta, Ni, Co or other metal materials.
As shown in Figure 8, said Semiconductor substrate 201 is carried out short annealing handle.Alloy-layer and the sacrifice layer reaction that makes that metal level and its are siliceous down handled in institute's short annealing; Form metal silicide 323; Said metal silicide 323 covers whole gate openings 207, and said metal silicide 323 is used for as the workfunction layers of regulating the MOS transistor threshold voltage.
As shown in Figure 9, in said gate openings, fill the gate metal material to form metal gates 319.In the present embodiment, said gate metal material can adopt W, Co, Cu or other metal materials.
The 3rd embodiment
As shown in Figure 4, after metal ion injects, formed high k dielectric layer 213 and alloy-layer 215 in the gate openings 207.Different with first embodiment of the invention, in the 3rd embodiment, can utilize the formation technology of similar clearance wall further to increase the medium thickness of said gate openings 207 vertical sidewall positions, to reduce the grid parasitic capacitance.Accordingly, the method for said formation MOS transistor is following:
Figure 10 to Figure 12 is based on the generalized section that the high K gate dielectric layer of the present invention manufacture method forms MOS transistor the 3rd embodiment.Wherein, the manufacture method of Figure 10 is after the flow process of Fig. 2 to Fig. 4, to implement, and the handling process of said Fig. 2 to Fig. 4 repeats no more.
Shown in figure 10, after the vertical injection of metal ion, remove sacrifice layer and alloy-layer.Afterwards, on said high k dielectric layer 213 and initial dielectric layer 209, continue to form laying 425, said laying 425 conformals cover said gate openings 207.In the present embodiment, said laying 425 adopts silica or silicon oxynitride, and thickness is less than 10 nanometers.
Then, shown in figure 11, on laying 425, continue to form the clearance wall dielectric layer, said clearance wall dielectric layer conformal cover gate opening 207, said clearance wall dielectric layer can adopt silicon nitride.Afterwards, said clearance wall dielectric layer is carried out isotropic dry etch, remove the outer clearance wall dielectric layer of gate openings 207 bottoms and gate openings 207, form second clearance wall 427 at the vertical sidewall of said gate openings 207.
Said second clearance wall 427 further dwindles the width of gate openings 207, thereby makes the metal gates of follow-up formation and the spacing of source-drain area further increase, and then makes the grid parasitic capacitance be able to reduce.
Shown in figure 12, in said gate openings, fill the gate metal material to form metal gates 419, the both sides of said metal gates 419 are connected with second clearance wall 427.In the present embodiment, said gate metal material can adopt W, Co, Cu or other metal materials.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.