CN102254805B - Method for adjusting work function of metal gate applied to N-channel metal oxide semiconductor (NMOS) device - Google Patents
Method for adjusting work function of metal gate applied to N-channel metal oxide semiconductor (NMOS) device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Abstract
The invention relates to a method for adjusting the work function of a metal gate applied to an N-channel metal oxide semiconductor (NMOS) device. The method comprises the following steps of: depositing a layer of metal nitride film or a metal film serving as a metal gate electrode on the surface of a high K medium by a physical vapor deposition method; injecting elements such as Tb or Er or Yb or Sr and the like into the metal gate electrode by an ion injection method; and driving doped metal ions into an interface between the metal gate electrode and the high K medium by high-temperature thermal annealing to form accumulation or forming dipoles on the interface between a high K gate medium and SiO2 to achieve the purpose of adjusting the effective work function of the metal gate. The method is simple and convenient, and has universality, high capability of adjusting the work function of the metal gate and good compatibility with a complementary metal oxide semiconductor (CMOS) process.
Description
Technical field
The invention belongs to technical field of semiconductors, refer in particular to a kind of control method that is applicable to the metal gate work function of nmos device, be suitable for 45 nanometers and following technology generation high-performance nano yardstick CMOS (Complementary Metal Oxide Semiconductor) (CMOS) preparation of devices and use.
Background technology
Along with the characteristic size of cmos device enters into the 45nm technology node and when following, in order to reduce grid tunnelling current and gate resistance significantly, eliminate the depletion of polysilicon effect, improve device reliability, alleviate the fermi level pinning effect, adopt high K (dielectric constant)/metal gate material to replace traditional SiO
2/ poly-Si (polysilicon) structure has become the common recognition of industry.But metal gate is integrated into and still has many problems urgency to be solved on the high-K gate dielectric, and as thermal stability problems, interfacial state problem, particularly Fermi's pinning effect make the acquisition of the suitable low threshold voltage of nanometer cmos device needs face very big challenge.
Summary of the invention
The objective of the invention is to propose a kind of control method that is applicable to the metal gate work function of nmos device, to obtain suitable gate work function, in the hope of obtaining appropriate threshold voltage.
For achieving the above object, the control method that is applicable to the metal gate work function of nmos device provided by the invention, its key step is as follows:
The step 1) device isolation forms the formation of rear interface oxide layer SiOx or SiON: under 600-900 ℃, 20-120 rapid thermal oxidation second forms;
Step 2) formation of gate dielectric membrane with high dielectric coefficient: adopt the PVD method, utilize reactive magnetron sputtering technology alternating sputtering Hf-La target and the deposit of Hf target to form HfLaON or alternating sputtering Hf target and the deposit of Si target and form the HfSiON gate medium;
Rapid thermal annealing behind the step 3) depositing high dielectric constant dielectric film: under 600-1050 ℃, 10-120 thermal annealing second;
The step 4) metal gate electrode forms: adopt the PVD method, utilize reactive magnetron sputtering depositing metal Metal Nitride Gates;
Step 5) N type metal ion injects the metal nitride grid is mixed;
The step 6) etching forms metal gate electrode;
Step 7) thermal annealing: temperature 350-1050 ℃;
Step 8) back side ohmic contact forms: adopt the PVD method, utilize direct current sputtering technology depositing Al-Si film overleaf;
Under step 9) alloy: the 380-450 ℃ temperature, N in alloying furnace
2Middle alloy annealing 30-60 branch.
Described control method, wherein, in the step 1 after device isolation forms, before interface oxide layer forms, adopt conventional method to clean earlier, then with under room temperature, soaking in hydrofluoric acid/isopropanol mixed solution, deionized water rinsing carries out the formation of interface oxide layer immediately after the drying.
Described control method, wherein, hydrofluoric acid in the step 1/isopropanol mixed solution concentration ratio is 0.2-1.5%: 0.01-0.10%: 1%, soak time is 2-10 minute.
Described control method, wherein, step 2 median surface oxide layer SiON adopts and injects nitrogen rapid thermal oxidation formation or the plasma nitrided again formation of initial oxidation more earlier.
Described control method, wherein, the sputter of high-dielectric-coefficient grid medium film is at N in the step 2
2Carry out ratio and thickness that power by changing alternating sputtering Hf-La target and Hf target or Hf target and Si target and time are regulated and control each element in/the Ar atmosphere.
Described control method, wherein, the depositing metal Metal Nitride Gates adopts at N in the step 4
2Corresponding TiN or TaN or the MoN of forming respectively of reactive sputtering Ti target or Ta target or Mo target in/the Ar atmosphere.
Described control method, wherein, metal ion injects nmos device in the step 5, and the ion of selection injects element to be had respectively: Tb or Er or Yb or Sr.
Described control method, wherein, TiN or TaN metal gate electrode adopt the ion etching of Cl radical reaction to form in the step 6, or adopt chemical wet etching to form.
Described control method, wherein, the thermal annealing in the step 7 divides two classes, and a class is to be suitable for first grid technique, adopts rapid thermal annealing or spike annealing or laser annealing, temperature 950-1200 ℃ ,-30 seconds 5 milliseconds of times; Another kind of is to be suitable for the back grid technique, adopts stove annealing, temperature 350-550 ℃, and time 20-60 branch.
Described control method, wherein, the Al-Si film thickness of step 8 back spatter deposition is the 80-120 nanometer.
The present invention adopts ion injection method that metal ion is injected in the metal gate membrane electrode, and behind rapid thermal annealing, ion is piled up on the interface of metal gate and high-K gate dielectric or at high-K gate dielectric and SiO
2The interface on generate dipole by interfacial reaction, reach the purpose of regulating the metal gate work function, and then realize the control of suitably low threshold voltage.The method is simple, has the ability of good thermal stability and adjusting metal gate work function, and compatible fully with CMOS technology, is convenient to IC industryization.
Description of drawings
Fig. 1 is under the different Tb implantation dosages, the different NMOS electric capacity TiTbN/HfLaON/ILSiO of Tb content among the metal gate TiTbN
2The comparison of/N (100) Si grid structure High Frequency C-V characteristic.Increase with the Tb implantation dosage as can be seen from figure, the C-V characteristic curve moves significantly to negative direction, shows that flat band voltage moves significantly to negative direction, and promptly the work function of nmos device reduces significantly.
Embodiment
The present invention utilizes physical vapor deposition (PVD) method, at high K medium such as HfLaOH, deposit layer of metal nitride film or metal film above the HfSiON etc., as metal gate electrode, adopt ion injection method that metal gate electrode is mixed then, to nmos device, the ion of selecting injects element Tb respectively, or Er, or Yb, or element such as Sr, doped metal ion is driven on the interface that enters metal gate electrode and high-K gate dielectric to form by high-temperature thermal annealing then and pile up or on the interface of high-K gate dielectric and SiO2, form dipole, cause the change of gate work function by interfacial reaction.The kind of change amount and metal gate material and dopant ion, the section of concentration distribute and are relevant with the response situation at interface.Optimize energy, dosage and heat-treat condition that ion injects, can obtain suitable gate work function, in the hope of obtaining appropriate threshold voltage.This method has universality, and technology is simple and convenient, and the ability of regulating the metal gate work function is strong, and is fine with the CMOS processing compatibility.
Key step of the present invention is as follows:
Step 1) is cleaned: after device isolation forms, carry out the cleaning before interface oxide layer forms, adopt conventional method to clean earlier, at room temperature soak with hydrofluoric acid/isopropanol mixed solution then, deionized water rinsing advances stove immediately after the drying; The weight ratio of hydrofluoric acid/isopropanol is 0.2-1.5%: 0.01-0.10%: 1%; Soak time is 0.5 minute-8 minutes.
Step 2) formation of boundary layer SiOx or SiON: under 600-900 ℃, 20-120 rapid thermal annealing second;
The formation of step 3) high-k (K) gate dielectric membrane: adopt the PVD method, utilize reactive magnetron sputtering technology alternating sputtering Hf-La target and the deposit of Hf target to form HfLaON or alternating sputtering Hf target and the deposit of Si target and form the HfSiON gate medium; Change the time of sputtering power or alternating sputtering, to obtain the high K deielectric-coating of different proportion and thickness.
Rapid thermal annealing behind the high K medium of step 4) deposit: under 600-1050 ℃, 4-120 thermal annealing second;
The step 5) metal gate electrode forms: adopts the PVD method, utilizes reactive magnetron sputtering depositing metal Metal Nitride Gates, and as TiN, TaN, MoN etc.;
Step 6) N type metal ion (as Tb, or Er, or Yb, or Sr etc.) inject the metal nitride grid are mixed;
Step 7) adopts the ion etching of Cl radical reaction to form metal gate electrode;
The step 8) high-temperature quick thermal annealing: under 500-1050 ℃, 2-30 thermal annealing second;
Step 9) back side ohmic contact forms: adopt the PVD method, utilize direct current sputtering technology depositing Al-Si film overleaf, film thickness 80-120nm;
Under step 10) alloy: the 380-450 ℃ temperature, N in alloying furnace
2In or (N
2+ 10%H
2) middle alloy annealing 30-60 branch.
Be further described below in conjunction with embodiment.
Step 1. is cleaned: after device isolation forms, carry out the cleaning before interface oxide layer forms, adopt conventional method to clean earlier, use hydrofluoric acid then: isopropyl alcohol: water (weight ratio)=0.3-0.8%: 0.01-0.08%: 1% mixed solution at room temperature soaks the 2-10 branch, deionized water rinsing, N
2Advance stove immediately after middle the drying;
Step 2. boundary layer SiOx forms: under 600-800 ℃ of temperature, at N
2In rapid thermal annealing (RTA) 20-120 second; Generate the oxide layer of 5-7A;
The formation of step 3. high-k (K) gate dielectric membrane: adopt the PVD method, utilize reactive magnetron sputtering technology at N
2Alternating sputtering Hf-La target and the deposit of Hf target form HfLaON in/the Ar atmosphere, and the sputter operating pressure is 5 * 10
-3Torr, sputtering power are 100-500W, the thick 10-40 dust of HfLaON high-k gate dielectric film that deposit forms;
Step 4. ultrasonic cleaning; Adopted acetone, absolute ethyl alcohol successively each ultrasonic cleaning 5-10 minute, deionized water rinsing, N
2The middle drying;
Rapid thermal annealing behind the high K medium of step 5. deposit: after drying, slice, thin piece advances stove immediately, and temperature 600-1000 ℃, time 10-120 second.
Step 6. metal nitride grid thin film deposition: adopt reactive magnetron sputtering technology at N
2The sputtered with Ti target forms TiN metal gate film, operating pressure 5 * 10 in the/Ar atmosphere
-3 モ, N
2Flow 2-8sccm, sputtering power are 600-1000w, TiN film thickness 5-100 nanometer.
Step 7. ion injects Tb: energy 10Kev-120Kev, dosage 2 * 10
14-6 * 10
15/ cm
2
Step 8. etching TiTbN electrode metal grid: adopt Cl radical reaction plasma etching, radio-frequency power 100-400W forms TiTbN metal gate electrode figure;
Step 9. rapid thermal annealing: to first grid technique, under nitrogen protection, rapid thermal annealing is 2 to 30 seconds under 700 to 1050 ℃ of temperature;
Step 10. back side ohmic contact forms: adopt the PVD method, utilize direct current sputtering technology backside deposition Al-Si film 60-100 nanometer in Ar atmosphere;
Under step 11. alloy: 380-450 ℃, under nitrogen protection alloy 30-60 minute.
Table 1 has provided the variation of flat band voltage with the Tb implantation dosage.At the Tb implantation dosage is 5.5E14cm
-2Down, compare with the Tb that undopes, flat band voltage has moved 0.38V significantly to negative direction, and is very effective, satisfied the needs of nmos device admirably.
Table 1
| Terbium implantation dosage (CM -2) | 0 | 3.5E14 | 4.5E14 | 5.5E14 |
| Flat band voltage (V) | -0.5 | -0.662 | -0.770 | -0.882 |
Claims (10)
1. control method that is applicable to the metal gate work function of nmos device, its key step is as follows:
The step 1) device isolation forms rear interface oxide layer SiO
2Or the formation of SiON: under 600-900 ℃, 20-120 rapid thermal oxidation second forms;
Step 2) formation of gate dielectric membrane with high dielectric coefficient: adopt the PVD method, utilize reactive magnetron sputtering technology alternating sputtering Hf-La target and the deposit of Hf target to form HfLaON or alternating sputtering Hf target and the deposit of Si target and form the HfSiON gate medium;
Rapid thermal annealing behind the step 3) depositing high dielectric constant dielectric film: under 600-1050 ℃, 10-120 thermal annealing second;
The step 4) metal gate electrode forms: adopt the PVD method, utilize reactive magnetron sputtering depositing metal Metal Nitride Gates;
Step 5) N type metal ion injects the metal nitride grid is mixed;
The step 6) etching forms metal gate electrode;
Step 7) thermal annealing: temperature 350-1050 ℃;
Step 8) back side ohmic contact forms: adopt the PVD method, utilize direct current sputtering technology depositing Al-Si film overleaf;
Under step 9) alloy: the 380-450 ℃ temperature, N in alloying furnace
2Middle alloy annealing 30-60 branch.
2. control method according to claim 1, wherein, in the step 1 after device isolation forms, before interface oxide layer forms, adopt conventional method to clean earlier, with soaking under room temperature in hydrofluoric acid/isopropanol mixed solution, deionized water rinsing carries out the formation of interface oxide layer immediately after the drying then.
3. control method according to claim 2, wherein, hydrofluoric acid in the step 1/isopropanol mixed solution concentration ratio is 0.2-1.5%: 0.01-0.10%: 1%, soak time is 2-10 minute.
4. control method according to claim 1, wherein, step 2 median surface oxide layer SiON adopts and injects nitrogen rapid thermal oxidation formation or the plasma nitrided again formation of initial oxidation more earlier.
5. control method according to claim 1, wherein, the sputter of high-dielectric-coefficient grid medium film is at N in the step 2
2Carry out ratio and thickness that power by changing alternating sputtering Hf-La target and Hf target or Hf target and Si target and time are regulated and control each element in/the Ar atmosphere.
6. control method according to claim 1, wherein, the depositing metal Metal Nitride Gates adopts at N in the step 4
2Corresponding TiN or TaN or the MoN of forming respectively of reactive sputtering Ti target or Ta target or Mo target in/the Ar atmosphere.
7. control method according to claim 1, wherein, metal ion injects nmos device in the step 5, and the ion of selection injects element to be had respectively: Tb or Er or Yb or Sr.
8. control method according to claim 1, wherein, TiN or TaN metal gate electrode adopt the ion etching of Cl radical reaction to form in the step 6, or adopt chemical wet etching to form.
9. control method according to claim 1, wherein, the thermal annealing in the step 7 divides two classes, and a class is to be suitable for first grid technique, adopts rapid thermal annealing or spike annealing or laser annealing, temperature 950-1200 ℃ ,-30 seconds 5 milliseconds of times; Another kind of is to be suitable for the back grid technique, adopts stove annealing, temperature 350-550 ℃, and time 20-60 branch.
10. control method according to claim 1, wherein, the Al-Si film thickness of step 8 back spatter deposition is the 80-120 nanometer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010183450 CN102254805B (en) | 2010-05-19 | 2010-05-19 | Method for adjusting work function of metal gate applied to N-channel metal oxide semiconductor (NMOS) device |
| US13/057,336 US8298927B2 (en) | 2010-05-19 | 2010-09-21 | Method of adjusting metal gate work function of NMOS device |
| PCT/CN2010/001457 WO2011143798A1 (en) | 2010-05-19 | 2010-09-21 | Method for adjusting metal gate work function of nmos device |
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| CN103311247B (en) * | 2012-03-14 | 2016-07-13 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| CN103855007A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Manufacturing method of P type MOSFE |
| CN103855012A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Manufacturing method of N type MOSFET |
| CN103855014B (en) * | 2012-11-30 | 2017-10-20 | 中国科学院微电子研究所 | P-type MOSFET and its manufacture method |
| CN103855013A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Manufacturing method of N type MOSFET |
| CN103855094A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN103855008A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | N type mosfet and manufacturing method thereof |
| US9029225B2 (en) | 2012-11-30 | 2015-05-12 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing N-type MOSFET |
| CN105990403B (en) * | 2015-01-29 | 2019-05-07 | 中国科学院微电子研究所 | A kind of grid and forming method thereof |
| US11264477B2 (en) * | 2019-09-23 | 2022-03-01 | Globalfoundries U.S. Inc. | Field-effect transistors with independently-tuned threshold voltages |
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