CN102110598A - Adjustment method for fully silicided metal gate work function for PMOS devices - Google Patents

Adjustment method for fully silicided metal gate work function for PMOS devices Download PDF

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CN102110598A
CN102110598A CN2009102437394A CN200910243739A CN102110598A CN 102110598 A CN102110598 A CN 102110598A CN 2009102437394 A CN2009102437394 A CN 2009102437394A CN 200910243739 A CN200910243739 A CN 200910243739A CN 102110598 A CN102110598 A CN 102110598A
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oxidation
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impurity
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周华杰
徐秋霞
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Institute of Microelectronics of CAS
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Abstract

一种适用于PMOS器件的全硅化金属栅功函数的调节方法，包括：局部氧化隔离或浅槽隔离，进行注入前氧化，然后注入14N+；漂净注入前氧化膜，栅氧化，并沉积多晶硅；光刻、刻蚀形成多晶硅栅电极；注入Al杂质，杂质激活；淀积金属镍，退火硅化，使金属镍和多晶硅完全反应形成全硅化物金属栅；选择去除未反应的金属镍。本发明提供的方法，易于集成，实现了与CMOS工艺的良好兼容。

A method for adjusting the work function of a fully silicided metal gate suitable for PMOS devices, comprising: local oxidation isolation or shallow trench isolation, performing pre-implantation oxidation, and then implanting 14 N + ; bleaching the pre-implantation oxide film, gate oxidation, and depositing Polysilicon; photolithography and etching to form polysilicon gate electrodes; injecting Al impurities, impurity activation; depositing metal nickel, annealing and silicide, making metal nickel and polysilicon completely react to form a full silicide metal gate; selectively removing unreacted metal nickel. The method provided by the invention is easy to integrate and realizes good compatibility with CMOS technology.

Description

Be applicable to the control method of PMOS device full silicidation metal gate work function
Technical field
The present invention relates to microelectronics sub-micro technology complementation metal oxide semiconductor device (CMOS) and vlsi technology field, be meant a kind of method that is used to regulate PMOS device full silicidation metal gate gate work function especially.
Background technology
Along with the development of microelectric technique, traditional polygate electrodes can not satisfy the requirement of nano-device.There is following problem in the nano-device polygate electrodes:
The boron penetration effects of a, PMOS pipe;
B, depletion of polysilicon effect;
C, grid series resistance are excessive;
There is Fermi's pinning effect in d, incompatible with gate dielectric material of future generation (high-dielectric-coefficient grid medium).
And metal gate electrode can be good at solving the above problem that polygate electrodes exists, and becomes the replacer of polygate electrodes, and becomes the focus of research in the world.
But the preparation metal gate device also has a lot of problems to need to solve.At first the factor of Kao Lving is exactly the selection problem of grid material.When which kind of material decision selects as grid material, to consider several factors.Such as:
1) with the compatibility of CMOS technology (as thermal stability, but etching etc.);
2) to the influence of gate medium reliability;
3) extensibility of technology (as high-dielectric-coefficient grid medium).
Except top factor, the factor of the main consideration of selection is the matching problem of suitable gate work function.
Because gate work function directly influences the threshold voltage (V of device Th) and transistorized performance.In order to obtain good performance, must select suitable gate work function to make the threshold voltage symmetry of NMOS and PMOS pipe also suitably low.For the device of advanced person's new construction, gate work function is particularly important.These new device structures much are operated under the mode of operation that exhausts entirely.The very low even not doping of substrate doping.The threshold value that can avoiding like this mixes causes is floated, and reduces the scattering process of impurity to the channel region charge carrier, improves the mobility of charge carrier rate, obtains higher drive current.But the result who does like this can not adopt in raceway groove the method for implanted dopant to regulate threshold voltage, can only come the threshold value of trim by the work function that changes grid, and the regulating power of gate electrode work function is had the higher requirement of ratio.
Up to now, the researcher has proposed multiple metal gate integrated technology, as single workfunction metal grid method, bimetallic method, metal counterdiffusion method, monometallic double work function method, full silicidation method.In these methods,, make it become a kind of technology that gets a good chance of being applied to metal gate preparation technology of future generation because simple, the preparation technology of full silicidation method gate work function control method is simple, good with the CMOS processing compatibility.
Initial full silicidation method adopts usually injects conventional impurity (B, BF 2, As, P, Sb) wait the work function of regulating the full silicidation metal gate.But the gate work function regulating power of discovering conventional impurity is limited, can't satisfy the requirement of high-performance body silicon complementary MOS device (CMOS) to the gate electrode work function; And the As, the Sb impurity that inject also can cause the adhesion problem between gate medium and the gate electrode.In order to satisfy the requirement of high-performance complementary mos device (CMOS), need to seek the gate work function that new impurity is regulated the full silicidation metal gate to the gate electrode work function.New impurity should obtain bigger gate work function regulating power, also want can with the CMOS process compatible, be easy to be integrated in the CMOS technology and go.Discover the grid difficult adjusting of work function altogether of PMOS device, therefore be necessary to seek full silicidation metal gate work function control method new, that be easy to integrated PMOS device.
Summary of the invention
The object of the present invention is to provide a kind of be easy to integrated, with the method for the good adjusting PMOS device full silicidation metal gate gate work function of CMOS processing compatibility.
To achieve these goals, the present invention utilizes ion implantation technique implanted dopant aluminium (Al) and activator impurity in silication forward direction polysilicon gate, then depositing metal nickel (Ni) and carry out rapid thermal annealing (RTA) and make metallic nickel and polysilicon complete reaction form full-silicide metal gate; Simultaneously the full silicidation process is with impurity aluminum (Al) fractional condensation to fully silicided (fusi) gate/gate medium near interface and the oxygen that the injects formation Al-O that reacts xKey, the Al of this moment are that the form with oxidation state exists.Al-O xKey is forming electric dipole (dipole) at the interface, forms an internal field, thereby has changed band structure at the interface, causes the gate electrode work function to increase, thereby regulates the gate work function of full silicidation metal gate.
The concrete technical scheme that adopts comprises the steps:
1) carrying out local oxide isolation or shallow-trench isolation are injected preceding oxidation, inject then 14N +
2) rinse the preceding oxide-film of injection, gate oxidation, and deposit spathic silicon;
3) photoetching, etching form polygate electrodes;
4) inject Al impurity, impurity activation;
5) depositing metal nickel, the annealing silication makes metallic nickel and polysilicon complete reaction form full-silicide metal gate;
6) select to remove unreacted metal nickel.
In the technique scheme, in the step of described carrying out local oxide isolation or shallow-trench isolation, oxidizing temperature is 1000 ℃, separation layer thickness be 3000 to
Figure G2009102437394D00031
The step of oxidation before the described injection, oxide thickness be 100 to Described injection 14N +Step in, injection condition is: inject energy and be 10 to 35Kev, implantation dosage is 1 * 10 14To 8 * 10 14Cm -2
In the technique scheme, the described step of injecting preceding oxide-film that rinses, the employing volume ratio is H 2O: HF=9: 1 solution carries out rinsing, adopts 3 then #Corrosive liquid cleaned 10 minutes, and 1 #Corrosive liquid cleaned 5 minutes, and dipping is 5 minutes under the HF/ isopropyl alcohol IPA solution room temperature; These are 3 years old #Corrosive liquid is that volume ratio is 3-5: 1 H 2SO 4With H 2O 2Solution; This is 1 years old #Corrosive liquid is that volume ratio is 1-0.7: 1: 5 NH 4OH+H 2O 2+ H 2O solution; Hydrofluoric acid/isopropanol is that volume ratio is percent 0.2-1: percent 0.01-0.08: 1 HF+IPA+H 2O solution.
In the technique scheme, in the step of described gate oxidation and deposit spathic silicon, the thickness of gate oxidation be 15 to
Figure G2009102437394D00033
Deposit spathic silicon adopts chemical vapor deposition LPCVD method, the thickness of the polysilicon of deposition be 1000 to
Figure G2009102437394D00034
In the technique scheme, describedly before forming polygate electrodes, photoetching, etching further comprise: remove back side polysilicon, and rinse back side oxide layer, carry out the back side then and inject implanted dopant 31P injects energy and is 50 to 100Kev, and implantation dosage is 3 * 10 15To 6 * 10 15Cm -2
In the technique scheme, described step at photoetching, etching formation polygate electrodes comprises: employing thickness is that 1.5 microns 9918 glue carry out photoetching as mask, adopt the reactive ion etching polysilicon, the on-site etching polysilicon is clean, form polygate electrodes.
In the technique scheme, the step of described injection Al impurity, the impurity of injection is aluminium, and impurity aluminum is injected in the polysilicon gate, injects energy and be 30 to 90Kev, implantation dosage is 1 * 10 15To 8 * 10 15Cm -2
In the technique scheme, in the step of described impurity activation, adopt annealing to activate implanted dopant, 950 to 1050 ℃ of annealing temperatures, annealing time 3 seconds to 10 seconds.
In the technique scheme, in the step of the described depositing metal nickel and the silication of annealing, the thickness of depositing metal nickel be 600 to Annealing conditions is: 500 to 580 ℃ of temperature, 30 to 60 seconds time.
In the technique scheme, described selection is removed in the step of unreacted metal nickel, adopts 3 #Corrosive liquid carries out erosion removal unreacted metal nickel, and these are 3 years old #Corrosive liquid is volume ratio (3～5): 1 H 2SO 4With H 2O 2Solution, etching time are 20 to 30 minutes.
Beneficial effect of the present invention:
The present invention utilizes ion implantation technique implanted dopant aluminium (Al) in silication forward direction polysilicon gate, then depositing metal nickel (Ni) and carry out rapid thermal annealing (RTA) and make metallic nickel and polysilicon complete reaction form full-silicide metal gate; Simultaneously the full silicidation process is with impurity aluminum (Al) fractional condensation to fully silicided (fusi) gate/gate medium near interface and the oxygen that the injects formation Al-O that reacts xKey, the Al of this moment are that the form with oxidation state exists.Al-O xKey is forming electric dipole (dipole) at the interface, forms an internal field, thereby has changed band structure at the interface, causes the gate electrode work function to increase, thereby regulates the gate work function of PMOS full silicidation metal gate.
In addition, the method for the gate work function of adjusting metal gate provided by the invention, be easy to integrated, good with the CMOS processing compatibility.
Description of drawings
Fig. 1 is the method flow diagram of adjusting P type full silicidation metal gate electric capacity gate work function provided by the invention;
Fig. 2 a-Fig. 2 e is the step of preparation process that the present invention prepares P type full silicidation metal gate electric capacity; Wherein:
(a) be the structure that forms after deposit polysilicon and photoetching, the etching; (b) inject schematic diagram for Al impurity; (c) be depositing metal (Ni) back schematic diagram; (d) generate (Ni) metal silicide gate electrode schematic diagram for the silicidation anneal reaction; (e) for selecting to remove unreacted metal (Ni) back schematic diagram;
Symbol description among Fig. 2:
1-body silicon substrate, the 2-gate oxide, the 3-polygate electrodes, 4-LOCOS isolates, and the 5-ion injects the Al element, 6-metals deposited (Ni), (Ni) metal silicide gate electrode that the 7-reaction generates;
Fig. 3 is the TEM figure of the prepared metal gate electrode of the present invention;
Fig. 4 is the CV characteristic curve that injects Al impurity electric capacity in the grid that utilize the present invention to prepare.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the method flow diagram of adjusting P type full silicidation metal gate electric capacity gate work function provided by the invention, and this method comprises:
Step 101: carrying out local oxide isolation or shallow-trench isolation, inject preceding oxidation, inject then 14N +
In this step, when carrying out local oxide isolation or shallow-trench isolation, oxidizing temperature is 1000 ℃, separation layer thickness be 3000 to
Figure G2009102437394D00051
Before injecting the oxide thickness of oxidation be 100 to
Figure G2009102437394D00052
Inject 14N +Injection condition be: inject energy and be 10 to 35Kev, implantation dosage is 1 * 10 14To 8 * 10 14Cm -2
Step 102: rinse and inject preceding oxide-film, gate oxidation, and deposit spathic silicon;
In this step, rinsing the preceding oxide-film employing of injection volume ratio is H 2O: HF=9: 1 solution carries out rinsing, adopts 3 then #Corrosive liquid cleaned 10 minutes, and 1 #Corrosive liquid cleaned 5 minutes, and dipping is 5 minutes under the HF/ isopropyl alcohol IPA solution room temperature; These are 3 years old #Corrosive liquid is that volume ratio is 3-5: 1 H 2SO 4With H 2O 2Solution; This is 1 years old #Corrosive liquid is that volume ratio is 1-0.7: 1: 5 NH 4OH+H 2O 2+ H 2O solution; Hydrofluoric acid/isopropanol is that volume ratio is percent 0.2-1: percent 0.01-0.08: 1 HF+IPA+H 2O solution.In the step of gate oxidation and deposit spathic silicon, the thickness of gate oxidation be 15 to
Figure G2009102437394D00053
Deposit spathic silicon adopts chemical vapor deposition LPCVD method, the thickness of the polysilicon of deposition be 1000 to
Figure G2009102437394D00054
Step 103: photoetching, etching form polygate electrodes;
In this step, employing thickness is that 1.5 microns 9918 glue carry out photoetching as mask, adopts the reactive ion etching polysilicon, and the on-site etching polysilicon is clean, forms polygate electrodes.
Further comprise before forming polygate electrodes in photoetching, etching: remove back side polysilicon, and rinse back side oxide layer, carry out the back side then and inject implanted dopant 31P injects energy and is 50 to 100Kev, and implantation dosage is 3 * 10 15To 6 * 10 15Cm -2
Step 104: inject Al impurity, impurity activation;
In this step, the impurity of injection is aluminium, and impurity aluminum is injected in the polysilicon gate, injects energy and be 30 to 90Kev, and implantation dosage is 1 * 10 15To 8 * 10 15Cm -2Impurity activation adopts annealing to activate implanted dopant, and annealing conditions is: 950 to 1050 ℃ of temperature, 3 seconds to 10 seconds time.
Step 105: depositing metal nickel, the annealing silication makes metallic nickel and polysilicon complete reaction form full-silicide metal gate;
In this step, the thickness of depositing metal nickel be 600 to
Figure G2009102437394D00061
Annealing conditions is: 500 to 580 ℃ of temperature, 30 to 60 seconds time.
Step 106: select to remove unreacted metal nickel.
In this step, adopt 3 #Corrosive liquid carries out erosion removal unreacted metal nickel, and these are 3 years old #Corrosive liquid is volume ratio 3-5: 1 H 2SO 4With H 2O 2Solution, etching time are 20 to 30 minutes.
Fig. 2 a-e is the processing step that the present invention prepares P type full silicidation metal gate electric capacity.Wherein:
(a) be the mos capacitance structure that forms after deposit polysilicon and photoetching, the etching; (b) inject schematic diagram for impurity; (c) be depositing metal (Ni) back schematic diagram; (d) generate (Ni) metal silicide gate electrode schematic diagram for the silicidation anneal reaction; (e) for selecting to remove unreacted metal (Ni) back schematic diagram.This technology specifically may further comprise the steps:
Step 1 a: oxidation: 1000 ℃,
Step 2: oxidation before injecting: thick
Figure G2009102437394D00063
Step 3: inject 14N +, energy is 10-35Kev, dosage is 1 * 10 14Cm -2-8 * 10 14Cm -2
Step 4: rinse and inject preceding oxide layer: H 2O: HF=9: rinse in 1 solution;
Step 5: clean: 3 #Liquid cleaned 10 minutes, and 1 #Liquid cleaned 5 minutes, HF/ isopropyl alcohol (IPA), and dipping is 5 minutes under the room temperature;
Step 6: gate oxidation: thickness
Figure G2009102437394D00064
Step 7: chemical vapor deposition (LPCVD) polysilicon:
Figure G2009102437394D00065
Step 8: remove back side polysilicon, and rinse back side oxide layer;
Step 9: the back side is injected: implanted dopant 31P, energy 50-100Kev, dosage 3 * 10 15-6 * 10 15
Step 10: photoetching polysilicon: 9918 glue, 1.5 microns;
Step 11: reactive ion etching polysilicon: clean polysilicon is carved in the place;
Step 12: grid inject: implanted dopant Al, inject energy 60Kev, dosage 4 * 10 15Cm -2
Step 13: impurity activation: 950 to 1050 ℃ of annealing temperatures, annealing time 3 seconds to 10 seconds;
Step 14: splash-proofing sputtering metal nickel (Ni): thickness,
Figure G2009102437394D00071
Step 15: rapid thermal annealing (RTA): temperature 500-580 ℃, time 30-60 second;
Step 16: selective etching: 3# liquid (H 2SO 4: H 2O 2=5: 1), 20-30 minute, unreacted metal nickel (Ni) is removed;
Fig. 3 is the TEM figure of the prepared full silicidation metal gate electrode of the present invention, and as can be seen from the figure polygate electrodes has changed the silicide metals gate electrode fully into.
Fig. 4 is the CV characteristic curve that utilizes the electric capacity that the present invention prepares, therefrom as can be seen in the grid behind the implanted dopant Al CV curve be offset flat band voltage (V Fb) variation reflected that the gate work function of gate electrode changes; In scope of experiment, the flat band voltage maximum of the more unadulterated electric capacity of flat band voltage of electric capacity has changed about 0.3V behind the injection Al; By calculating, work function can be adjusted to 4.639eV.
More than with specific embodiment purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all; any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1.一种适用于PMOS器件全硅化金属栅功函数的调节的方法，其主要步骤包括：1. A method applicable to the adjustment of the work function of the fully silicided metal gate of a PMOS device, the main steps of which include: 1)局部氧化隔离或浅槽隔离，进行注入前氧化，然后注入14N+；1) Local oxidation isolation or shallow trench isolation, oxidation before implantation, and then implantation of 14 N + ; 2)漂净注入前氧化膜，栅氧化，并沉积多晶硅；2) Rinse the oxide film before implantation, oxidize the gate, and deposit polysilicon; 3)光刻、刻蚀形成多晶硅栅电极；3) Photolithography and etching to form polysilicon gate electrodes; 4)注入Al杂质，杂质激活；4) Al impurity is injected to activate the impurity; 5)淀积金属镍，退火硅化，使金属镍和多晶硅完全反应形成全硅化物金属栅；5) Deposit metal nickel, anneal and silicidate, so that metal nickel and polysilicon completely react to form a full silicide metal gate; 6)选择去除未反应的金属镍。6) Selectively remove unreacted metallic nickel. 2.根据权利要求1所述的方法，其中，所述局部氧化隔离或浅槽隔离的步骤中，氧化温度为800-1000℃，隔离层厚度为 2. The method according to claim 1, wherein, in the step of local oxidation isolation or shallow trench isolation, the oxidation temperature is 800-1000° C., and the thickness of the isolation layer is 所述注入前氧化的步骤中，氧化厚度为 In the step of oxidation before injection, the oxidation thickness is 所述注入14N+的步骤中，注入条件为：注入能量为10-35Kev，注入剂量为1×1014-8×1014cm-2。In the step of implanting 14 N + , the implantation conditions are: implantation energy is 10-35Kev, and implantation dose is 1×10 14 -8×10 14 cm -2 . 3.根据权利要求1所述的方法，其中，所述漂净注入前氧化膜的步骤中，采用体积比为H2O∶HF＝6-9∶4-1的溶液进行漂洗，然后采用3#腐蚀液清洗6-10分钟，1#腐蚀液清洗3-5分钟，HF/异丙醇IPA溶液室温下浸渍3-5分钟；该3#腐蚀液是体积比为3-5∶1的H2SO4与H2O2溶液；该1#腐蚀液是体积比为1-0.7∶1∶5的NH4OH+H2O2+H2O溶液；氢氟酸/异丙醇/水是体积比为0.2-1％∶0.01-0.08％∶1的HF+IPA+H2O溶液。3. The method according to claim 1, wherein, in the step of rinsing the oxide film before injection, a solution with a volume ratio of H 2 O:HF=6-9:4-1 is used for rinsing, and then 3 # Corrosion solution cleaning for 6-10 minutes, 1 # corrosion solution cleaning for 3-5 minutes, HF/isopropanol IPA solution at room temperature for 3-5 minutes; the 3 # corrosion solution is H with a volume ratio of 3-5:1 2 SO 4 and H 2 O 2 solution; the 1 # corrosion solution is NH 4 OH+H 2 O 2 +H 2 O solution with a volume ratio of 1-0.7:1:5; hydrofluoric acid/isopropanol/water It is a HF+IPA+H 2 O solution with a volume ratio of 0.2-1%:0.01-0.08%:1. 4.根据权利要求1所述的方法，其中，所述栅氧化并沉积多晶硅的步骤中，栅氧化的厚度为
Figure F2009102437394C00013
沉积多晶硅采用化学气相淀积方法，沉积的多晶硅的厚度为
Figure F2009102437394C00014
4. The method according to claim 1, wherein, in the step of gate oxidation and polysilicon deposition, the thickness of the gate oxide is
Figure F2009102437394C00013
Polysilicon is deposited by chemical vapor deposition, and the thickness of the deposited polysilicon is
Figure F2009102437394C00014
 5.根据权利要求1所述的的方法，其中，所述在光刻、刻蚀形成多晶硅栅电极之前包括：5. The method according to claim 1, wherein said forming the polysilicon gate electrode before photolithography and etching comprises: 去背面多晶硅，并漂净背面氧化层，然后进行背面注入，注入杂质31P，注入能量为50-100Kev，注入剂量为3×1015-6×1015cm-2。Remove the polysilicon on the back, and rinse the oxide layer on the back, and then implant the impurity 31 P, the implant energy is 50-100Kev, and the implant dose is 3×10 15 -6×10 15 cm -2 . 6.根据权利要求1所述的的方法，其中，所述在光刻、刻蚀形成多晶硅栅电极的步骤包括：6. The method according to claim 1, wherein the step of forming a polysilicon gate electrode in photolithography and etching comprises: 采用厚度为1.0-1.5微米的9918胶作为掩模进行光刻，采用反应离子刻蚀多晶硅，将场区内多晶硅刻蚀干净，形成多晶硅栅电极。The 9918 glue with a thickness of 1.0-1.5 microns is used as a mask for photolithography, and the polysilicon is etched by reactive ion etching to etch the polysilicon in the field area to form a polysilicon gate electrode. 7.根据权利要求1所述的的方法，其中，所述注入Al杂质的步骤中，注入的杂质为铝，将杂质铝注入多晶硅栅内，注入能量为30-90Kev，注入剂量为1×1015-8×1015cm-2。7. The method according to claim 1, wherein, in the step of implanting Al impurities, the implanted impurities are aluminum, the impurity aluminum is implanted into the polysilicon gate, the implantation energy is 30-90Kev, and the implantation dose is 1×10 15 -8×10 15 cm -2 . 8.根据权利要求1所述的的方法，其中，所述杂质激活的步骤中，采用退火激活注入杂质，退火温度950-1050℃，退火时间3秒-10秒。8 . The method according to claim 1 , wherein, in the impurity activation step, annealing is used to activate the implanted impurity, the annealing temperature is 950-1050° C., and the annealing time is 3 seconds-10 seconds. 9.根据权利要求1所述的的方法，其中，所述淀积金属镍并退火硅化的步骤中，淀积金属镍的厚度为
Figure F2009102437394C00021
退火温度500-580℃，退火时间30-60秒。9. The method according to claim 1, wherein, in the step of depositing metallic nickel and annealing and siliciding, the thickness of depositing metallic nickel is
Figure F2009102437394C00021
The annealing temperature is 500-580°C, and the annealing time is 30-60 seconds. 10.根据权利要求1所述的的方法，其中，所述选择去除未反应的金属镍的步骤中，采用3#腐蚀液进行腐蚀去除未反应的金属镍，该3#腐蚀液为体积比3-5∶1的H2SO4与H2O2溶液，腐蚀时间为20至30分钟。10. The method according to claim 1, wherein, in the step of described selective removal of unreacted metallic nickel, adopt 3 # corrosion solution to corrode and remove unreacted metallic nickel, and this 3 # corrosion solution is a volume ratio of 3 - 5: 1 H2SO4 to H2O2 solution , etch time 20 to 30 minutes.
CN2009102437394A 2009-12-23 2009-12-23 Adjustment method for fully silicided metal gate work function for PMOS devices Pending CN102110598A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531540A (en) * 2012-07-02 2014-01-22 中国科学院微电子研究所 Semiconductor device manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531540A (en) * 2012-07-02 2014-01-22 中国科学院微电子研究所 Semiconductor device manufacturing method
CN103531540B (en) * 2012-07-02 2016-06-08 中国科学院微电子研究所 Semiconductor device manufacturing method

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Application publication date: 20110629