CN102110598A - Method for adjusting full silicification metal gate work function of PMOS (P-channel metal oxide semiconductor) device - Google Patents
Method for adjusting full silicification metal gate work function of PMOS (P-channel metal oxide semiconductor) device Download PDFInfo
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- CN102110598A CN102110598A CN2009102437394A CN200910243739A CN102110598A CN 102110598 A CN102110598 A CN 102110598A CN 2009102437394 A CN2009102437394 A CN 2009102437394A CN 200910243739 A CN200910243739 A CN 200910243739A CN 102110598 A CN102110598 A CN 102110598A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 61
- 239000002184 metal Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 50
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- 150000004706 metal oxides Chemical class 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 title description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 239000012535 impurity Substances 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 22
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 22
- 238000000137 annealing Methods 0.000 claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 20
- 239000007924 injection Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 18
- 238000001259 photo etching Methods 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 10
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N isopropyl alcohol Natural products CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 29
- 239000007788 liquid Substances 0.000 claims description 21
- 239000000243 solution Substances 0.000 claims description 20
- 239000002019 doping agent Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 230000004913 activation Effects 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000007598 dipping method Methods 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 4
- 125000001449 isopropyl group Chemical group [H]C([H])([H])C([H])(*)C([H])([H])[H] 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 5
- 239000007943 implant Substances 0.000 abstract 2
- 230000003213 activating effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000004151 rapid thermal annealing Methods 0.000 description 6
- 230000001105 regulatory effect Effects 0.000 description 5
- 229910018516 Al—O Inorganic materials 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 241000027294 Fusi Species 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000009833 condensation Methods 0.000 description 2
- 230000005494 condensation Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- -1 silicide metals Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
A method for adjusting the work function of a fully silicided metal gate suitable for a PMOS device comprises the following steps: local oxidation isolation or shallow trench isolation, pre-implant oxidation, and then implant14N+(ii) a Rinsing the oxide film before injection, oxidizing the gate, and depositing polysilicon; photoetching and etching to form a polysilicon gate electrode; injecting Al impurities, and activating the impurities; depositing metal nickel, annealing and silicifying to enable the metal nickel and the polycrystalline silicon to completely react to form a full-silicide metal gate; and selectively removing unreacted metallic nickel. The method provided by the invention is easy to integrate and realizes good compatibility with a CMOS process.
Description
Technical field
The present invention relates to microelectronics sub-micro technology complementation metal oxide semiconductor device (CMOS) and vlsi technology field, be meant a kind of method that is used to regulate PMOS device full silicidation metal gate gate work function especially.
Background technology
Along with the development of microelectric technique, traditional polygate electrodes can not satisfy the requirement of nano-device.There is following problem in the nano-device polygate electrodes:
The boron penetration effects of a, PMOS pipe;
B, depletion of polysilicon effect;
C, grid series resistance are excessive;
There is Fermi's pinning effect in d, incompatible with gate dielectric material of future generation (high-dielectric-coefficient grid medium).
And metal gate electrode can be good at solving the above problem that polygate electrodes exists, and becomes the replacer of polygate electrodes, and becomes the focus of research in the world.
But the preparation metal gate device also has a lot of problems to need to solve.At first the factor of Kao Lving is exactly the selection problem of grid material.When which kind of material decision selects as grid material, to consider several factors.Such as:
1) with the compatibility of CMOS technology (as thermal stability, but etching etc.);
2) to the influence of gate medium reliability;
3) extensibility of technology (as high-dielectric-coefficient grid medium).
Except top factor, the factor of the main consideration of selection is the matching problem of suitable gate work function.
Because gate work function directly influences the threshold voltage (V of device
Th) and transistorized performance.In order to obtain good performance, must select suitable gate work function to make the threshold voltage symmetry of NMOS and PMOS pipe also suitably low.For the device of advanced person's new construction, gate work function is particularly important.These new device structures much are operated under the mode of operation that exhausts entirely.The very low even not doping of substrate doping.The threshold value that can avoiding like this mixes causes is floated, and reduces the scattering process of impurity to the channel region charge carrier, improves the mobility of charge carrier rate, obtains higher drive current.But the result who does like this can not adopt in raceway groove the method for implanted dopant to regulate threshold voltage, can only come the threshold value of trim by the work function that changes grid, and the regulating power of gate electrode work function is had the higher requirement of ratio.
Up to now, the researcher has proposed multiple metal gate integrated technology, as single workfunction metal grid method, bimetallic method, metal counterdiffusion method, monometallic double work function method, full silicidation method.In these methods,, make it become a kind of technology that gets a good chance of being applied to metal gate preparation technology of future generation because simple, the preparation technology of full silicidation method gate work function control method is simple, good with the CMOS processing compatibility.
Initial full silicidation method adopts usually injects conventional impurity (B, BF
2, As, P, Sb) wait the work function of regulating the full silicidation metal gate.But the gate work function regulating power of discovering conventional impurity is limited, can't satisfy the requirement of high-performance body silicon complementary MOS device (CMOS) to the gate electrode work function; And the As, the Sb impurity that inject also can cause the adhesion problem between gate medium and the gate electrode.In order to satisfy the requirement of high-performance complementary mos device (CMOS), need to seek the gate work function that new impurity is regulated the full silicidation metal gate to the gate electrode work function.New impurity should obtain bigger gate work function regulating power, also want can with the CMOS process compatible, be easy to be integrated in the CMOS technology and go.Discover the grid difficult adjusting of work function altogether of PMOS device, therefore be necessary to seek full silicidation metal gate work function control method new, that be easy to integrated PMOS device.
Summary of the invention
The object of the present invention is to provide a kind of be easy to integrated, with the method for the good adjusting PMOS device full silicidation metal gate gate work function of CMOS processing compatibility.
To achieve these goals, the present invention utilizes ion implantation technique implanted dopant aluminium (Al) and activator impurity in silication forward direction polysilicon gate, then depositing metal nickel (Ni) and carry out rapid thermal annealing (RTA) and make metallic nickel and polysilicon complete reaction form full-silicide metal gate; Simultaneously the full silicidation process is with impurity aluminum (Al) fractional condensation to fully silicided (fusi) gate/gate medium near interface and the oxygen that the injects formation Al-O that reacts
xKey, the Al of this moment are that the form with oxidation state exists.Al-O
xKey is forming electric dipole (dipole) at the interface, forms an internal field, thereby has changed band structure at the interface, causes the gate electrode work function to increase, thereby regulates the gate work function of full silicidation metal gate.
The concrete technical scheme that adopts comprises the steps:
1) carrying out local oxide isolation or shallow-trench isolation are injected preceding oxidation, inject then
14N
+
2) rinse the preceding oxide-film of injection, gate oxidation, and deposit spathic silicon;
3) photoetching, etching form polygate electrodes;
4) inject Al impurity, impurity activation;
5) depositing metal nickel, the annealing silication makes metallic nickel and polysilicon complete reaction form full-silicide metal gate;
6) select to remove unreacted metal nickel.
In the technique scheme, in the step of described carrying out local oxide isolation or shallow-trench isolation, oxidizing temperature is 1000 ℃, separation layer thickness be 3000 to
The step of oxidation before the described injection, oxide thickness be 100 to
Described injection
14N
+Step in, injection condition is: inject energy and be 10 to 35Kev, implantation dosage is 1 * 10
14To 8 * 10
14Cm
-2
In the technique scheme, the described step of injecting preceding oxide-film that rinses, the employing volume ratio is H
2O: HF=9: 1 solution carries out rinsing, adopts 3 then
#Corrosive liquid cleaned 10 minutes, and 1
#Corrosive liquid cleaned 5 minutes, and dipping is 5 minutes under the HF/ isopropyl alcohol IPA solution room temperature; These are 3 years old
#Corrosive liquid is that volume ratio is 3-5: 1 H
2SO
4With H
2O
2Solution; This is 1 years old
#Corrosive liquid is that volume ratio is 1-0.7: 1: 5 NH
4OH+H
2O
2+ H
2O solution; Hydrofluoric acid/isopropanol is that volume ratio is percent 0.2-1: percent 0.01-0.08: 1 HF+IPA+H
2O solution.
In the technique scheme, in the step of described gate oxidation and deposit spathic silicon, the thickness of gate oxidation be 15 to
Deposit spathic silicon adopts chemical vapor deposition LPCVD method, the thickness of the polysilicon of deposition be 1000 to
In the technique scheme, describedly before forming polygate electrodes, photoetching, etching further comprise: remove back side polysilicon, and rinse back side oxide layer, carry out the back side then and inject implanted dopant
31P injects energy and is 50 to 100Kev, and implantation dosage is 3 * 10
15To 6 * 10
15Cm
-2
In the technique scheme, described step at photoetching, etching formation polygate electrodes comprises: employing thickness is that 1.5 microns 9918 glue carry out photoetching as mask, adopt the reactive ion etching polysilicon, the on-site etching polysilicon is clean, form polygate electrodes.
In the technique scheme, the step of described injection Al impurity, the impurity of injection is aluminium, and impurity aluminum is injected in the polysilicon gate, injects energy and be 30 to 90Kev, implantation dosage is 1 * 10
15To 8 * 10
15Cm
-2
In the technique scheme, in the step of described impurity activation, adopt annealing to activate implanted dopant, 950 to 1050 ℃ of annealing temperatures, annealing time 3 seconds to 10 seconds.
In the technique scheme, in the step of the described depositing metal nickel and the silication of annealing, the thickness of depositing metal nickel be 600 to
Annealing conditions is: 500 to 580 ℃ of temperature, 30 to 60 seconds time.
In the technique scheme, described selection is removed in the step of unreacted metal nickel, adopts 3
#Corrosive liquid carries out erosion removal unreacted metal nickel, and these are 3 years old
#Corrosive liquid is volume ratio (3～5): 1 H
2SO
4With H
2O
2Solution, etching time are 20 to 30 minutes.
Beneficial effect of the present invention:
The present invention utilizes ion implantation technique implanted dopant aluminium (Al) in silication forward direction polysilicon gate, then depositing metal nickel (Ni) and carry out rapid thermal annealing (RTA) and make metallic nickel and polysilicon complete reaction form full-silicide metal gate; Simultaneously the full silicidation process is with impurity aluminum (Al) fractional condensation to fully silicided (fusi) gate/gate medium near interface and the oxygen that the injects formation Al-O that reacts
xKey, the Al of this moment are that the form with oxidation state exists.Al-O
xKey is forming electric dipole (dipole) at the interface, forms an internal field, thereby has changed band structure at the interface, causes the gate electrode work function to increase, thereby regulates the gate work function of PMOS full silicidation metal gate.
In addition, the method for the gate work function of adjusting metal gate provided by the invention, be easy to integrated, good with the CMOS processing compatibility.
Description of drawings
Fig. 1 is the method flow diagram of adjusting P type full silicidation metal gate electric capacity gate work function provided by the invention;
Fig. 2 a-Fig. 2 e is the step of preparation process that the present invention prepares P type full silicidation metal gate electric capacity; Wherein:
(a) be the structure that forms after deposit polysilicon and photoetching, the etching; (b) inject schematic diagram for Al impurity; (c) be depositing metal (Ni) back schematic diagram; (d) generate (Ni) metal silicide gate electrode schematic diagram for the silicidation anneal reaction; (e) for selecting to remove unreacted metal (Ni) back schematic diagram;
Symbol description among Fig. 2:
1-body silicon substrate, the 2-gate oxide, the 3-polygate electrodes, 4-LOCOS isolates, and the 5-ion injects the Al element, 6-metals deposited (Ni), (Ni) metal silicide gate electrode that the 7-reaction generates;
Fig. 3 is the TEM figure of the prepared metal gate electrode of the present invention;
Fig. 4 is the CV characteristic curve that injects Al impurity electric capacity in the grid that utilize the present invention to prepare.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the method flow diagram of adjusting P type full silicidation metal gate electric capacity gate work function provided by the invention, and this method comprises:
Step 101: carrying out local oxide isolation or shallow-trench isolation, inject preceding oxidation, inject then
14N
+
In this step, when carrying out local oxide isolation or shallow-trench isolation, oxidizing temperature is 1000 ℃, separation layer thickness be 3000 to
Before injecting the oxide thickness of oxidation be 100 to
Inject
14N
+Injection condition be: inject energy and be 10 to 35Kev, implantation dosage is 1 * 10
14To 8 * 10
14Cm
-2
Step 102: rinse and inject preceding oxide-film, gate oxidation, and deposit spathic silicon;
In this step, rinsing the preceding oxide-film employing of injection volume ratio is H
2O: HF=9: 1 solution carries out rinsing, adopts 3 then
#Corrosive liquid cleaned 10 minutes, and 1
#Corrosive liquid cleaned 5 minutes, and dipping is 5 minutes under the HF/ isopropyl alcohol IPA solution room temperature; These are 3 years old
#Corrosive liquid is that volume ratio is 3-5: 1 H
2SO
4With H
2O
2Solution; This is 1 years old
#Corrosive liquid is that volume ratio is 1-0.7: 1: 5 NH
4OH+H
2O
2+ H
2O solution; Hydrofluoric acid/isopropanol is that volume ratio is percent 0.2-1: percent 0.01-0.08: 1 HF+IPA+H
2O solution.In the step of gate oxidation and deposit spathic silicon, the thickness of gate oxidation be 15 to
Deposit spathic silicon adopts chemical vapor deposition LPCVD method, the thickness of the polysilicon of deposition be 1000 to
Step 103: photoetching, etching form polygate electrodes;
In this step, employing thickness is that 1.5 microns 9918 glue carry out photoetching as mask, adopts the reactive ion etching polysilicon, and the on-site etching polysilicon is clean, forms polygate electrodes.
Further comprise before forming polygate electrodes in photoetching, etching: remove back side polysilicon, and rinse back side oxide layer, carry out the back side then and inject implanted dopant
31P injects energy and is 50 to 100Kev, and implantation dosage is 3 * 10
15To 6 * 10
15Cm
-2
Step 104: inject Al impurity, impurity activation;
In this step, the impurity of injection is aluminium, and impurity aluminum is injected in the polysilicon gate, injects energy and be 30 to 90Kev, and implantation dosage is 1 * 10
15To 8 * 10
15Cm
-2Impurity activation adopts annealing to activate implanted dopant, and annealing conditions is: 950 to 1050 ℃ of temperature, 3 seconds to 10 seconds time.
Step 105: depositing metal nickel, the annealing silication makes metallic nickel and polysilicon complete reaction form full-silicide metal gate;
In this step, the thickness of depositing metal nickel be 600 to
Annealing conditions is: 500 to 580 ℃ of temperature, 30 to 60 seconds time.
Step 106: select to remove unreacted metal nickel.
In this step, adopt 3
#Corrosive liquid carries out erosion removal unreacted metal nickel, and these are 3 years old
#Corrosive liquid is volume ratio 3-5: 1 H
2SO
4With H
2O
2Solution, etching time are 20 to 30 minutes.
Fig. 2 a-e is the processing step that the present invention prepares P type full silicidation metal gate electric capacity.Wherein:
(a) be the mos capacitance structure that forms after deposit polysilicon and photoetching, the etching; (b) inject schematic diagram for impurity; (c) be depositing metal (Ni) back schematic diagram; (d) generate (Ni) metal silicide gate electrode schematic diagram for the silicidation anneal reaction; (e) for selecting to remove unreacted metal (Ni) back schematic diagram.This technology specifically may further comprise the steps:
Step 1 a: oxidation: 1000 ℃,
Step 2: oxidation before injecting: thick
Step 3: inject
14N
+, energy is 10-35Kev, dosage is 1 * 10
14Cm
-2-8 * 10
14Cm
-2
Step 4: rinse and inject preceding oxide layer: H
2O: HF=9: rinse in 1 solution;
Step 5: clean: 3
#Liquid cleaned 10 minutes, and 1
#Liquid cleaned 5 minutes, HF/ isopropyl alcohol (IPA), and dipping is 5 minutes under the room temperature;
Step 6: gate oxidation: thickness
Step 7: chemical vapor deposition (LPCVD) polysilicon:
Step 8: remove back side polysilicon, and rinse back side oxide layer;
Step 9: the back side is injected: implanted dopant
31P, energy 50-100Kev, dosage 3 * 10
15-6 * 10
15
Step 10: photoetching polysilicon: 9918 glue, 1.5 microns;
Step 11: reactive ion etching polysilicon: clean polysilicon is carved in the place;
Step 12: grid inject: implanted dopant Al, inject energy 60Kev, dosage 4 * 10
15Cm
-2
Step 13: impurity activation: 950 to 1050 ℃ of annealing temperatures, annealing time 3 seconds to 10 seconds;
Step 14: splash-proofing sputtering metal nickel (Ni): thickness,
Step 15: rapid thermal annealing (RTA): temperature 500-580 ℃, time 30-60 second;
Step 16: selective etching: 3# liquid (H
2SO
4: H
2O
2=5: 1), 20-30 minute, unreacted metal nickel (Ni) is removed;
Fig. 3 is the TEM figure of the prepared full silicidation metal gate electrode of the present invention, and as can be seen from the figure polygate electrodes has changed the silicide metals gate electrode fully into.
Fig. 4 is the CV characteristic curve that utilizes the electric capacity that the present invention prepares, therefrom as can be seen in the grid behind the implanted dopant Al CV curve be offset flat band voltage (V
Fb) variation reflected that the gate work function of gate electrode changes; In scope of experiment, the flat band voltage maximum of the more unadulterated electric capacity of flat band voltage of electric capacity has changed about 0.3V behind the injection Al; By calculating, work function can be adjusted to 4.639eV.
More than with specific embodiment purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all; any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. method that is applicable to the adjusting of PMOS device full silicidation metal gate work function, its key step comprises:
1) carrying out local oxide isolation or shallow-trench isolation are injected preceding oxidation, inject then
14N
+
2) rinse the preceding oxide-film of injection, gate oxidation, and deposit spathic silicon;
3) photoetching, etching form polygate electrodes;
4) inject Al impurity, impurity activation;
5) depositing metal nickel, the annealing silication makes metallic nickel and polysilicon complete reaction form full-silicide metal gate;
6) select to remove unreacted metal nickel.
2. method according to claim 1, wherein, in the step of described carrying out local oxide isolation or shallow-trench isolation, oxidizing temperature is 800-1000 ℃, separation layer thickness is
The step of oxidation before the described injection, oxide thickness is
Described injection
14N
+Step in, injection condition is: the injection energy is 10-35Kev, implantation dosage is 1 * 10
14-8 * 10
14Cm
-2
3. method according to claim 1, wherein, the described step of injecting preceding oxide-film that rinses, the employing volume ratio is H
2The solution of O: HF=6-9: 4-1 carries out rinsing, adopts 3 then
#Corrosive liquid cleaned 6-10 minute, and 1
#Corrosive liquid cleaned 3-5 minute, and dipping is 3-5 minute under the HF/ isopropyl alcohol IPA solution room temperature; These are 3 years old
#Corrosive liquid is that volume ratio is 3-5: 1 H
2SO
4With H
2O
2Solution; This is 1 years old
#Corrosive liquid is that volume ratio is 1-0.7: 1: 5 NH
4OH+H
2O
2+ H
2O solution; Hydrofluoric acid/isopropanol is that volume ratio is 0.2-1%: 0.01-0.08%: 1 HF+IPA+H
2O solution.
4. method according to claim 1, wherein, in the step of described gate oxidation and deposit spathic silicon, the thickness of gate oxidation is
Deposit spathic silicon adopts chemical gas-phase deposition method, and the thickness of the polysilicon of deposition is
5. method according to claim 1 wherein, describedly comprised before photoetching, etching form polygate electrodes:
Remove back side polysilicon, and rinse back side oxide layer, carry out the back side then and inject implanted dopant
31P, the injection energy is 50-100Kev, implantation dosage is 3 * 10
15-6 * 10
15Cm
-2
6. method according to claim 1, wherein, described step at photoetching, etching formation polygate electrodes comprises:
Employing thickness is that 9918 glue of 1.0-1.5 micron carry out photoetching as mask, adopts the reactive ion etching polysilicon, and the on-site etching polysilicon is clean, forms polygate electrodes.
7. method according to claim 1, wherein, the step of described injection Al impurity, the impurity of injection is aluminium, and impurity aluminum is injected in the polysilicon gate, and the injection energy is 30-90Kev, and implantation dosage is 1 * 10
15-8 * 10
15Cm
-2
8. method according to claim 1 wherein, in the step of described impurity activation, adopts annealing to activate implanted dopant, annealing temperature 950-1050 ℃, annealing time 3 seconds-10 seconds.
9. method according to claim 1, wherein, in the step of the described depositing metal nickel and the silication of annealing, the thickness of depositing metal nickel is
Annealing temperature 500-580 ℃, annealing time 30-60 second.
10. method according to claim 1, wherein, described selection is removed in the step of unreacted metal nickel, adopts 3
#Corrosive liquid carries out erosion removal unreacted metal nickel, and these are 3 years old
#Corrosive liquid is volume ratio 3-5: 1 H
2SO
4With H
2O
2Solution, etching time are 20 to 30 minutes.
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|---|---|---|---|
| CN2009102437394A CN102110598A (en) | 2009-12-23 | 2009-12-23 | Method for adjusting full silicification metal gate work function of PMOS (P-channel metal oxide semiconductor) device |
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|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531540A (en) * | 2012-07-02 | 2014-01-22 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
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2009
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531540A (en) * | 2012-07-02 | 2014-01-22 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103531540B (en) * | 2012-07-02 | 2016-06-08 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
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Application publication date: 20110629 |