CN103065965B - A kind of manufacture method of semiconductor device - Google Patents
A kind of manufacture method of semiconductor device Download PDFInfo
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- CN103065965B CN103065965B CN201110320507.1A CN201110320507A CN103065965B CN 103065965 B CN103065965 B CN 103065965B CN 201110320507 A CN201110320507 A CN 201110320507A CN 103065965 B CN103065965 B CN 103065965B
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Abstract
The invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, be formed with grid structure on the semiconductor substrate; Form the first dielectric layer on the semiconductor substrate, at least cover described grid structure; Grind described first dielectric layer, expose the top of described grid structure; Deposition the first metal layer, at least covers the top of described grid structure, and performs the first annealing in process; Remove described the first metal layer and described first dielectric layer; Form the second dielectric layer on the semiconductor substrate, at least cover described grid structure; Etch described second dielectric layer, expose the source/drain region of described Semiconductor substrate and described grid structure; Depositing second metal layer, and perform the second annealing in process; Remove described second metal level and the second dielectric layer, and perform the 3rd annealing in process.According to the present invention, separately can form the self-aligned silicide of grid and source/drain region, make the thickness of the two different, simultaneously using the Ni containing different proportion Pt as the metal material forming self-aligned silicide, promote its electrology characteristic.
Description
Technical field
The present invention relates to semiconductor fabrication process, form the method for two self-aligned silicide (dualsalicide) in particular to one.
Background technology
Along with the development of CMOS manufacturing process, require to form for ultra-shallow junctions in integrated circuits to make junction leakage be reduced to minimum level, the reduction of source/drain region silicide thickness when this causes forming self-aligned silicide, thus, the thickness of grid silicide also reduces thereupon, thus causes the continuous rising of sheet resistance (Rs) and the decline of device performance.
For traditional self-aligned silicide formation process, the problems referred to above are that itself is intrinsic, because except non-usage metal material forms grid, for the grid (such as polysilicon gate) using other material to be formed, gate salicide and source/drain region self-aligned silicide are formed simultaneously.
Therefore, need to propose a kind of method, to form gate salicide and source/drain region self-aligned silicide respectively, while the self-aligned silicide thickness of reduction source/drain region, do not reduce the thickness of gate salicide, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, be formed with grid structure on the semiconductor substrate; Form the first dielectric layer on the semiconductor substrate, at least to cover described grid structure; Grind described first dielectric layer, to expose the top of described grid structure; Deposition the first metal layer, at least to cover the top of described grid structure, and performs the first annealing in process; Remove described the first metal layer and described first dielectric layer; Form one second dielectric layer on the semiconductor substrate, at least to cover described grid structure; Etch described second dielectric layer, to expose the source/drain region of described Semiconductor substrate and described grid structure; Depositing second metal layer, and perform the second annealing in process; Remove described second metal level and the second dielectric layer, and perform the 3rd annealing in process.
Further, the material of described first and second metal levels is nickel platinum alloy.
Further, the ratio of described platinum is 0-15%.
Further, the thickness of described first and second metal levels is 50-300 dust.
Further, in described second metal level, the ratio of platiniferous is different from the ratio of platiniferous in described the first metal layer.
Further, the thickness of described second metal level is different from the thickness of described the first metal layer.
Further, low-temperature rapid thermal annealing process is adopted to carry out described first and second annealing in process.
Further, the temperature of described first and second annealing in process is 200-350 DEG C.
Further, high-temperature quick thermal annealing technique is adopted to carry out described 3rd annealing in process.
Further, the temperature of described 3rd annealing in process is 300-600 DEG C.
Further, after the described the first metal layer of deposition or described second metal level, a protective layer is formed.
Further, the material of described protective layer is titanium nitride.
Further, the thickness of described protective layer is 50-200 dust.
Further, described first dielectric layer is the silicon nitride layer and oxide skin(coating) that stack gradually.
Further, described second dielectric layer is silicon nitride layer.
Further, wet clean process is adopted to remove described the first metal layer and described first dielectric layer, described second metal level and described second dielectric layer.
Further, dry etching is etched to described in.
Further, described grid structure comprises the gate dielectric and gate material layers that stack gradually.
According to the present invention, separately can form gate salicide and source/drain region self-aligned silicide, make the thickness of the two different, simultaneously using the Ni containing different proportion Pt as the metal material forming self-aligned silicide, promote the characteristic of two self-aligned silicide.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 I is the schematic cross sectional view of each step of the method for the two self-aligned silicide (dualsalicide) of formation that the present invention proposes;
Fig. 2 is the flow chart of the method for the two self-aligned silicide (dualsalicide) of formation that the present invention proposes.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the method for the two self-aligned silicide (dualsalicide) of formation that the present invention proposes.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Below, only for PMOS transistor, the detailed step of the method for the two self-aligned silicide (dualsalicide) of formation that the present invention proposes is described with reference to Figure 1A-Fig. 1 I and Fig. 2.
With reference to Figure 1A-Fig. 1 I, illustrated therein is the schematic cross sectional view of each step of the method for the two self-aligned silicide (dualsalicide) of formation that the present invention proposes.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.Exemplarily, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to form.Isolation channel, buried regions (not shown) etc. can also be formed with in described Semiconductor substrate 100.In addition, for PMOS transistor, N trap (not shown) in described Semiconductor substrate 100, can also be formed with, and before formation grid structure, low dose of boron can be carried out once to whole N trap and inject, for adjusting the threshold voltage V of PMOS transistor
th.
Described Semiconductor substrate 100 is formed with grid structure, and as an example, described grid structure can comprise the gate dielectric 101 and gate material layers 102 that stack gradually.The material of gate dielectric 101 can comprise oxide, e.g., and silicon dioxide (SiO
2).The material of gate material layers 102 can comprise polysilicon.As another example, described grid structure can be Semiconductor Oxide-Nitride Oxide-semiconductor (SONOS) layer stacked gate structure.
In addition, exemplarily, described Semiconductor substrate 100 can also be formed be positioned at grid structure both sides and near the clearance wall structure 103 of grid structure.Wherein, clearance wall structure 103 can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.In the present embodiment, clearance wall structure 103 may be used for the distance controlling metal silicide and raceway groove, is communicated with raceway groove to prevent metal silicide further.
Then, as shown in Figure 1B, described Semiconductor substrate 100 forms the first dielectric layer, described first dielectric layer is silicon nitride (SiN) layer 104 and oxide skin(coating) (such as SiO that are formed successively
2) 105, at least to cover described grid structure.The technique forming described silicon nitride layer 104 and oxide skin(coating) 105 can adopt process known in those skilled in the art, is no longer repeated at this.
It should be noted that at this, the minimum interface of the described oxide skin(coating) 105 of formation should higher than the top of described grid structure, and its effect prevents described grid structure stressed when the described silicon nitride layer 104 that next step grinding is formed and oxide skin(coating) 105 and lodges.In other embodiments, described oxide skin(coating) 105 can not be formed.
Then, as shown in Figure 1 C, chemical mechanical milling tech (CMP) is adopted to grind described silicon nitride layer 104 and oxide skin(coating) 105, until expose the top of described grid structure.
Then, as shown in figure ip, the first metal layer 106 is formed, to cover the top of described grid structure.The technique forming described the first metal layer 106 can adopt method conventional in this area, such as, and physical vaporous deposition or vapour deposition method etc.The material of described the first metal layer 106 is the nickel (Ni) containing certain proportion platinum (Pt), and described ratio is 0-15%.The thickness of described the first metal layer 106 is 50-300 dust.Meanwhile, can form protective layer on described the first metal layer 106, the material of described protective layer is the nitride of refractory metal, such as TiN, and the effect of described protective layer avoids described the first metal layer 106 be exposed to the environment of non-inert and be oxidized.The thickness of described protective layer is 50-200 dust.
Next, low-temperature rapid thermal annealing (RTA) technique is adopted to anneal to described the first metal layer 106.Annealed process, the material in the first metal layer 106 spreads in the silicon materials in described gate material layers 102, and forms metal silicide 107 with silicon materials.The temperature of described low-temperature rapid thermal annealing is 200-350 DEG C.
Then; as referring to figure 1e; the first metal layer 106 adopting wet clean process to remove successively not react with described gate material layers 102, be formed in silicon nitride layer 104 in described Semiconductor substrate 100 and oxide skin(coating) 105, the protective layer be formed on described the first metal layer 106 is also removed in the lump.
Then, as shown in fig. 1f, described Semiconductor substrate 100 forms the second dielectric layer, described second dielectric layer is silicon nitride layer 104, at least covers described grid structure.Next, display is not given in silicon nitride layer 104, figure described in patterning.
Then, as shown in Figure 1 G, etch described silicon nitride layer 104, expose the source/drain region of described Semiconductor substrate 100 and described grid structure.Described etching can adopt dry method etch technology known in those skilled in the art to carry out.
Then, as shown in fig. 1h, the second metal level 108 is formed, to cover described Semiconductor substrate 100.The technique forming described second metal level 109 can adopt method conventional in this area, such as, and physical vaporous deposition or vapour deposition method etc.The material of described second metal level 108 is the nickel (Ni) containing certain proportion platinum (Pt), and described ratio is 0-15%.The thickness of described second metal level 108 is 50-300 dust.Meanwhile, can form protective layer on described second metal level 108, the material of described protective layer is the nitride of refractory metal, such as TiN, and the effect of described protective layer avoids described second metal level 108 be exposed to the environment of non-inert and be oxidized.The thickness of described protective layer is 50-200 dust.
Next, low-temperature rapid thermal annealing (RTA) technique is adopted to anneal to described second metal level 108.Annealed process, the material in the second metal level 108 spreads in the silicon materials in described Semiconductor substrate 100, and forms metal silicide 109 with silicon materials.The temperature of described low-temperature rapid thermal annealing is 200-350 DEG C.
It should be noted that at this, the described the first metal layer 106 of formation is identical with the composition material of described second metal level 108, but wherein the ratio of contained Pt can be different, and the thickness simultaneously formed is different.
Then; as shown in Figure 1 I; adopt wet clean process to remove the second metal level 108 do not reacted with Semiconductor substrate 100, the silicon nitride layer 104 be formed in described Semiconductor substrate 100 successively, the protective layer be formed on described second metal level 108 is also removed in the lump.
Next, adopt high-temperature quick thermal annealing (RTA) technique to anneal to the described metal silicide 109 and 107 formed, complete the making of source/drain region and gate salicide.The temperature of described high-temperature quick thermal annealing is 300-600 DEG C.
So far, whole processing steps that method is according to an exemplary embodiment of the present invention implemented are completed.Next, can be completed the making of whole semiconductor device by subsequent technique, described subsequent technique is identical with traditional process for fabricating semiconductor device.According to the present invention, separately can form gate salicide and source/drain region self-aligned silicide, make the thickness of the two different, simultaneously using the Ni containing different proportion Pt as the metal material forming self-aligned silicide, promote the characteristic of two self-aligned silicide.
With reference to Fig. 2, illustrated therein is the flow chart of the method for the two self-aligned silicide (dualsalicide) of formation that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
In step 201, provide Semiconductor substrate, be formed with grid structure on the semiconductor substrate;
In step 202., form the first dielectric layer on the semiconductor substrate, at least to cover described grid structure;
In step 203, grind described first dielectric layer, to expose the top of described grid structure;
In step 204, deposition the first metal layer, at least to cover the top of described grid structure, and performs the first annealing in process;
In step 205, described the first metal layer and described first dielectric layer is removed;
In step 206, form the second dielectric layer on the semiconductor substrate, at least to cover described grid structure;
In step 207, etch described second dielectric layer, with in the source/drain region of exposing described Semiconductor substrate and described grid structure;
In a step 208, depositing second metal layer, and perform the second annealing in process;
In step 209, remove described second metal level and described second dielectric layer, and perform the 3rd annealing in process.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (17)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, is formed with grid structure on the semiconductor substrate;
Form the first dielectric layer on the semiconductor substrate, at least to cover described grid structure;
Grind described first dielectric layer, to expose the top of described grid structure;
Deposition the first metal layer, at least to cover the top of described grid structure, and performs the first annealing in process, to form the first metal silicide;
Remove described the first metal layer and described first dielectric layer;
Form one second dielectric layer on the semiconductor substrate, at least to cover described grid structure;
Etch described second dielectric layer, to expose the source/drain region of described Semiconductor substrate and described grid structure;
Depositing second metal layer, the thickness of described second metal level is less than the thickness of described the first metal layer, and performs the second annealing in process, to form the second metal silicide;
Remove described second metal level and the second dielectric layer, and perform the 3rd annealing in process, with the thickness making the thickness of described first metal silicide be greater than described second metal silicide.
2. method according to claim 1, is characterized in that, the material of described first and second metal levels is nickel platinum alloy.
3. method according to claim 2, is characterized in that, the ratio of described platinum is 0-15%.
4. method according to claim 1, is characterized in that, the thickness of described first and second metal levels is 50-300 dust.
5. method according to claim 2, is characterized in that, in described second metal level, the ratio of platiniferous is different from the ratio of platiniferous in described the first metal layer.
6. method according to claim 1, is characterized in that, adopts low-temperature rapid thermal annealing process to carry out described first and second annealing in process.
7. the method according to claim 1 or 6, is characterized in that, the temperature of described first and second annealing in process is 200-350 DEG C.
8. method according to claim 1, is characterized in that, adopts high-temperature quick thermal annealing technique to carry out described 3rd annealing in process.
9. the method according to claim 1 or 8, is characterized in that, the temperature of described 3rd annealing in process is 300-600 DEG C.
10. method according to claim 1, is characterized in that, after the described the first metal layer of deposition or described second metal level, forms a protective layer.
11. methods according to claim 10, is characterized in that, the material of described protective layer is titanium nitride.
12. methods according to claim 11, is characterized in that, the thickness of described protective layer is 50-200 dust.
13. methods according to claim 1, is characterized in that, described first dielectric layer is the silicon nitride layer and oxide skin(coating) that stack gradually.
14. methods according to claim 1, is characterized in that, described second dielectric layer is silicon nitride layer.
15. methods according to claim 1, is characterized in that, adopt wet clean process to remove described the first metal layer and described first dielectric layer, described second metal level and described second dielectric layer.
16. methods according to claim 1, is characterized in that, described in be etched to dry etching.
17. methods according to claim 1, is characterized in that, described grid structure comprises the gate dielectric and gate material layers that stack gradually.
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| CN109037051B (en) * | 2018-07-24 | 2021-02-12 | 武汉新芯集成电路制造有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN111128873B (en) * | 2019-12-30 | 2022-04-22 | 广州粤芯半导体技术有限公司 | Wafer surface metal alloying treatment method |
| CN115132604B (en) * | 2022-08-30 | 2022-11-25 | 广州粤芯半导体技术有限公司 | Silicide process monitoring method |
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| CN101123271A (en) * | 2006-08-11 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
| CN101496172A (en) * | 2005-05-24 | 2009-07-29 | 德克萨斯仪器股份有限公司 | Nickel silicide method and structure |
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| JP4822852B2 (en) * | 2006-01-17 | 2011-11-24 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| US20070249149A1 (en) * | 2006-04-21 | 2007-10-25 | International Business Machines Corporation | Improved thermal budget using nickel based silicides for enhanced semiconductor device performance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101496172A (en) * | 2005-05-24 | 2009-07-29 | 德克萨斯仪器股份有限公司 | Nickel silicide method and structure |
| CN101123271A (en) * | 2006-08-11 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
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