CN103065965A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN103065965A CN103065965A CN2011103205071A CN201110320507A CN103065965A CN 103065965 A CN103065965 A CN 103065965A CN 2011103205071 A CN2011103205071 A CN 2011103205071A CN 201110320507 A CN201110320507 A CN 201110320507A CN 103065965 A CN103065965 A CN 103065965A
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Abstract
The invention provides a semiconductor device manufacturing method which comprises that a semiconductor substrate is provided, a grid structure is formed on the semiconductor substrate; a first dielectric layer is formed on the semiconductor substrate and at least covers the grid structure; the first dielectric layer is ground, the top portion of the grid structure is exposed; a first metal layer is deposited and at least covers the top portion of the grid structure, and a first annealing process is carried out; the first metal layer and the first dielectric layer are removed; a second dielectric layer is formed on the semiconductor substrate and at least covers the grid structure; the second dielectric layer is etched, and a source/leakage zone of the semiconductor substrate and the grid structure are exposed; a second metal layer is deposited, and a second annealing process is carried out; the second metal layer and the second dielectric layer are removed, and a third annealing process is carried out. According to the semiconductor device manufacturing method, self-aligning silicide of a grid and the source/leakage zone can be respectively formed independently, the thicknesses of the two pieces of silicide are different, and meanwhile Ni containing Pt of different proportions is used as metal materials for the self-aligning silicide, and the electrical property of the self-aligning silicide is improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method that forms two self-aligned silicides (dual salicide).
Background technology
Development along with the CMOS manufacturing process, requirement forms super shallow junction in order to make junction leakage be reduced to minimum level in integrated circuit, the reduction of source when this causes forming self-aligned silicide/drain region silicide thickness, thus, the thickness of grid silicide also reduces thereupon, thereby causes the continuous rising of sheet resistance (Rs) and the decline of device performance.
Form technique for traditional self-aligned silicide, the problems referred to above are that itself is intrinsic, unless because use metal material to form grid, for the grid (for example polysilicon gate) that uses other material to form, grid self-aligned silicide and source/drain region self-aligned silicide forms simultaneously.
Therefore, need to propose a kind of method, to form respectively grid self-aligned silicide and source/drain region self-aligned silicide, in reduction source/drain region self-aligned silicide thickness, do not reduce the thickness of grid self-aligned silicide, to address the above problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, is formed with grid structure in described Semiconductor substrate; Form the first dielectric layer in described Semiconductor substrate, to cover at least described grid structure; Grind described the first dielectric layer, to expose the top of described grid structure; The deposition the first metal layer covering at least the top of described grid structure, and is carried out the first annealing in process; Remove described the first metal layer and described the first dielectric layer; Form one second dielectric layer in described Semiconductor substrate, to cover at least described grid structure; Described the second dielectric layer of etching is with source/drain region and the described grid structure that exposes described Semiconductor substrate; Deposit the second metal level, and carry out the second annealing in process; Remove described the second metal level and the second dielectric layer, and carry out the 3rd annealing in process.
Further, the material of described the first and second metal levels is the nickel platinum alloy.
Further, the ratio of described platinum is 0-15%.
Further, the thickness of described the first and second metal levels is the 50-300 dust.
Further, the ratio of platiniferous is different from the ratio of platiniferous in the described the first metal layer in described the second metal level.
Further, the thickness of described the second metal level is different from the thickness of described the first metal layer.
Further, adopt the low temperature rapid thermal anneal process to carry out described the first and second annealing in process.
Further, the temperature of described the first and second annealing in process is 200-350 ℃.
Further, adopt high-temperature quick thermal annealing technique to carry out described the 3rd annealing in process.
Further, the temperature of described the 3rd annealing in process is 300-600 ℃.
Further, after the described the first metal layer of deposition or described the second metal level, form a protective layer.
Further, the material of described protective layer is titanium nitride.
Further, the thickness of described protective layer is the 50-200 dust.
Further, described the first dielectric layer is silicon nitride layer and the oxide skin(coating) that stacks gradually.
Further, described the second dielectric layer is silicon nitride layer.
Further, adopt wet clean process to remove described the first metal layer and described the first dielectric layer, described the second metal level and described the second dielectric layer.
Further, the described dry etching that is etched to.
Further, described grid structure comprises gate dielectric and the gate material layers that stacks gradually.
According to the present invention, can form independently respectively grid self-aligned silicide and source/drain region self-aligned silicide, make the thickness of the two different, simultaneously with the Ni that contains different proportion Pt as the metal material that forms self-aligned silicide, promote the characteristic of two self-aligned silicides.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In the accompanying drawing:
Figure 1A-Fig. 1 I is the schematic cross sectional view of each step of the method for the two self-aligned silicides (dual salicide) of the formation that proposes of the present invention;
Fig. 2 is the flow chart of the method for the two self-aligned silicides (dual salicide) of the formation that proposes of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that the method for the two self-aligned silicides (dual salicide) of formation that explaination the present invention proposes in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination but do not get rid of.
Below, only take the PMOS transistor as example, the detailed step of the method for the two self-aligned silicides (dual salicide) of formation that the present invention proposes is described with reference to Figure 1A-Fig. 1 I and Fig. 2.
With reference to Figure 1A-Fig. 1 I, wherein show the schematic cross sectional view of each step of the method for the two self-aligned silicides (dual salicide) of formation that the present invention proposes.
At first, shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, is doped with the monocrystalline silicon of impurity, silicon-on-insulator (SOI) etc.As example, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to consist of.In described Semiconductor substrate 100, can also be formed with isolation channel, buried regions (not shown) etc.In addition, for the PMOS transistor, can also be formed with N trap (not shown) in the described Semiconductor substrate 100, and before forming grid structure, can carry out once low dose of boron to whole N trap and inject, be used for adjusting the transistorized threshold voltage V of PMOS
Th
Be formed with grid structure in described Semiconductor substrate 100, as an example, described grid structure can comprise gate dielectric 101 and the gate material layers 102 that stacks gradually.The material of gate dielectric 101 can comprise oxide, as, silicon dioxide (SiO
2).The material of gate material layers 102 can comprise polysilicon.As another example, described grid structure can be semiconductor-stacked grid structure of oxide-nitride thing-oxide-semiconductor (SONOS).
In addition, as example, on described Semiconductor substrate 100, can also be formed with and be positioned at the grid structure both sides and near the clearance wall structure 103 of grid structure.Wherein, clearance wall structure 103 can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.In the present embodiment, clearance wall structure 103 can be used for the distance of control metal silicide and raceway groove, is communicated with further to prevent metal silicide and raceway groove.
Then, as shown in Figure 1B, form the first dielectric layer in described Semiconductor substrate 100, described the first dielectric layer be the silicon nitride (SiN) that forms successively layers 104 and oxide skin(coating) (SiO for example
2) 105, to cover at least described grid structure.The technique that forms described silicon nitride layer 104 and oxide skin(coating) 105 can adopt process known in those skilled in the art, is no longer given unnecessary details at this.
Need to prove at this, the minimum interface of the described oxide skin(coating) 105 of formation should be higher than the top of described grid structure, and its effect is to prevent when next step described silicon nitride layer 104 that grind to form and oxide skin(coating) 105 that described grid structure is stressed and lodge.In other embodiments, can not form described oxide skin(coating) 105.
Then, shown in Fig. 1 C, adopt chemical mechanical milling tech (CMP) to grind described silicon nitride layer 104 and oxide skin(coating) 105, until expose the top of described grid structure.
Then, shown in Fig. 1 D, form the first metal layer 106, to cover the top of described grid structure.The technique that forms described the first metal layer 106 can adopt method commonly used in this area, for example, and physical vaporous deposition or vapour deposition method etc.The material of described the first metal layer 106 is for containing the nickel (Ni) of certain proportion platinum (Pt), and described ratio is 0-15%.The thickness of described the first metal layer 106 is the 50-300 dust.Simultaneously, can form protective layer at described the first metal layer 106, the material of described protective layer is the nitride of refractory metal, TiN for example, and the effect of described protective layer is to avoid described the first metal layer 106 to be exposed to the environment of non-inertia and oxidation occurs.The thickness of described protective layer is the 50-200 dust.
Next, adopt low temperature rapid thermal annealing (RTA) technique that described the first metal layer 106 is annealed.Spread in annealed processing, the material in the first metal layer 106 silicon materials in the described gate material layers 102, and form metal silicide 107 with silicon materials.The temperature of described low temperature rapid thermal annealing is 200-350 ℃.
Then; shown in Fig. 1 E; the first metal layer 106 that adopts wet clean process to remove successively not to react with described gate material layers 102, be formed on silicon nitride layer 104 and oxide skin(coating) 105 on the described Semiconductor substrate 100, the protective layer that is formed on the described the first metal layer 106 is also removed in the lump.
Then, shown in Fig. 1 F, form the second dielectric layer in described Semiconductor substrate 100, described the second dielectric layer is silicon nitride layer 104, covers at least described grid structure.Next, the described silicon nitride layer 104 of patterning does not give demonstration among the figure.
Then, shown in Fig. 1 G, the described silicon nitride layer 104 of etching exposes source/drain region and the described grid structure of described Semiconductor substrate 100.Described etching can adopt dry method etch technology known in those skilled in the art to carry out.
Then, shown in Fig. 1 H, form the second metal level 108, to cover described Semiconductor substrate 100.The technique that forms described the second metal level 109 can adopt method commonly used in this area, for example, and physical vaporous deposition or vapour deposition method etc.The material of described the second metal level 108 is for containing the nickel (Ni) of certain proportion platinum (Pt), and described ratio is 0-15%.The thickness of described the second metal level 108 is the 50-300 dust.Simultaneously, can form protective layer at described the second metal level 108, the material of described protective layer is the nitride of refractory metal, TiN for example, and the effect of described protective layer is to avoid described the second metal level 108 to be exposed to the environment of non-inertia and oxidation occurs.The thickness of described protective layer is the 50-200 dust.
Next, adopt low temperature rapid thermal annealing (RTA) technique that described the second metal level 108 is annealed.Spread in annealed processing, the material in the second metal level 108 silicon materials in the described Semiconductor substrate 100, and form metal silicide 109 with silicon materials.The temperature of described low temperature rapid thermal annealing is 200-350 ℃.
Need to prove at this, the described the first metal layer 106 of formation is identical with the composition material of described the second metal level 108, but wherein the ratio of contained Pt can be different, and the thickness that forms simultaneously is different.
Then; shown in Fig. 1 I; the second metal level 108 that adopts wet clean process to remove successively not to react with Semiconductor substrate 100, be formed on the silicon nitride layer 104 on the described Semiconductor substrate 100, the protective layer that is formed on described the second metal level 108 is also removed in the lump.
Next, adopt high-temperature quick thermal annealing (RTA) technique that the described metal silicide 109 and 107 that forms is annealed, finish the making of source/drain region and grid self-aligned silicide.The temperature of described high-temperature quick thermal annealing is 300-600 ℃.
So far, according to an exemplary embodiment of the present invention whole processing steps of method enforcement have been finished.Next, can finish by subsequent technique the making of whole semiconductor device, described subsequent technique and traditional process for fabricating semiconductor device are identical.According to the present invention, can form independently respectively grid self-aligned silicide and source/drain region self-aligned silicide, make the thickness of the two different, simultaneously with the Ni that contains different proportion Pt as the metal material that forms self-aligned silicide, promote the characteristic of two self-aligned silicides.
With reference to Fig. 2, wherein show the flow chart of the method for the two self-aligned silicides (dual salicide) of formation that the present invention proposes, be used for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, be formed with grid structure in described Semiconductor substrate;
In step 202, form the first dielectric layer in described Semiconductor substrate, to cover at least described grid structure;
In step 203, grind described the first dielectric layer, to expose the top of described grid structure;
In step 204, the deposition the first metal layer covering at least the top of described grid structure, and is carried out the first annealing in process;
In step 205, remove described the first metal layer and described the first dielectric layer;
In step 206, form the second dielectric layer in described Semiconductor substrate, to cover at least described grid structure;
In step 207, described the second dielectric layer of etching is with in the source/drain region of exposing described Semiconductor substrate and described grid structure;
In step 208, deposit the second metal level, and carry out the second annealing in process;
In step 209, remove described the second metal level and described the second dielectric layer, and carry out the 3rd annealing in process.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (18)
1. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, is formed with grid structure in described Semiconductor substrate;
Form the first dielectric layer in described Semiconductor substrate, to cover at least described grid structure;
Grind described the first dielectric layer, to expose the top of described grid structure;
The deposition the first metal layer covering at least the top of described grid structure, and is carried out the first annealing in process;
Remove described the first metal layer and described the first dielectric layer;
Form one second dielectric layer in described Semiconductor substrate, to cover at least described grid structure;
Described the second dielectric layer of etching is with source/drain region and the described grid structure that exposes described Semiconductor substrate;
Deposit the second metal level, and carry out the second annealing in process;
Remove described the second metal level and the second dielectric layer, and carry out the 3rd annealing in process.
2. method according to claim 1 is characterized in that, the material of described the first and second metal levels is the nickel platinum alloy.
3. method according to claim 2 is characterized in that, the ratio of described platinum is 0-15%.
4. method according to claim 1 is characterized in that, the thickness of described the first and second metal levels is the 50-300 dust.
5. method according to claim 2 is characterized in that, the ratio of platiniferous is different from the ratio of platiniferous in the described the first metal layer in described the second metal level.
6. method according to claim 1 is characterized in that, the thickness of described the second metal level is different from the thickness of described the first metal layer.
7. method according to claim 1 is characterized in that, adopts the low temperature rapid thermal anneal process to carry out described the first and second annealing in process.
8. according to claim 1 or 7 described methods, it is characterized in that, the temperature of described the first and second annealing in process is 200-350 ℃.
9. method according to claim 1 is characterized in that, adopts high-temperature quick thermal annealing technique to carry out described the 3rd annealing in process.
10. according to claim 1 or 9 described methods, it is characterized in that, the temperature of described the 3rd annealing in process is 300-600 ℃.
11. method according to claim 1 is characterized in that, after the described the first metal layer of deposition or described the second metal level, forms a protective layer.
12. method according to claim 11 is characterized in that, the material of described protective layer is titanium nitride.
13. method according to claim 12 is characterized in that, the thickness of described protective layer is the 50-200 dust.
14. method according to claim 1 is characterized in that, described the first dielectric layer is silicon nitride layer and the oxide skin(coating) that stacks gradually.
15. method according to claim 1 is characterized in that, described the second dielectric layer is silicon nitride layer.
16. method according to claim 1 is characterized in that, adopts wet clean process to remove described the first metal layer and described the first dielectric layer, described the second metal level and described the second dielectric layer.
17. method according to claim 1 is characterized in that, the described dry etching that is etched to.
18. method according to claim 1 is characterized in that, described grid structure comprises gate dielectric and the gate material layers that stacks gradually.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037051A (en) * | 2018-07-24 | 2018-12-18 | 武汉新芯集成电路制造有限公司 | The preparation method and semiconductor structure of semiconductor structure |
| CN111128873A (en) * | 2019-12-30 | 2020-05-08 | 广州粤芯半导体技术有限公司 | Wafer surface metal alloying treatment method |
| CN115132604A (en) * | 2022-08-30 | 2022-09-30 | 广州粤芯半导体技术有限公司 | Silicide process monitoring method |
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| US20070166975A1 (en) * | 2006-01-17 | 2007-07-19 | Fujitsu Limited | Fabrication process of a semiconductor device |
| US20070249149A1 (en) * | 2006-04-21 | 2007-10-25 | International Business Machines Corporation | Improved thermal budget using nickel based silicides for enhanced semiconductor device performance |
| CN101123271A (en) * | 2006-08-11 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
| CN101496172A (en) * | 2005-05-24 | 2009-07-29 | 德克萨斯仪器股份有限公司 | Nickel silicide method and structure |
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2011
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101496172A (en) * | 2005-05-24 | 2009-07-29 | 德克萨斯仪器股份有限公司 | Nickel silicide method and structure |
| US20070166975A1 (en) * | 2006-01-17 | 2007-07-19 | Fujitsu Limited | Fabrication process of a semiconductor device |
| US20070249149A1 (en) * | 2006-04-21 | 2007-10-25 | International Business Machines Corporation | Improved thermal budget using nickel based silicides for enhanced semiconductor device performance |
| CN101123271A (en) * | 2006-08-11 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037051A (en) * | 2018-07-24 | 2018-12-18 | 武汉新芯集成电路制造有限公司 | The preparation method and semiconductor structure of semiconductor structure |
| CN111128873A (en) * | 2019-12-30 | 2020-05-08 | 广州粤芯半导体技术有限公司 | Wafer surface metal alloying treatment method |
| CN115132604A (en) * | 2022-08-30 | 2022-09-30 | 广州粤芯半导体技术有限公司 | Silicide process monitoring method |
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