CN104576337A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN104576337A CN104576337A CN201310473656.0A CN201310473656A CN104576337A CN 104576337 A CN104576337 A CN 104576337A CN 201310473656 A CN201310473656 A CN 201310473656A CN 104576337 A CN104576337 A CN 104576337A
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- Prior art keywords
- layer
- dielectric layer
- interlayer dielectric
- contact hole
- metal gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 199
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims abstract description 69
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000011229 interlayer Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 34
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 21
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 21
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims description 58
- 239000006117 anti-reflective coating Substances 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 21
- 239000000470 constituent Substances 0.000 claims description 20
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 238000010276 construction Methods 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000005137 deposition process Methods 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 7
- 239000000428 dust Substances 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000004904 shortening Methods 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 206010057855 Hypotelorism of orbit Diseases 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a manufacturing method for a semiconductor device. The manufacturing method comprises the following steps of providing a semiconductor substrate, wherein a first interlayer dielectric layer, a high-k-metal gate structure positioned in the first interlayer dielectric layer and sidewall structures positioned on the two sides of the high-k-metal gate structure are formed on the semiconductor substrate, and embedded germanium-silicon layers are formed in the semiconductor substrate on the two sides of the sidewall structures; forming contact holes communicated with the embedded germanium-silicon layers in the first interlayer dielectric layer; forming sidewalls on the sidewalls of the contact holes; forming self-aligned silicide on the embedded germanium-silicon layers exposed between the sidewalls; forming contact plugs with which the contact holes are completely filled. According to the manufacturing method, after the contact holes are formed, the sidewalls are formed on the sidewalls of the contact holes by implementing a conventional sidewall forming process, and then a conventional self-aligned silicide forming process is implemented, so that the problem of shortening of the distances between the sidewalls of the contact holes and the high-k-metal gate structure caused by a Siconi etching process can be solved, and the contact holes of the high-k-metal gate structure can be effectively isolated.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of implement high k-metal gate process after on the source/drain region of metal gates both sides, form the method for self-aligned silicide.
Background technology
In the manufacturing process of integrated circuit of future generation, for the making of the grid of complementary metal oxide semiconductors (CMOS) (CMOS), the high k-metal gate process of usual employing, its typical implementation process comprises: first, form dummy gate structure on a semiconductor substrate, described dummy gate structure is by sacrificial gate dielectric layer stacked from bottom to top and sacrificial gate material layer; Then, gate pitch wall construction is formed in the both sides of dummy gate structure, remove dummy gate structure afterwards, deposited interfacial layer, high k dielectric layer, cover layer (capping layer), workfunction layers (workfunction metal layer) and barrier layer (barrier layer) successively in the groove stayed between gate pitch wall construction; Finally carry out the filling of metal gate material.
After the high k dielectric layer of deposition, need to perform annealing, to improve the configuration of surface of the micro-structural of high k dielectric layer, improve the contact berrier between itself and the metal gates of substrate and follow-up formation, effectively stop the Schottky of the electronics (or hole) in channel region to pass.Also need to implement annealing to reduce the contact resistance between self-aligned silicide and substrate owing to forming self-aligned silicide on the source/drain region of dummy gate structure both sides, for reducing considering of heat budget, usually after stating high k-metal gate process on the implementation, form the interlayer dielectric layer of covering metal grid, the contact hole being communicated with source/drain region is formed in interlayer dielectric layer, on the source/drain region of being exposed by contact hole, form self-aligned silicide afterwards, above-mentioned twice annealing can be merged into thus and once implement.
Because described contact hole has the depth-to-width ratio of bigger numerical, therefore, after the described contact hole of formation, need to implement conventional Siconi etching, to make described contact hole, there is good sidewall form and fully expose described source/drain region.But, described Siconi etching will cause the further loss of described interlayer dielectric layer, thus cause the further shortening of spacing between high k-metal gate structure and described contact hole, when device feature size reduces day by day, described interlayer dielectric layer will be had a strong impact on to the effective isolation between high k-metal gate structure and described contact hole.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprise: Semiconductor substrate is provided, be formed with the first interlayer dielectric layer on the semiconductor substrate and be arranged in the high k-metal gate structure of described first interlayer dielectric layer and be positioned at the side wall construction of described high k-metal gate structure both sides, in the Semiconductor substrate of described side wall construction both sides, being formed with embedded germanium silicon layer; The contact hole being communicated with described embedded germanium silicon layer is formed in described first interlayer dielectric layer; The sidewall of described contact hole forms side wall; The embedded germanium silicon layer exposed between by described side wall forms self-aligned silicide; Form the contact plug of filling described contact hole completely.
Further, described high k-metal gate structure comprise stack gradually from bottom to top high k dielectric layer, workfunction setting metal layer, barrier layer and metal gate material layer.
Further, be formed with boundary layer in the below of described high k dielectric layer, between described high k dielectric layer and described workfunction setting metal layer, be formed with cover layer, between described barrier layer and described metal gate material layer, be formed with soakage layer.
Further, the step forming described embedded germanium silicon layer comprises: adopt the technique of first dry etching wet etching again in the Semiconductor substrate of described side wall construction both sides, form ∑ shape groove; Selective epitaxial growth process is adopted to form described embedded germanium silicon layer, to fill described ∑ shape groove completely.
Further, described embedded germanium silicon layer is doped with boron.
Further, after the embedded germanium silicon layer of described epitaxial growth, also comprise the step adopting original position epitaxial growth technology to form cap layers at the top of described embedded germanium silicon layer, the constituent material of described cap layers is silicon.
Further, the step forming described contact hole comprises: form the second interlayer dielectric layer, advanced patterned layer, dielectric antireflective coatings, oxide skin(coating), bottom antireflective coating on the semiconductor substrate successively and have the photoresist layer of described contact hole pattern, cover described first interlayer dielectric layer and described high k-metal gate structure; Dry method etch technology is adopted to etch described bottom antireflective coating, described oxide skin(coating), described dielectric antireflective coatings, described advanced patterned layer, described second interlayer dielectric layer and described first interlayer dielectric layer successively, until expose described embedded germanium silicon layer to stop described etching; Adopt cineration technics to remove described photoresist layer, described bottom antireflective coating, described oxide skin(coating), described dielectric antireflective coatings and described advanced patterned layer, expose described second interlayer dielectric layer.
Further, the constituent material of described second interlayer dielectric layer is identical with the constituent material of described first interlayer dielectric layer.
Further, the step forming described side wall comprises: at sidewall and the bottom formation spacer material layer of described contact hole; Etch described spacer material layer, expose the bottom of described contact hole.
Further, adopt conformal deposition process to form described spacer material layer, the material of described spacer material layer is silicon nitride, and the thickness of described spacer material layer is 150-200 dust.
Further, described conformal deposition process is atom layer deposition process.
Further, adopt side wall etching technics to implement described etching, the thickness of the described side wall of formation is 80-130 dust.
Further, described self-aligned silicide is NiPtSi.
According to the present invention, after the described contact hole of formation, first implement the technique of conventional formation side wall to form described side wall at the sidewall of described contact hole, implement the technique of the conventional described self-aligned silicide of formation again, the problem of the hypotelorism between the sidewall of the described contact hole that Siconi etch process wherein can be avoided to cause and described high k-metal gate structure, guarantees effective isolation therebetween.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The schematic cross sectional view of the device that Figure 1A-Fig. 1 F obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 2 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to form the method for self-aligned silicide after explaining the high k-metal gate process of enforcement of the present invention's proposition on the source/drain region of metal gates both sides.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below, with reference to Figure 1A-Fig. 1 F and Fig. 2, the detailed step forming self-aligned silicide after method according to an exemplary embodiment of the present invention implements high k-metal gate process on the source/drain region of metal gates both sides is described.
With reference to Figure 1A-Fig. 1 F, the schematic cross sectional view of the device that the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively obtains respectively.
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, the constituent material of Semiconductor substrate 100 can to adopt on unadulterated monocrystalline silicon, monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), insulator stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate 100 selects monocrystalline silicon.Isolation structure 101 is formed in Semiconductor substrate 100, exemplarily, isolation structure 101 be shallow trench isolation from (STI) structure or selective oxidation silicon (LOCOS) isolation structure, in the present embodiment, isolation structure 101 is fleet plough groove isolation structure.Semiconductor substrate 100 is divided into nmos area and PMOS district by isolation structure 101, in order to simplify, in diagram, PMOS district is only shown.Also be formed with various trap (well) structure in Semiconductor substrate 100, in order to simplify, be omitted in diagram; For PMOS district, described well structure is N trap and before formation dummy gate structure, can carries out once low dose of boron inject, for adjusting the threshold voltage V in PMOS district whole N trap
th.
Be formed with high k-metal gate structure on a semiconductor substrate 100, exemplarily, high k-metal gate structure comprise stack gradually from bottom to top high k dielectric layer 110d, workfunction setting metal layer 110a, barrier layer 110b and metal gate material layer 110c.The k value (dielectric constant) of high k dielectric layer 110d is generally more than 3.9, its constituent material comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide, zirconia or aluminium oxide.Workfunction setting metal layer 110a comprises one or more layers metal or metallic compound, for N-type metal gate structure, the constituent material of its workfunction setting metal layer 110a is the metal material being applicable to NMOS, comprise titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, also comprise the carbide of above-mentioned metallic element, nitride etc.; For P type metal gate structure, the constituent material of its workfunction setting metal layer 110a is the metal material being applicable to PMOS device, comprises ruthenium, palladium, platinum, tungsten and alloy thereof, also comprises the carbide of above-mentioned metallic element, nitride etc.The material of barrier layer 110b comprises tantalum nitride or titanium nitride, and the material of metal gate material layer 110c comprises tungsten or aluminium.It should be noted that, can also form boundary layer in the below of high k dielectric layer 110d, its constituent material comprises Si oxide (SiO
x), the effect forming boundary layer improves the interfacial characteristics between high k dielectric layer and Semiconductor substrate 100; Cover layer can also be formed between high k dielectric layer 110d and workfunction setting metal layer 110a, its constituent material comprises titanium nitride or tantalum nitride, and forming tectal effect is stop the metal material in the workfunction setting metal layer 110a of follow-up formation to the diffusion of high k dielectric layer 110d; Soakage layer can also be formed between barrier layer 110b and metal gate material layer 110c, its constituent material comprises titanium or titanium-aluminium alloy, the effect forming soakage layer improves the interfacial characteristics between barrier layer 110b and metal gate material layer 110c, in order to simplify, omitted in diagram.
In addition, exemplarily, be also formed on a semiconductor substrate 100 and be positioned at high k-metal gate structure both sides and near the side wall construction 102 of high k-metal gate structure.Wherein, side wall construction 102 can comprise at least oxide skin(coating) and/or nitride layer.In the present embodiment, the constituent material of side wall construction 102 is silicon nitride.
In the Semiconductor substrate 100 of side wall construction 102 both sides, be formed with embedded germanium silicon layer 103, its forming process generally includes following steps: adopt the technique of first dry etching wet etching again in the Semiconductor substrate 100 of side wall construction 102 both sides, form ∑ shape groove; Selective epitaxial growth process is adopted to form embedded germanium silicon layer 103, to fill described ∑ shape groove completely, the embedded germanium silicon layer 103 formed can doped with boron, and described selective epitaxial growth process can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).The concrete steps of the described first dry etching technique of wet etching are again as follows: first adopt the Semiconductor substrate 100 of longitudinal etching side wall structure 102 both sides of dry method etch technology to form groove, in the present embodiment, and employing CF
4with HBr as main etching gas, temperature 40-60 DEG C, power 200-400W, bias voltage 50-200V, etching period is determined according to etch depth; Adopt isotropic dry method etch technology to continue the described groove of etching again, form oval-shaped groove in the below of described groove, namely form bowl-shape groove, in the present embodiment, adopt Cl
2and NF
3as main etching gas, temperature 40-60 DEG C, power 100-500W, bias voltage 0-10V, etching period is determined according to the sidewall of the described bowl-shape groove degree of depth recessed to the channel region of Semiconductor substrate 100; Finally adopt the described bowl-shape groove of wet etching process expansion etching, to form described ∑ shape groove, the temperature of described wet etching is 30-60 DEG C, the desired size of basis of time ∑ shape groove 103 and determining, be generally 100-300s, in the present embodiment, adopt Tetramethylammonium hydroxide (TMAH) solution as the corrosive liquid of described wet etching.
Cap layers 104 can be formed, to be conducive to the follow-up enforcement forming self-aligned silicide on embedded germanium silicon layer 103 at the top of embedded germanium silicon layer 103.In the present embodiment, original position epitaxial growth technology is adopted to form cap layers 104, namely the epitaxial growth technology that formation cap layers 104 adopts is carried out in same reaction chamber with the epitaxial growth technology that the embedded germanium silicon layer 103 of formation adopts, and exemplarily, the constituent material of cap layers 104 is silicon.
After forming embedded germanium silicon layer 103 or cap layers 104, form the contact etch stop layer 105 and the first interlayer dielectric layer 106 that cover the dummy gate structure be made up of stacked sacrificial gate dielectric layer and sacrificial gate material layer completely from bottom to top on a semiconductor substrate 100.The material preferred nitrogen SiClx of contact etch stop layer 105, the preferred using plasma of material of the first interlayer dielectric layer 106 strengthens the oxide of chemical vapor deposition method formation.Then, perform cmp to expose the top of described dummy gate structure, then, remove described dummy gate structure, and in the groove stayed, form aforementioned high k-metal gate structure.
Then, as shown in Figure 1B, form the second interlayer dielectric layer 106a, advanced patterned layer (APF) 108, dielectric antireflective coatings (DARC) 109, oxide skin(coating) 111, bottom antireflective coating (BARC) 112 and the photoresist layer 113 with contact hole pattern 114a on a semiconductor substrate 100 successively, cover the first interlayer dielectric layer 106 and described high k-metal gate structure.Form the various suitable technique that above-mentioned each layer can adopt those skilled in the art to have the knack of, such as, chemical vapor deposition method is adopted to form the second interlayer dielectric layer 106a, advanced patterned layer 108, dielectric antireflective coatings 109 and oxide skin(coating) 111, adopt spin coating proceeding to form bottom antireflective coating 112, adopt the techniques such as spin coating, exposure, development to form the photoresist layer 113 with contact hole pattern 114a.The constituent material of the second interlayer dielectric layer 106a is identical with the constituent material of the first interlayer dielectric layer 106, and preferred using plasma strengthens the oxide that chemical vapor deposition method is formed.The preferred amorphous carbon of constituent material of advanced patterned layer 108.The effect of oxide skin(coating) 111 is the decline of the exposure performance of the photoresist layer 113 preventing the dielectric antireflective coatings 109 of alkalescence from causing to the diffusion of photoresist layer 113, guarantees the contact hole graph in mask plate to be intactly transferred to photoresist layer 113.
Then, as shown in Figure 1 C, in the second interlayer dielectric layer 106a with the first interlayer dielectric layer 106, form the contact hole 114 being communicated with cap layers 104.The processing step forming contact hole 114 comprises: to have the photoresist layer 113 of contact hole pattern 114a for mask, dry method etch technology is adopted to etch bottom antireflective coating 112, oxide skin(coating) 111, dielectric antireflective coatings 109, advanced patterned layer 108, second interlayer dielectric layer 106a, the first interlayer dielectric layer 106 and contact etch stop layer 105 successively, until expose cap layers 104 to stop described etching; Adopt cineration technics to remove photoresist layer 113, bottom antireflective coating 112, oxide skin(coating) 111, dielectric antireflective coatings 109 and advanced patterned layer 108, expose the second interlayer dielectric layer 106a.
Then, as shown in figure ip, at sidewall and the bottom formation spacer material layer 115 of contact hole 114.In the present embodiment, adopt conformal deposition process to form spacer material layer 115, to make the spacer material layer 115 of formation, there is in contact hole 114 good Step Coverage shape.Because the depth-to-width ratio of contact hole 114 is less than 2:1, therefore, the conformal deposition process of the routine that those skilled in the art have the knack of all may be used for forming spacer material layer 115, the preferred atom layer deposition process of described conformal deposition process, the material preferred nitrogen SiClx of spacer material layer 115.In the present embodiment, the thickness of spacer material layer 115 is 150-200 dust.
Then, as referring to figure 1e, the etched side walling bed of material 115, exposes the bottom of the second interlayer dielectric layer 106a and contact hole 114, and the sidewall of contact hole 114 is formed side wall 115a.In the present embodiment, etch described in side wall etching (blanket etch) process implementing of the routine adopting those skilled in the art to have the knack of, its etching gas mainly contains C
xh
yf
z, Ar, O
2deng, the thickness of the side wall 115a of formation is 80-130 dust.
Then, as shown in fig. 1f, the cap layers 104 exposed between by side wall 115a forms self-aligned silicide 107, its forming process generally includes following steps: first implement conventional Siconi etching, have good sidewall form to make contact hole 114 and fully expose cap layers 104, its etching gas mainly contains NH
3and NF
3; Formed again and cover the sidewall of contact hole 114 and the metal level of bottom, the technique forming described metal level can adopt method conventional in this area, such as, physical vaporous deposition or vapour deposition method etc., the material of described metal level is the nickel (Ni) containing certain proportion platinum (Pt), in the present embodiment, described ratio is 0-15%, simultaneously, protective layer can be formed on described metal level, the material of described protective layer is the nitride of refractory metal, such as TiN, and the effect of described protective layer avoids described metal level be exposed to the environment of non-inert and be oxidized; Then, adopt low-temperature rapid thermal annealing (RTA) technique to anneal to described metal level, the material in described metal level is spread in the silicon materials forming cap layers 104, and reacts with described silicon materials and form self-aligned silicide 107, in the present embodiment,
The temperature of described low-temperature rapid thermal annealing is 200-350 DEG C; Next, adopt wet clean process to remove the metal level not being converted into self-aligned silicide 107 by above-mentioned reaction, the protective layer be formed on described metal level is also removed in the lump; Finally, adopt high-temperature quick thermal annealing technique to anneal to the self-aligned silicide 107 formed, complete the making of self-aligned silicide 107, in the present embodiment, the temperature of described high-temperature quick thermal annealing is 300-600 DEG C.
Next, form the contact plug 116 of complete filling contact hole 114, the preferred tungsten of its constituent material.The various suitable technology adopting those skilled in the art to have the knack of forms contact plug 116, such as physical gas-phase deposition.Then, cmp is performed to expose the second interlayer dielectric layer 106a.
So far, complete the processing step that method is according to an exemplary embodiment of the present invention implemented, next, the making of whole semiconductor device can be completed by subsequent technique, comprise the metal interconnecting wires that formation is communicated with contact plug 116 and aforementioned high k-metal gate structure respectively.According to the present invention, after formation contact hole 114, the technique first implementing conventional formation side wall forms side wall 115a with the sidewall at contact hole 114, implement the technique of conventional formation self-aligned silicide 107 again, the problem of the hypotelorism between the sidewall of the contact hole 114 that Siconi etch process wherein can be avoided to cause and aforementioned high k-metal gate structure, guarantees effective isolation therebetween.
With reference to Fig. 2, the flow chart of the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively, for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, be formed with the first interlayer dielectric layer on a semiconductor substrate and be arranged in the high k-metal gate structure of the first interlayer dielectric layer and be positioned at the side wall construction of high k-metal gate structure both sides, in the Semiconductor substrate of side wall construction both sides, being formed with embedded germanium silicon layer;
In step 202., in the first interlayer dielectric layer, form the contact hole being communicated with embedded germanium silicon layer;
In step 203, the sidewall of contact hole forms side wall;
In step 204, the embedded germanium silicon layer exposed between by side wall forms self-aligned silicide;
In step 205, the contact plug of complete filling contact hole is formed.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, be formed with the first interlayer dielectric layer on the semiconductor substrate and be arranged in the high k-metal gate structure of described first interlayer dielectric layer and be positioned at the side wall construction of described high k-metal gate structure both sides, in the Semiconductor substrate of described side wall construction both sides, being formed with embedded germanium silicon layer;
The contact hole being communicated with described embedded germanium silicon layer is formed in described first interlayer dielectric layer;
The sidewall of described contact hole forms side wall;
The embedded germanium silicon layer exposed between by described side wall forms self-aligned silicide;
Form the contact plug of filling described contact hole completely.
2. method according to claim 1, is characterized in that, described high k-metal gate structure comprise stack gradually from bottom to top high k dielectric layer, workfunction setting metal layer, barrier layer and metal gate material layer.
3. method according to claim 2, it is characterized in that, be formed with boundary layer in the below of described high k dielectric layer, between described high k dielectric layer and described workfunction setting metal layer, be formed with cover layer, between described barrier layer and described metal gate material layer, be formed with soakage layer.
4. method according to claim 1, is characterized in that, the step forming described embedded germanium silicon layer comprises: adopt the technique of first dry etching wet etching again in the Semiconductor substrate of described side wall construction both sides, form ∑ shape groove; Selective epitaxial growth process is adopted to form described embedded germanium silicon layer, to fill described ∑ shape groove completely.
5. method according to claim 4, is characterized in that, described embedded germanium silicon layer is doped with boron.
6. method according to claim 4, is characterized in that, after the embedded germanium silicon layer of described epitaxial growth, also comprise the step adopting original position epitaxial growth technology to form cap layers at the top of described embedded germanium silicon layer, the constituent material of described cap layers is silicon.
7. method according to claim 1, it is characterized in that, the step forming described contact hole comprises: form the second interlayer dielectric layer, advanced patterned layer, dielectric antireflective coatings, oxide skin(coating), bottom antireflective coating on the semiconductor substrate successively and have the photoresist layer of described contact hole pattern, cover described first interlayer dielectric layer and described high k-metal gate structure; Dry method etch technology is adopted to etch described bottom antireflective coating, described oxide skin(coating), described dielectric antireflective coatings, described advanced patterned layer, described second interlayer dielectric layer and described first interlayer dielectric layer successively, until expose described embedded germanium silicon layer to stop described etching; Adopt cineration technics to remove described photoresist layer, described bottom antireflective coating, described oxide skin(coating), described dielectric antireflective coatings and described advanced patterned layer, expose described second interlayer dielectric layer.
8. method according to claim 7, is characterized in that, the constituent material of described second interlayer dielectric layer is identical with the constituent material of described first interlayer dielectric layer.
9. method according to claim 1, is characterized in that, the step forming described side wall comprises: at sidewall and the bottom formation spacer material layer of described contact hole; Etch described spacer material layer, expose the bottom of described contact hole.
10. method according to claim 9, is characterized in that, adopt conformal deposition process to form described spacer material layer, the material of described spacer material layer is silicon nitride, and the thickness of described spacer material layer is 150-200 dust.
11. methods according to claim 10, is characterized in that, described conformal deposition process is atom layer deposition process.
12. methods according to claim 9, is characterized in that, adopt side wall etching technics to implement described etching, the thickness of the described side wall of formation is 80-130 dust.
13. methods according to claim 1, is characterized in that, described self-aligned silicide is NiPtSi.
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