CN106158643A - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN106158643A CN106158643A CN201510163918.2A CN201510163918A CN106158643A CN 106158643 A CN106158643 A CN 106158643A CN 201510163918 A CN201510163918 A CN 201510163918A CN 106158643 A CN106158643 A CN 106158643A
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- forming method
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- 238000000034 method Methods 0.000 title claims abstract description 138
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- 150000002500 ions Chemical class 0.000 claims abstract description 62
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 29
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- 238000005516 engineering process Methods 0.000 claims description 17
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 15
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- 238000011065 in-situ storage Methods 0.000 claims description 8
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- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 3
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- 239000010410 layer Substances 0.000 description 347
- 239000010408 film Substances 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
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- 239000010703 silicon Substances 0.000 description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 12
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- 239000004065 semiconductor Substances 0.000 description 12
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 10
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- 239000013078 crystal Substances 0.000 description 4
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 4
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 4
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- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
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- 238000001465 metallisation Methods 0.000 description 1
- VMWYVTOHEQQZHQ-UHFFFAOYSA-N methylidynenickel Chemical compound [Ni]#[C] VMWYVTOHEQQZHQ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
A kind of forming method of transistor, including: substrate is provided；Grid structure is formed at described substrate surface；Opening is formed in the substrate of described grid structure both sides；Stressor layers is formed in described opening；Form cover layer on described stressor layers surface, described cover layer is interior doped with oxygen group elements ion；Using silication technique for metal to make described cover layer be converted into electric contacting layer, the material of described electric contacting layer is the metal silicide doped with oxygen group elements ion.In the transistor formed, the resistance on stressor layers surface reduces, and makes the operating current of described transistor improve, stable performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of a kind of transistor.
Background technology
Along with developing rapidly of semiconductor fabrication, semiconductor device just towards higher component density with
And the direction of higher integrated level develops.Transistor as most basic semiconductor device currently by extensively
Application, therefore along with component density and the raising of integrated level of semiconductor device, the grid size of transistor
Become the most shorter.But, the grid size of transistor shortens and transistor can be made to produce short-channel effect,
And then generation leakage current, finally affect the electric property of semiconductor device.At present, prior art is mainly led to
Cross raising carrier mobility to improve performance of semiconductor device.When the mobility of carrier improves, crystal
The driving electric current of pipe improves, then the leakage current in transistor reduces, and improves one of carrier mobility
Key element is to improve the stress in transistor channel region, and the stress therefore improving transistor channel region is permissible
It is greatly enhanced the performance of transistor.
Prior art improves a kind of method of transistor channel region stress: in source region and the drain region of transistor
Form stressor layers.Wherein, the stressor layers material of PMOS transistor is SiGe (SiGe), due to SiGe and
Silicon has identical lattice structure, i.e. " diamond " structure, and at room temperature, the lattice paprmeter of SiGe is big
In the lattice paprmeter of silicon, therefore there is lattice mismatch between silicon and SiGe, enable stressor layers to channel region
Compressive stress is provided, thus improves the carrier mobility performance of PMOS transistor channel region.Correspondingly,
The stressor layers material of nmos pass transistor is carborundum (SiC), due at room temperature, the lattice of carborundum
Less than the lattice paprmeter of silicon, therefore there is lattice mismatch between silicon and carborundum, it is possible to channel region in constant
Tension is provided, thus improves the performance of nmos pass transistor.
But, the electrical connection properties between stressor layers and conductive structure that prior art is formed is the best, fall
The low Performance And Reliability of semiconductor device.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of transistor, in the transistor formed,
The resistance on stressor layers surface reduces, and makes the operating current of described transistor improve, stable performance.
For solving the problems referred to above, the present invention provides the forming method of a kind of transistor, including: substrate is provided；
Grid structure is formed at described substrate surface；Opening is formed in the substrate of described grid structure both sides；?
Stressor layers is formed in described opening；Doping in cover layer, described cover layer is formed on described stressor layers surface
There is chalcogen element ion；Silication technique for metal is used to make described cover layer be converted into electric contacting layer, described electricity
The material of contact layer is the metal silicide doped with oxygen group elements ion.
Optionally, the material of described stressor layers is carborundum；Doped with N-shaped ion in described stressor layers.
Optionally, the forming step of described stressor layers includes: in sidewall and the lower surface shape of described opening
Become Seed Layer；The stress material layer filling full described opening is formed on described Seed Layer surface.
Optionally, the formation process of described Seed Layer is chemical vapor deposition method, physical vapour deposition (PVD) work
Skill or atom layer deposition process；The formation process of described stress material layer is epitaxial deposition process.
Optionally, the material of described cover layer is the carborundum of doping chalcogen element ion.
Optionally, the formation process of described cover layer is epitaxial deposition process.
Optionally, in described cover layer the oxygen group elements ion of doping be sulphion, plasma selenium or tellurium from
Son.
Optionally, in cover layer, the technique of doping chalcogen element ion is that doping process or ion are noted in situ
Enter technique.
Optionally, in situ doping process is used adulterate in cover layer chalcogen element ion, and the oxygen adulterated
When race's element ion is sulphion, process gas includes the one in hydrogen sulfide, sulfur dioxide, sulfur fluoride
Or it is multiple.
Optionally, when in described cover layer, the oxygen group elements ion of doping is sulphion, described sulphion
Atom percentage concentration be 0.1～5%.
Optionally, the thickness of described cover layer is 3 nanometers～50 nanometers.
Optionally, described silication technique for metal includes: on described substrate, cover layer and grid structure surface
Form metal level；Use the first annealing process to make the metallic atom in metal level to cover layer internal diffusion, make
Cover layer is converted into electric contacting layer；After described first annealing process, remove remaining metal level.
Optionally, the material of described metal level is nickel or platinum.
Optionally, also include: after removing remaining metal level, carry out the second annealing process.
Optionally, described grid structure includes: is positioned at the gate dielectric layer of substrate surface, is positioned at gate dielectric layer
The gate electrode layer on surface and be positioned at gate electrode layer and gate dielectric layer both sides sidewall and the side wall of substrate surface.
Optionally, the material of described gate dielectric layer is silicon oxide；The material of described gate electrode layer is polysilicon.
Optionally, also include: after forming described cover layer, in described substrate and cover surface shape
Becoming dielectric layer, described dielectric layer exposes the top surface of described grid structure；Remove described gate electrode layer,
Gate openings is formed in described dielectric layer；Lower surface in described gate openings forms high-k dielectric layer；
Metal gate is formed on described high-k dielectric layer surface.
Optionally, the forming step of described opening includes: is formed at described substrate and grid structure surface and covers
Film layer, described mask layer exposes the section substrate surface of described grid structure both sides；With described mask layer
For mask, etch described substrate, in described substrate, form opening.
Optionally, the etching technics forming described opening includes dry etch process.
Optionally, also include: form electric interconnection structure on described electric contacting layer surface.
Compared with prior art, technical scheme has the advantage that
In the forming method of the present invention, after stressor layers surface forms cover layer, in described cover layer
Doping chalcogen element ion；After follow-up employing silication technique for metal makes cover layer be converted into electric contacting layer,
Can make formed electric contacting layer material is the metal silicide doped with oxygen group elements ion.Due to warp
Crossing research to find, the chalcogen element ion that adulterates in metal silicide materials can reduce metal silicide material
The Schottky barrier of material, therefore, the Schottky barrier of the electric contacting layer formed reduces, and the most described electricity connects
The resistance of contact layer reduces such that it is able to reduce between described stressor layers and follow-up formed electric interconnection structure
Resistance.Owing to the resistance between stressor layers and follow-up formed electric interconnection structure reduces, it is possible to increase
Electric current between electric interconnection structure and stressor layers, thus improve the operating current of formed transistor, make
The performance of the transistor formed is more stable, and reliability improves.
Further, the material of described stressor layers is carborundum, then the covering layer material formed is doped with oxygen
The carborundum of race's element ion；Being converted, by described cover layer, the electric contacting layer material formed is that doping chalcogen is first
The metal carbon-silicon compound material of element ion, it is possible to reduce the Xiao Te of metal carbon-silicon compound material further
Base potential barrier, reduces the contact resistance between stressor layers and electric contacting layer with this, then the electrical interconnection being subsequently formed
Resistance between structure and stressor layers reduces.
Further, in described cover layer, the oxygen group elements ion of doping is sulphion, mixes in cover layer
The technique of miscellaneous oxygen group elements ion is original position doping process；Described original position doping process can cover being formed
During Ceng, by adding sulfur source gas in process gas, it is possible to make in cover layer the sulfur of doping from
Son is more evenly distributed, and doping process is the simplest；Sulphion distribution in the electric contacting layer then formed
Being more uniformly distributed, the electric contacting layer formed is more stable for the ability reducing contact resistance.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the cross-sectional view of the forming process of a kind of transistor of the embodiment of the present invention；
Fig. 4 to Figure 10 is the cross-sectional view of the forming process of the transistor of the embodiment of the present invention.
Detailed description of the invention
As stated in the Background Art, the electrical connectivity between prior art is formed stressor layers and conductive structure
Can not be good, reduce the Performance And Reliability of semiconductor device.
Finding through research, owing to the material of stressor layers is semi-conducting material, and the material of conductive structure is
Metal, there is Schottky barrier, causes carrier to exist in described stressor layers at the contact interface of conductive structure
Transition difficulty at the contact interface of described stressor layers and conductive structure is relatively big, the most described stressor layers and conduction
Contact resistance between structure is bigger.
In order to reduce the contact resistance between described stressor layers and conductive structure, a kind of method is in stressor layers
Surface forms the electric contacting layer with metal silicide as material, and described metal silicide materials can reduce to be led
Schottky barrier between electricity structure and stressor layers, thus reduces contacting between stressor layers and conductive structure
Resistance.
Fig. 1 to Fig. 3 is the cross-sectional view of the forming process of a kind of transistor of the embodiment of the present invention.
Refer to Fig. 1, it is provided that substrate 100, described substrate 100 surface has grid structure 101, described
In the substrate 100 of grid structure 101 both sides, there is opening 102.
Refer to Fig. 2, use selective epitaxial depositing operation in described opening 102 (as shown in Figure 1)
Forming stressor layers 103, the surface of described stressor layers 103 is higher than described substrate 100 surface.
Refer to Fig. 3, use silication technique for metal to make the part stressor layers 103 being positioned at surface be converted into electricity and connect
Contact layer 104, the material of described electric contacting layer 104 is metal silicide.
Wherein, when the transistor formed is PMOS transistor, the material of described stressor layers 103 is
SiGe (SiGe)；When the transistor formed is nmos pass transistor, the stressor layers 103 formed
Material be carborundum (SiC).The forming step of described electric contacting layer 104 includes: in stressor layers 103
Forming metal layer on surface；Use thermal anneal process make the metallic atom in metal level to stressor layers internal diffusion,
Make the part stressor layers 103 being positioned at surface be converted into metal silicide materials, form electric contacting layer 104；?
After described thermal anneal process, remove remaining metal level.
The material of described metal level is nickel (Ni) or cobalt (Co)；Wherein, especially material with nickel as metal level
During material, it is possible to make formed electric contacting layer 104 have lower contact resistance.For PMOS crystal
For pipe, the material of described stressor layers 103 is SiGe, and the material of the electric contacting layer 104 formed is for mixing
The nickel-silicon compound of germanium；For nmos pass transistor, the material of described stressor layers 103 is carborundum,
The nickel-silicon compound that material is carbon dope of the electric contacting layer 104 formed.
But, along with constantly reducing of semiconductor technology node, the size of the transistor of required formation also phase
Should reduce, cause the contact area between described stressor layers 103 and conductive structure less, cause stress
Contact resistance between layer 103 and conductive structure is bigger.Even if between conductive structure and stressor layers 103
Form electric contacting layer 104, owing to the characteristic of material itself limits, to reduction described stressor layers 103 and leading
Between electricity structure, contact resistance is limited in one's ability.As a example by nmos pass transistor, when the material of described metal level
When material is for nickel, electric contacting layer 104 material formed is the nickel-silicon compound of carbon dope, but, due to institute
The Schottky barrier of the nickel-silicon compound stating carbon dope remains unchanged higher, causes in formed nmos pass transistor,
Contact resistance between stressor layers and conductive structure remains unchanged bigger.Therefore, the forming process of described transistor
The demand of technology development cannot be met.
In order to solve the problems referred to above, the present invention provides the forming method of a kind of transistor.Wherein, at stress
After layer surface forms cover layer, adulterate in described cover layer chalcogen element ion；Gold is used when follow-up
Belong to after silicification technics makes cover layer be converted into electric contacting layer, it is possible to make the formed electric contacting layer material be
Metal silicide doped with oxygen group elements ion.Owing to finding through research, in metal silicide materials
Middle doping chalcogen element ion can reduce the Schottky barrier of metal silicide materials, therefore, is formed
The Schottky barrier of electric contacting layer reduce, the resistance of the most described electric contacting layer reduces such that it is able to reduce
Resistance between described stressor layers and follow-up formed electric interconnection structure.Due to stressor layers and follow-up institute shape
Resistance between the electric interconnection structure become reduces, it is possible to increase the electric current between electric interconnection structure and stressor layers,
Thus improve the operating current of formed transistor, the performance making formed transistor is more stable,
Reliability improves.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Fig. 4 to Figure 10 is the cross-sectional view of the forming process of the transistor of the embodiment of the present invention.
Refer to Fig. 4, it is provided that substrate 200；Grid structure 201 is formed on described substrate 200 surface.
Described substrate 200 is silicon substrate, germanium substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator
(SOI) substrate or germanium on insulator (GOI) substrate.In the present embodiment, described substrate 200 is silicon
Substrate, the follow-up stressor layers that formed in the substrate 200 of described grid structure 201 both sides, and described stress
The material of layer is SiGe or carborundum, it is possible to make to there is lattice mismatch between described silicon substrate and stressor layers,
Enable formed stressor layers that the substrate 200 bottom grid structure is applied stress, improve raceway groove with this
The carrier mobility in district.In the present embodiment, the transistor formed is nmos pass transistor, follow-up
The stressor layers material formed is carborundum.
Described grid structure 201 is used for forming transistor.Described grid structure 201 includes: be positioned at substrate
Grid layer on 200 and be positioned at the side wall of described grid layer sidewall surfaces.In the present embodiment, described
Grid structure 201 also includes: the gate dielectric layer between described grid layer and substrate 200.Wherein,
The material of described grid layer is polysilicon or amorphous silicon, and the thickness of grid layer is 500 angstroms～1500 angstroms；Institute
The material stating gate dielectric layer is silicon oxide.
In one embodiment, described grid structure 201 can be directly used for forming transistor, the most described grid
The material of dielectric layer 210 can also be silicon nitride or silicon oxynitride.
In another embodiment, described grid structure 201 can be used as dummy gate structure, follow-up with high K
Gate dielectric layer and metal gate substitute described grid layer and gate dielectric layer, then can form high-K metal gate structure
The transistor of (High K Metal Gate is called for short HKMG), the most described grid layer and gate dielectric layer are
The high-K gate dielectric layer being subsequently formed and metal gate take up space position.
In this embodiment, described gate dielectric layer can protect substrate when the described grid layer of follow-up removal
200 surfaces are from damage, and the material of described gate dielectric layer is silicon oxide, described gate dielectric layer and substrate
Etching selection between 200 surfaces is bigger, when removing described gate dielectric layer, to substrate 200 surface
Damage less.
The formation process of described gate dielectric layer and grid layer includes: form gate dielectric film on substrate 200 surface；
Gate electrode film is formed on described gate dielectric film surface；Patterned first mask is formed on described gate electrode film surface
Layer (not shown), described patterned first mask layer exposes part of grid pole film surface and covers needs
Form corresponding region and the position of grid layer；With described patterned first mask layer as mask, etch institute
State gate electrode film and gate dielectric film, till exposing described substrate 200 surface, form grid layer and grid
Dielectric layer.Wherein, the formation process thermal oxidation technology of described gate dielectric film, chemical oxidation process, chemistry
Gas-phase deposition, physical gas-phase deposition or atom layer deposition process；The formation work of described gate electrode film
Skill is chemical vapor deposition method or physical gas-phase deposition.
In the present embodiment, after forming described grid layer and gate dielectric layer, retain described patterned
First mask layer, described patterned first mask layer can be subsequently formed stressor layers and electric contacting layer mistake
Cheng Zhong, protects the top of described grid layer.
The technique etching described gate electrode film is anisotropic dry etch process, etching gas Cl2、HBr、
SF6In one or more；The technique etching described gate dielectric film is dry etch process, wet etching work
One or both combinations in skill, wherein, the etching liquid of described wet-etching technology includes hydrofluoric acid solution,
The gas of dry etching includes hydrofluoric acid gas.
Described patterned first mask material is SiN, SiON, SiOCN, SiOBN, SiO2In
One or more combination, thickness is 50 angstroms～500 angstroms.The formation work of described patterned first mask layer
Skill includes: form mask material film on described gate electrode film surface；Figure is formed on described mask material film surface
Shape layer, described patterned layer covers the corresponding region needing to form grid layer；With described patterned layer it is
Mask, etches described mask material film, till exposing gate electrode film surface, forms patterned
One mask layer.
Wherein, the formation process of described mask material film is atom layer deposition process or chemical gaseous phase deposition work
Skill.Described patterned layer can be patterned photoresist layer, it is also possible to for using multiple graphics mask work
(Self-Aligned Double Patterning is called for short for the mask that skill is formed, such as self-alignment duplex pattern
SADP) mask.
In other embodiments, described grid structure 201 is as dummy gate structure, and described grid structure
201 can include the gate dielectric layer between described grid layer and substrate without silicon oxide, described grid layer
Material is polysilicon, after the described grid layer of follow-up removal, forms high K grid in the position of described grid layer
Dielectric layer and be positioned at the metal gate on high-K gate dielectric layer surface.
Described side wall is for the distance of the stressor layers that is subsequently formed of definition to grid layer.The material of described side wall
Including silicon oxide, silicon nitride, silicon oxynitride, the silicon oxynitride of carbon dope, boron-doping silicon oxynitride in one
Plant or multiple combination；The thickness of described side wall is 20 angstroms～200 angstroms；The formation process of described side wall includes:
At substrate, the sidewall surfaces of grid layer and patterned first mask layer surface deposition side wall film；Return and carve
Lose described side wall film until exposing described patterned first mask layer lower surface and substrate 200
Till surface, form described side wall.
In the present embodiment, owing to remaining patterned first mask layer at the top surface of grid layer,
Described patterned first mask layer can protect described grid in the described technique being etched back to side wall film
The top surface of layer.
Refer to Fig. 5, in the substrate 200 of described grid structure 201 both sides, form opening 202.
In the present embodiment, described opening 202 is used for forming stressor layers, and adulterate in described stressor layers P
Type ion or N-type ion, it is possible in the substrate 200 of grid structure 201 both sides, form source region and drain region.
The degree of depth of described opening 202 is 50 nanometers～200 nanometers.
The forming step of described opening 202 includes: in described substrate 200 and grid structure 201 surface shape
The second mask layer (not shown), described second mask layer is become to expose the portion of described grid structure 201 both sides
Divide substrate 200 surface；With described second mask layer as mask, etch described substrate 200, at described substrate
Opening 202 is formed in 200.
Along with the size of transistor constantly reduces, in order to the structure and size making described second mask layer is more smart
Really, described second mask layer exposes described grid structure 201 and is positioned at described grid structure 201 liang
Section substrate 200 surface of side, the area size that the most described second mask layer exposes is relatively big, described in cover
Film layer by technique limited less, simplify the formation process of described second mask layer.Due to described grid
The top surface of layer has the first mask layer and covers, therefore during being subsequently formed opening 202, and institute
The top surface stating grid layer is not damaged.
In the present embodiment, the transistor owing to being formed is nmos pass transistor, and nmos pass transistor
Carrier be electronics, the transfer ability of electronics is higher, and therefore, the sidewall of described opening 202 is perpendicular to
Substrate 200 surface i.e. can provide sufficiently large stress to channel region.
In the present embodiment, the etching technics forming described opening 202 is anisotropic dry etching work
Skill.Described substrate 200 is silicon substrate, and the parameter of described anisotropic dry etch process includes: carve
Erosion gas includes the mixed gas of chlorine, hydrogen bromide or chlorine and hydrogen bromide, and the flow of hydrogen bromide is 200
Standard milliliters is per minute～800 standard milliliters are per minute, and the flow of chlorine is that 20 standard milliliters are per minute～100
Standard milliliters is per minute, and the flow of noble gas is that 50 standard milliliters are per minute～1000 standard milliliters every point
Clock, the pressure of etching cavity is 2 millitorrs～200 millitorrs, and etch period is 15 seconds～60 seconds.
In other embodiments, the transistor formed is PMOS transistor, the stressor layers being subsequently formed
Material is SiGe.Owing to the carrier of PMOS transistor is hole, and the mobility in hole is relatively low, for
The channel region making PMOS transistor obtains bigger stress, needs to make described stressor layers arrive grid layer
Distance is less, it is therefore desirable to make the sidewall of described opening substrate 200 sunken inside bottom described grid layer,
Make the sidewall of described opening and substrate 200 surface in " Σ " shape；When forming described opening, using
After anisotropic dry etch process forms the groove that sidewall is perpendicular to substrate 200 surface, use each
Heterotropic wet-etching technology etches sidewall and the lower surface of described groove；Due to described anisotropy
Wet-etching technology etch rate on<111>crystal orientation the slowest, and the crystal orientation on described substrate 200 surface
For<100>or<110>, therefore, it is possible to make the sidewall of formed groove form drift angle, and described drift angle is to lining
The end 200 sunken inside；And the etching liquid of described anisotropic wet-etching technology is alkaline solution, described
Alkaline solution be potassium hydroxide (KOH), sodium hydroxide (NaOH), Lithium hydrate (LiOH),
Ammonia (NH4OH) one or more combinations or in Tetramethylammonium hydroxide (TMAH).
Refer to Fig. 6, in described opening 202 (as shown in Figure 5), form stressor layers 203.
In the present embodiment, the transistor formed is nmos pass transistor, the most described stressor layers 203
Material be carborundum, the substrate 200 bottom grid structure 201 can be provided by described stressor layers 203
Tension, to improve the electronics mobility at channel region.In described stressor layers 203, also doped with n
Type ion, in order to form source region and drain region in the substrate 200 of grid structure 201 both sides.Real at other
Executing in example, described transistor is PMOS transistor, and the material of described stressor layers is SiGe.
The forming step of described stressor layers 203 includes: in sidewall and the lower surface shape of described opening 202
Become Seed Layer；The stress material layer filling full described opening 202 is formed on described Seed Layer surface.Described
The formation process of Seed Layer is chemical vapor deposition method, physical gas-phase deposition or ald work
Skill；Described Seed Layer is used for epitaxial growth stress material layer.In the present embodiment, the shape of described Seed Layer
One-tenth technique is atom layer deposition process, and described atom layer deposition process can form the Seed Layer of thinner thickness,
And the Seed Layer using atom layer deposition process to be formed has good gradient coating performance, it is possible to closely cover
It is placed on sidewall and the lower surface of opening 202.
The formation process of described stress material layer is epitaxial deposition process.In the present embodiment, described in answer dead-wood
The material of the bed of material is carborundum, and formation process is selective epitaxial depositing operation, including: temperature is 500
Degree Celsius～800 degrees Celsius, air pressure is 1 torr～100 torr, and deposition gases includes silicon source gas (SiH4Or
SiH2Cl2) and carbon-source gas (CH4、CH3Cl or CH2Cl2), described silicon source gas and carbon-source gas
Flow be 1 standard milliliters/minute～1000 standard milliliters/minute.Additionally, described selective epitaxial deposition
The gas of technique also includes HCl and H2, the flow of described HCl be 1 standard milliliters/minute～1000 standards
Ml/min, H2Flow be 0.1 standard liter/min～50 standard liter/min.
In the present embodiment, in described selective epitaxial deposition process, it is possible to doping work in situ
Skill is adulterated N-shaped ion in stress material layer, and described N-shaped ion includes phosphonium ion or arsenic ion；Described
Dopant ion distribution in doping process can regulate and control source region or drain region in situ and dopant ion concentration, thus
It can be avoided that dopant ion spreads, suppress short-channel effect.In other embodiments, it is possible in shape
After becoming stressor layers 203, or after being subsequently formed cover layer, with ion implantation technology at described stress
Doping N-shaped ion in layer 203.
Refer to Fig. 7, form cover layer 204 on described stressor layers 203 surface, in described cover layer 204
Doped with oxygen group elements ion.
Described cover layer 204 is positioned at stressor layers 202 surface, in follow-up silication technique for metal transfer
Turn to the electric contacting layer of metal silicide materials；Owing to stressor layers 203 is interior doped with p-type ion or N-shaped
Ion to form source region or drain region, described in be positioned at the electric contacting layer on stressor layers 203 surface follow-up for reducing
It is formed at the resistance between the electric interconnection structure on electric contacting layer surface and described stressor layers 203, thus increases
The operating current of transistor, improves the performance of transistor.
The formation process of described cover layer 204 is selective epitaxial depositing operation.In the present embodiment, institute
State the carborundum that material is doping oxygen group elements (Group VIA element) ion of cover layer 204；Described oxygen
Race's element ion is sulphion, plasma selenium or tellurium ion；Adulterate in cover layer 204 chalcogen element ion
Technique be in situ doping process or ion implantation technology.
In the present embodiment, the material of described cover layer 204 includes carborundum, and described stressor layers 203
Material be carborundum, therefore formed described cover layer 204 time, it is possible to based on formed stressor layers 203
The technique of Shi Xiangtong, and add the technique of doping chalcogen element ion doping, make formation cover layer 204
Technique is relatively simple.
Adulterate after chalcogen element ion in cover layer 204, follow-up conversion by described cover layer 204 and
The electric contacting layer material become is the metal silicide materials of doping chalcogen element ion；Described doping chalcogen unit
The metal silicide materials of element ion is come compared to the metal silicide materials of undoped p oxygen group elements ion
Say have lower Schottky barrier, then carrier jumps between stressor layers 203 and described electric contacting layer
The difficulty moved reduces, and the resistance between stressor layers 203 and the electric interconnection structure being subsequently formed reduces, thus
Improve the operating current of transistor, adapt to the manufacturing technology demand of more minute sized semiconductor device.
In the present embodiment, in situ doping process is used to adulterate in cover layer 204 chalcogen element ion；
Described original position doping process can make the doping content of the oxygen group elements ion being doped in cover layer 204 divide
Cloth is more uniformly distributed, and is conducive to improving the quality of the follow-up electric contacting layer being transformed by described cover layer 204.
And, use in situ doping process can in cover layer 204 doping content higher oxygen group elements ion,
Thus be more beneficial for reducing the contact resistance between the electric contacting layer being subsequently formed and stressor layers 203.At this
In embodiment, in described cover layer 204, the atom percentage concentration of the sulphion of doping is 0.1～5%.
In the present embodiment, owing to the technique of doping chalcogen element ion is original position doping process, therefore exist
The oxygen group elements ion adulterated in cover layer 204 is sulphion；The technique of doping sulphion includes:
Formed in the selective epitaxial depositing operation of cover layer 204, add sulfur source gas, described sulfur source gas bag
Including one or more combinations in hydrogen sulfide, sulfur dioxide, sulfur fluoride, the flow of described sulfur source gas is 1
Standard milliliters/minute～1000 standard milliliters/minute.
In other embodiments, in cover layer 204 the oxygen group elements ion of doping be plasma selenium or tellurium from
Son, the technique of adulterate described plasma selenium or tellurium ion includes: formed using selective epitaxial depositing operation
The initial overlay layer of carbofrax material；Use ion implantation technology in described initial overlay layer doped selenium from
Son or tellurium ion, form cover layer 204.
The thickness of described cover layer 204 is 3 nanometers～50 nanometers, and oxygen group elements ion is at described cover layer
It is uniformly distributed in 204；Owing to follow-up needs are converted into electric contacting layer with described cover layer 204, then described in cover
The thickness of cap rock 204 determines the thickness of the electric contacting layer being subsequently formed；In order to ensure follow-up metallic silicon
In metallization processes, metallic atom can spread and be uniformly distributed in cover layer 204, described cover layer 204
Thickness unsuitable blocked up；And, in order to ensure that the electric contacting layer resistance formed by cover layer 204 is less,
The thickness of described cover layer 204 is also unsuitable too small.
After forming described cover layer 204, silication technique for metal is used to make described cover layer 204 convert
For electric contacting layer, the material of described electric contacting layer is the metal silicide doped with oxygen group elements ion.With
Lower the forming step of electric contacting layer will be illustrated.
Refer to Fig. 8, form metal on described substrate 200, cover layer 204 and grid structure 201 surface
Layer 205.
In the present embodiment, after forming described opening 202 (as shown in Figure 5), described second is retained
Mask layer, the most described second mask layer can be as the mask of described silication technique for metal；Described second covers
Film layer exposes described grid structure 201 and described cover layer 204 surface, due to the table of described grid layer
Mask has the first mask layer, and the most described silication technique for metal will not form metal on described grid layer surface
Layer of suicide material.
The material of described metal level 205 is nickel or platinum, and the formation process of described metal level 205 is chemistry gas
Phase depositing operation, physical gas-phase deposition or atom layer deposition process.Described metal level 205 is used for
In the first follow-up annealing process, provide metallic atom to described cover layer 204 so that cover layer 204
The electric contacting layer of metal silicide materials can be converted into.
In the present embodiment, the material of described metal level 205 is nickel；In the first follow-up annealing process,
Nickle atom is to described cover layer 204 internal diffusion, it is possible to form the nisiloy carbon compound mixing sulfur, compared to gold
Belong to the material of layer 205 when being cobalt, described in mix the nisiloy carbon compound of sulfur there is lower Schottky barrier,
The electric contacting layer making to be subsequently formed is conducive to have lower resistance.
Refer to Fig. 9, use the first annealing process to make the metallic atom in metal level 205 to cover layer 204
(as shown in Figure 8) internal diffusion, makes cover layer 204 be converted into electric contacting layer 206.
In described first annealing process, the metallic atom in metal level 205 to cover layer 204 internal diffusion,
Be combined with the material of cover layer 204, become metal silicide materials, make described cover layer 204 be converted into
Electric contacting layer 206.
In the present embodiment, the material of described cover layer 204 is the carborundum mixing sulfur, and the electricity formed connects
Contact layer 206 is to mix the carbon nickle silicide of sulfur；For the carbon nickel suicide material not mixing sulfur, described electricity connects
Contact layer 206 has lower Schottky barrier, between the most described electric contacting layer 206 and stressor layers 203
Contact resistance is less, is conducive to reducing further the operating current of transistor, improves the performance of transistor.
Described first annealing process is rapid thermal annealing, spike thermal annealing or laser thermal anneal.When first moves back
When ignition technique is short annealing, the temperature of described rapid thermal annealing is 200～500 DEG C, and the time is 10 seconds～120
Second, protective gas is nitrogen or noble gas；When the first annealing process is spike thermal annealing, temperature is
300～600 DEG C, protective gas is nitrogen or noble gas；When the first annealing process is laser thermal anneal,
Temperature is 500～900 DEG C, and the time is 0.1 millisecond～2 milliseconds, and protective gas is nitrogen or noble gas.
Electric contacting layer 206 material formed is metal silicide materials, and described annealing process can drive
Metallic atom in metal level 205 enters in cover layer 204, at least makes part of covering layer 204 be converted into
Electric contacting layer 206, and the thickness of formed electric contacting layer 206 increases with the prolongation of annealing time.
Refer to Figure 10, after described first annealing process, remove remaining metal level 205 (such as Fig. 9
Shown in).
The technique removing described metal level 205 is dry etch process or wet-etching technology.Implement one
In example, the technique removing described metal level 205 is wet-etching technology, the quarter of described wet-etching technology
Erosion selectivity is preferable, and the damage to electric contacting layer 206, substrate 200 and grid structure 201 is less.
In one embodiment, after removing metal level 205, additionally it is possible to remove the second mask layer；Remove
The technique of described second mask layer is dry etch process or wet-etching technology.
In the present embodiment, after being additionally included in the remaining metal level 205 of removal, the second lehr attendant is carried out
Skill.Described second annealing process is for making metallic atom more uniformly spreading in electric contacting layer 206.
Described second annealing process and the first annealing process are identical or different.
In one embodiment, it is additionally included in described electric contacting layer 206 surface and forms electric interconnection structure.Described
The formation process of electric interconnection structure includes: on electric contacting layer 206, substrate 200 and grid structure 201 surface
Forming dielectric layer (sign), the surface of described dielectric layer is higher than or is flush to described grid structure 201
Top surface, the surface of described dielectric layer is smooth, and the material of described dielectric layer be silicon oxide, silicon nitride,
One or more combinations in silicon oxynitride, low-K dielectric material；Dielectric layer described in etched portions, in institute
Form, in stating dielectric layer, the through hole exposing electric contacting layer 206 surface；Conduction material is filled in described through hole
Material, forms described electric interconnection structure.After filling described conductive material, additionally it is possible to use chemical machinery
Glossing removes the conductive material of dielectric layer surface wholly or in part.
Owing to the resistivity of described electric contacting layer 206 is relatively low, and between electric contacting layer and stressor layers 203
Contact resistance is relatively low, and the contact resistance between the most described electric interconnection structure and stressor layers 203 is relatively low so that
Electric current in channel region between source region and drain region increases, and advantageously reduces the problems such as leakage current with this.
In one embodiment, described electric contacting layer can also after forming the through hole in described dielectric layer,
Formed before forming described electric contacting layer.I.e. after forming cover layer, at cover layer, substrate and grid
Body structure surface forms dielectric layer, and the surface of described dielectric layer is higher than or is flush to the top of described grid structure
There is in surface, and described dielectric layer the through hole exposing cover layer；Silication technique for metal is used to make described
The cover layer of via bottoms is converted into electric contacting layer.
In another embodiment, the transistor formed is high-k/metal gate (High k Metal Gate, letter
Claim HKMG) transistor, the technique forming described transistor includes rear grid (Gate Last) technique.Tool
Body, form dielectric layer at described substrate 200 and cover layer 204 surface, and described dielectric layer exposes
After the top surface of described grid structure 201, remove described grid layer, formed in described dielectric layer
Gate openings；Lower surface in described gate openings forms high-k dielectric layer, and (dielectric coefficient of material is big
In or equal to 4)；Metal gate is formed on described high-k dielectric layer surface.
To sum up, in the present embodiment, after stressor layers surface forms cover layer, mix in described cover layer
Miscellaneous oxygen group elements ion；After follow-up employing silication technique for metal makes cover layer be converted into electric contacting layer,
Can make formed electric contacting layer material is the metal silicide doped with oxygen group elements ion.Due to warp
Crossing research to find, the chalcogen element ion that adulterates in metal silicide materials can reduce metal silicide material
The Schottky barrier of material, therefore, the Schottky barrier of the electric contacting layer formed reduces, and the most described electricity connects
The resistance of contact layer reduces such that it is able to reduce between described stressor layers and follow-up formed electric interconnection structure
Resistance.Owing to the resistance between stressor layers and follow-up formed electric interconnection structure reduces, it is possible to increase
Electric current between electric interconnection structure and stressor layers, thus improve the operating current of formed transistor, make
The performance of the transistor formed is more stable, and reliability improves.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a transistor, it is characterised in that including:
Substrate is provided；
Grid structure is formed at described substrate surface；
Opening is formed in the substrate of described grid structure both sides；
Stressor layers is formed in described opening；
Form cover layer on described stressor layers surface, described cover layer is interior doped with oxygen group elements ion；
Silication technique for metal is used to make described cover layer be converted into electric contacting layer, the material of described electric contacting layer
For the metal silicide doped with oxygen group elements ion.
2. the forming method of transistor as claimed in claim 1, it is characterised in that the material of described stressor layers
For carborundum；Doped with N-shaped ion in described stressor layers.
3. the forming method of transistor as claimed in claim 1, it is characterised in that the formation of described stressor layers
Step includes: sidewall and lower surface at described opening form Seed Layer；On described Seed Layer surface
Form the stress material layer filling full described opening.
4. the forming method of transistor as claimed in claim 3, it is characterised in that the formation of described Seed Layer
Technique is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process；Described should
The formation process of the dead-wood bed of material is epitaxial deposition process.
5. the forming method of transistor as claimed in claim 1, it is characterised in that the material of described cover layer
Carborundum for the chalcogen element ion that adulterates.
6. the forming method of transistor as claimed in claim 5, it is characterised in that the formation of described cover layer
Technique is epitaxial deposition process.
7. the forming method of transistor as claimed in claim 1, it is characterised in that mix in described cover layer
Miscellaneous oxygen group elements ion is sulphion, plasma selenium or tellurium ion.
8. the forming method of transistor as claimed in claim 7, it is characterised in that doped with oxygen in cover layer
The technique of race's element ion is original position doping process or ion implantation technology.
9. the forming method of transistor as claimed in claim 8, it is characterised in that use doping process in situ
Adulterate in cover layer chalcogen element ion, and when the oxygen group elements ion of doping is sulphion, technique
Gas includes one or more in hydrogen sulfide, sulfur dioxide, sulfur fluoride.
10. the forming method of transistor as claimed in claim 7, it is characterised in that when mixing in described cover layer
When miscellaneous oxygen group elements ion is sulphion, the atom percentage concentration of described sulphion is 0.1～5%.
The forming method of 11. transistors as claimed in claim 1, it is characterised in that the thickness of described cover layer
It is 3 nanometers～50 nanometers.
The forming method of 12. transistors as claimed in claim 1, it is characterised in that described silication technique for metal
Including: at described substrate, cover layer and grid structure forming metal layer on surface；Use the first lehr attendant
Skill makes the metallic atom in metal level to cover layer internal diffusion, makes cover layer be converted into electric contacting layer；?
After described first annealing process, remove remaining metal level.
The forming method of 13. transistors as claimed in claim 12, it is characterised in that the material of described metal level
For nickel or platinum.
The forming method of 14. transistors as claimed in claim 12, it is characterised in that also include: surplus removing
After remaining metal level, carry out the second annealing process.
The forming method of 15. transistors as claimed in claim 1, it is characterised in that described grid structure includes:
The gate dielectric layer, the gate electrode layer being positioned at gate dielectric layer surface that are positioned at substrate surface and be positioned at grid electricity
Pole layer and gate dielectric layer both sides sidewall and the side wall of substrate surface.
The forming method of 16. transistors as claimed in claim 15, it is characterised in that the material of described gate dielectric layer
Material is silicon oxide；The material of described gate electrode layer is polysilicon.
The forming method of 17. transistors as claimed in claim 16, it is characterised in that also include: forming institute
After stating cover layer, forming dielectric layer at described substrate and cover surface, described dielectric layer exposes
The top surface of described grid structure；Remove described gate electrode layer, in described dielectric layer, form grid
Opening；Lower surface in described gate openings forms high-k dielectric layer；At described high-k dielectric layer table
Face forms metal gate.
The forming method of 18. transistors as claimed in claim 1, it is characterised in that the formation step of described opening
Suddenly include: forming mask layer at described substrate and grid structure surface, described mask layer exposes described
The section substrate surface of grid structure both sides；With described mask layer as mask, etch described substrate,
Opening is formed in described substrate.
The forming method of 19. transistors as claimed in claim 18, it is characterised in that form the quarter of described opening
Etching technique includes dry etch process.
The forming method of 20. transistors as claimed in claim 1, it is characterised in that also include: at described electricity
Contact layer surface forms electric interconnection structure.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109087852A (en) * | 2018-08-10 | 2018-12-25 | 深圳市华星光电技术有限公司 | The production method of transistor metal electrode structure |
| CN110364438A (en) * | 2019-05-29 | 2019-10-22 | 北京华碳元芯电子科技有限责任公司 | Transistor and its manufacturing method |
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| CN1508846A (en) * | 2002-12-19 | 2004-06-30 | 株式会社瑞萨科技 | Semiconductor device and its manufacturing method |
| WO2015001863A1 (en) * | 2013-07-04 | 2015-01-08 | 住友電気工業株式会社 | Method for manufacturing silicon carbide semiconductor device |
| CN105280492A (en) * | 2014-07-21 | 2016-01-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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| CN1508846A (en) * | 2002-12-19 | 2004-06-30 | 株式会社瑞萨科技 | Semiconductor device and its manufacturing method |
| WO2015001863A1 (en) * | 2013-07-04 | 2015-01-08 | 住友電気工業株式会社 | Method for manufacturing silicon carbide semiconductor device |
| CN105280492A (en) * | 2014-07-21 | 2016-01-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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| CN109087852A (en) * | 2018-08-10 | 2018-12-25 | 深圳市华星光电技术有限公司 | The production method of transistor metal electrode structure |
| CN109087852B (en) * | 2018-08-10 | 2020-09-08 | 深圳市华星光电技术有限公司 | Method for manufacturing transistor metal electrode structure |
| CN110364438A (en) * | 2019-05-29 | 2019-10-22 | 北京华碳元芯电子科技有限责任公司 | Transistor and its manufacturing method |
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