WO2024065277A1

WO2024065277A1 - Semiconductor device, preparation method and electronic device

Info

Publication number: WO2024065277A1
Application number: PCT/CN2022/122134
Authority: WO
Inventors: 宋以斌; 陈栋
Original assignee: 华为技术有限公司
Priority date: 2022-09-28
Filing date: 2022-09-28
Publication date: 2024-04-04

Abstract

A semiconductor device, a preparation method and an electronic device, which relate to the technical field of semiconductors. The semiconductor device is provided with contact holes, wherein a metal layer and an isolation layer are provided in each contact hole; the metal layer is in contact with a contact portion by means of the contact hole; the isolation layer is arranged between an inner wall of the contact hole and the metal layer; and materials for the realization of the isolation layer comprise a dense material. It is less likely to break down a dense material than a common dielectric material. Therefore, by means of providing an isolation layer, which is made of materials comprising the dense material, between an inner wall of each contact hole and a metal layer with which the contact hole is filled, the phenomenon of ions in the metal layer breaking down the isolation layer and diffusing outside the contact hole can be effectively prevented, thereby facilitating a reduction in the risk of short-circuiting between the contact hole and the other contact holes or an active area of a device. Moreover, in the solution, there is no need to make the hole diameter of the contact hole very small, thereby facilitating an improvement in process windows for an etching process and a subsequent filling process of the contact hole and a reduction in the difficulty of preparing the semiconductor device.

Description

Semiconductor device, preparation method and electronic device

Technical Field

The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and an electronic device.

Background technique

In semiconductor devices, contact holes play a vital role in the structure of semiconductor devices as the channels for interconnecting multiple metal layers and connecting the active area of the device (such as source, drain or gate, etc.) with other devices in the chip. However, with the development and popularization of semiconductor technology, the number of contact holes per unit area in semiconductor devices has increased exponentially, which has led to smaller and smaller spacing between contact holes and between contact holes and device active areas, and thus the risk of short circuits between contact holes and between contact holes and device active areas has increased.

In order to solve the above problems, in an existing implementation method, the diameter of the contact hole can be miniaturized to increase the spacing between the contact holes and between the contact hole and the device active area, so as to achieve the purpose of reducing the risk of short circuits between the contact holes and between the contact hole and the device active area. However, the smaller the diameter of the contact hole, the more difficult it is to etch the contact hole to the bottom, and the more likely it is to have filling voids when the contact hole is subsequently filled, which is not conducive to improving the reliability of semiconductor devices. It can be seen that the solution of miniaturizing the diameter of the contact hole poses a huge challenge to the etching process of the contact hole and the subsequent filling process, which is not conducive to reducing the difficulty of manufacturing semiconductor devices.

Based on this, there is a need for a semiconductor device to reduce the difficulty of manufacturing the semiconductor device.

Summary of the invention

The present application provides a semiconductor device, a preparation method and an electronic device, which are used to reduce the difficulty of preparing the semiconductor device.

In a first aspect, the present application provides a semiconductor device, comprising a contact portion, a stacking structure, a first isolation layer and a first metal layer. The contact portion is arranged on a substrate, and the stacking structure is stacked on one side of the contact portion. The stacking structure comprises at least one etching stop layer and at least one dielectric layer alternately stacked, and the stacking structure has a first contact hole, which penetrates the stacking structure and is connected to the contact portion. A first isolation layer and a first metal layer are arranged in the first contact hole, the first metal layer contacts the contact portion through the first contact hole, the first isolation layer is arranged between the first metal layer and the inner wall of the first contact hole, and the implementation material of the first isolation layer comprises a dense material.

In the above design, dense materials are less likely to break down than general dielectric materials. By setting a first isolation layer made of dense materials between the inner wall of the first contact hole and the first metal layer filled in the first contact hole, the phenomenon of ions of the first metal layer breaking through the first isolation layer and diffusing outward can be effectively prevented. In this way, even if the spacing between the first contact hole and other contact holes or between the first contact hole and the device active area is small, the first isolation layer can be used to isolate the first metal layer filled in the first contact hole from the metal layers or device active areas filled in other contact holes, effectively reducing the risk of short circuits between the first contact hole and other contact holes and between the first contact hole and the device active area. It can be seen that this design does not require the aperture of the first contact hole to be made very small, thereby improving the process window of the etching process of the first contact hole and the subsequent filling process, which helps to reduce the difficulty of manufacturing semiconductor devices.

In one possible design, the thickness of the first isolation layer can be less than 100 angstroms.

Through this design, even if a first isolation layer is deposited on the inner wall of the first contact hole, since the first isolation layer is a very thin layer, the operation of depositing the first isolation layer has little effect on the aperture of the first contact hole, thereby reducing the impact on the process window of the subsequent first metal layer filling process.

In one possible design, the first isolation layer may be deposited on the inner wall of the first contact hole by atomic layer deposition (ALD) technology. ALD technology has good consistency and can closely fit a very thin (e.g., less than 100 angstroms) first isolation layer on the inner wall of the first contact hole. In this way, the aperture of the first contact hole after deposition can be as close as possible to the aperture of the first contact hole before deposition, thereby reducing the impact on the subsequent filling of the first metal layer, increasing the process window for filling the first metal layer in the first contact hole, and minimizing the cost impact on the semiconductor device.

In a possible design, the dense material may be a single material or a composite material with a high K value (K value is understood as a density parameter value, the larger the K value of a material, the denser the material), for example, including but not limited to: silicon nitride (SiN); a composite material of silicon nitride and silicon oxide (SiO ₂ ); a composite material of silicon nitride and metal oxide, wherein the metal oxide may be, for example, aluminum oxide; metal oxide, etc. By using a material with a high K value as a dense material, its density can meet the requirements of anti-breakdown strength, and the isolation function of the first isolation layer can be effectively realized.

In the present application, the dielectric layer is also referred to as a dielectric layer, an interlayer dielectric layer or an interlayer dielectric layer (ILD), which is an electrical insulating layer disposed between different layers of a semiconductor device. In one example, the dielectric layer can be made of a silicon dioxide (SiO ₂ ) material having a dielectric constant of 3.9 to 4.0, so as to utilize the strong insulation of the silicon dioxide material to better isolate other layers disposed on both sides of the dielectric layer.

In the present application, the etching stop layer is a layer used to limit the etching process to prevent over-etching. In one example, the etching stop layer can be made of silicon nitride (SiN) material, so as to utilize the high stress of silicon nitride to neutralize the tensile stress of the dielectric layer adjacent to the silicon nitride, thereby changing the interface characteristics of the dielectric layer, increasing the breakdown voltage of the dielectric layer, and effectively improving the reliability of the semiconductor device.

In one possible design, the etching selectivity ratio of any etch stop layer and the adjacent dielectric layer can be greater than 1, that is, the speed of etching the dielectric layer using the same etching material will be faster than the speed of etching the adjacent etch stop layer, so as to ensure that the dielectric layer is etched quickly to the bottom while the etch stop layer is accurately stopped at the desired position by slowly etching.

In a possible design, the first contact hole may be an inclined hole, that is, the hole wall of the first contact hole is inclined along the stacking direction. Since the inclined hole is relatively easy to prepare, the requirements for the contact hole preparation process can be reduced.

In a possible design, the first isolation layer is disposed between the first metal layer and the inner wall of the first contact hole, and specifically, the first isolation layer is disposed around the first metal layer and the entire inner wall of the first contact hole. In this way, the entire peripheral area of the first metal layer filled in the first contact hole can be surrounded by the first isolation layer, thereby effectively preventing the first metal layer ions filled in the first contact hole from diffusing to the outside of the inner wall of the first contact hole, thereby improving the reliability of the first contact hole.

In one possible design, the first metal layer contacts the contact portion, which may specifically mean that the contact portion contacts both the first metal layer and the first isolation layer. In this way, by making the entire conductive interface of the first metal layer contact the contact portion, it helps to expand the flow area of the first metal layer and effectively improve the conductive performance of the contact hole.

In a possible design, the material for implementing the first metal layer may include copper, cobalt, tungsten or rubidium, so as to utilize the strong conductivity of these metals to improve the effect of connecting the active region of the device with other devices.

In the present application, the contact portion may be a source, a drain, a gate, or a second metal layer filled in the second contact hole. When the contact portion is a source, a drain, or a gate, an isolation layer may be provided on the inner wall of the contact hole directly contacting the device active area to reduce the risk of short circuit between the contact hole directly contacting the device active area and other contact holes or other device active areas. When the contact portion is a second metal layer filled in the second contact hole, an isolation layer may be provided on the inner wall of the first contact hole contacting the second contact hole to reduce the risk of short circuit between the first contact hole contacting the second contact hole and other contact holes other than the second contact hole and the first contact hole or other device active areas other than the device active area connected to the second contact hole.

The following is a further introduction to the structure of semiconductor devices from different types of contact parts:

Case 1: The contact is the source or drain

In this case, at least one etching stop layer may include a first etching stop layer and a second etching stop layer, and at least one dielectric layer may include a first dielectric layer. In this design, by providing an isolation layer between the inner wall of the contact hole directly contacting the source or the contact hole directly contacting the drain and the metal layer filled in the contact hole directly contacting the source or the contact hole directly contacting the drain, the metal layer filled in the contact hole directly contacting the source or the contact hole directly contacting the drain can be isolated from the metal layers filled in other contact holes or other device active areas, thereby effectively avoiding the phenomenon of short circuit between the source or the drain and other device active areas. Moreover, the substrate, the first etching stop layer, the first dielectric layer and the second etching stop layer can constitute the first layer structure of the semiconductor device. The source or drain is connected to the top plane of the first layer structure by the metal layer filled in the contact hole that directly contacts the source or the metal layer filled in the contact hole that directly contacts the drain. The source or drain can also be connected to other devices in the chip on the top plane of the first layer structure. In this way, part of the routing that needs to be set on the original plane where the source or drain is located can be dispersed to the top plane of the first layer structure, thereby reducing the routing pressure on the original plane where the source or drain is located.

In case 1, the source or drain is disposed on the substrate, which may specifically mean that: the source or drain is entirely buried in the substrate and connected to a side plane of the substrate relative to the stacking structure through a conductive medium, or the source or drain is buried in the substrate and one side surface is exposed to a side plane of the substrate relative to the stacking structure, or a portion of the source or drain is buried in the substrate and the other portion is exposed outside the substrate, or the source or drain is completely exposed outside the substrate and one side surface contacts a side plane of the substrate relative to the stacking structure. The conductive medium may be a single medium or a mixed medium having conductive capability, such as metal, alloy (such as copper alloy or aluminum alloy, etc.), composite metal, conductive plastic, conductive rubber, conductive fiber fabric, conductive coating, conductive adhesive, transparent conductive film and composite materials thereof, etc.

Case 2: The contact is the gate

In this case, the semiconductor device may further include a first etching stop layer and a first dielectric layer stacked in sequence between the substrate and the stack structure, at least one etching stop layer may include a second etching stop layer and a third etching stop layer, and at least one dielectric layer may include a second dielectric layer. The gate is located in the gate hole, and the gate hole may also include a side wall surrounding the gate. The gate hole penetrates the first etching stop layer and the first dielectric layer, and the bottom of the gate hole is buried in the substrate. In this design, by surrounding an isolation layer between the inner wall of the contact hole directly contacting the gate and the metal layer filled in the contact hole directly contacting the gate, the metal layer filled in the contact hole directly contacting the gate can be isolated from the metal layers filled in other contact holes and the source and drain, effectively avoiding the phenomenon of short circuit between the gate and the source or drain. Moreover, the substrate, the first etch stop layer, the first dielectric layer, the second etch stop layer, the second dielectric layer and the third etch stop layer can constitute the 1.5-layer structure of the semiconductor device. The gate is connected to the top plane of the 1.5-layer structure by the metal layer filled in the contact hole that directly contacts the gate. The routing of the gate connecting other devices can be set on the top plane of the 1.5-layer structure. In this way, part of the routing required on the original plane where the gate is located can be dispersed to the top plane of the 1.5-layer structure, thereby reducing the routing pressure on the original plane where the gate is located.

Based on the above-mentioned cases 1 and 2, the gate can be connected to the top plane of the 1.5-layer structure through the above-mentioned contact hole that directly contacts the gate, and the source can be connected to the top plane of the 1-layer structure through the above-mentioned contact hole that directly contacts the source, while the drain is still in the original plane, or the drain can be connected to the top plane of the 1-layer structure through the above-mentioned contact hole that directly contacts the drain, while the source is still in the original plane. In this way, by staggering the connection of the gate, source and drain to different planes through this contact hole design method, not only can it be avoided to set too dense routing on the same plane, which helps to reduce the difficulty of preparation of the back-end process, but it can also separate the routing connected to the gate, the routing connected to the source and the routing connected to the drain as much as possible in the back-end process, thereby further reducing the risk of short circuit between the gate, source and drain.

Case 3: The contact portion is the second metal layer filled in the second contact hole

In this case, the second contact hole can be a contact hole adjacent to the first contact hole in the stacking direction, such as a contact hole connected to the gate, a contact hole connected to the source, a contact hole connected to the drain, or a contact hole connected to the third metal layer filled in the third contact hole.

In a possible design, when the second contact hole is a contact hole connected to the source or drain, the semiconductor device may further include a first etch stop layer, a first dielectric layer, and a second etch stop layer stacked in sequence between the substrate and the stack structure, at least one etch stop layer may include a K-layer third etch stop layer, and at least one dielectric layer may include a K-layer second dielectric layer, where K is a positive integer. The second contact hole penetrates the first etch stop layer, the first dielectric layer, and the second etch stop layer, and the second contact hole is connected to the source or drain, and the source or drain is disposed on the substrate. In this design:

When the value of K is 1, the stacked structure includes a second dielectric layer and a third etch stop layer. In this case, in addition to the second contact hole directly contacting the source or drain, the semiconductor device may also include a first contact hole penetrating the third etch stop layer and the second dielectric layer, the first contact hole is connected to the second metal layer filled in the second contact hole, and the first metal layer and the first isolation layer are arranged in the first contact hole, the first metal layer contacts the second metal layer through the first contact hole, and the first isolation layer is arranged between the inner wall of the first contact hole and the first metal layer filled in the first contact hole. In this way, by setting a first contact hole penetrating an etch stop layer and a dielectric layer on the second contact hole directly contacting the source or drain, the source or drain can be further connected from the top plane of the first layer structure originally connected to the top plane of the 1.5 layer structure, while the other electrode in the source and the drain is still connected to the top plane of the first layer structure, which can effectively reduce the routing pressure in the top plane of the first layer structure. At the same time, an isolation layer is formed on the inside of the first contact hole, which can isolate the metal layer filled in the first contact hole from the metal layers filled in other contact holes except the first contact hole and the second contact hole or other device active areas except the device active area contacted by the second contact hole while connecting the source or drain to a higher plane, thereby effectively reducing the risk of short circuit between the source or drain and the surrounding device active areas.

When the value of K is 2, the stacked structure includes two second dielectric layers and two third etch stop layers. In this case, in addition to the second contact hole directly contacting the source or drain, the semiconductor device may also include a first contact hole penetrating the two third etch stop layers and the two second dielectric layers, the first contact hole is connected to the second metal layer filled in the second contact hole, and the first metal layer and the first isolation layer are arranged in the first contact hole, the first metal layer contacts the second metal layer through the first contact hole, and the first isolation layer is arranged between the inner wall of the first contact hole and the first metal layer filled in the first contact hole. In this example, the substrate, the first etching stop layer, the first dielectric layer, the second etching stop layer, the two second dielectric layers and the two third etching stop layers can constitute the second layer structure of the semiconductor device. By setting a first contact hole penetrating the two etching stop layers and the two dielectric layers on the second contact hole directly contacting the source or drain, the source or drain can be further connected from the top plane of the first layer structure originally connected to the top plane of the second layer structure. The top plane of the second layer structure is higher than the top plane of the 1.5 layer structure to which the gate is connected, while the other electrode in the source or drain is still connected to the top plane of the first layer structure. In this way, by connecting the gate, source and drain to different planes respectively, the routing in each plane can be laid out as evenly as possible. In addition, forming an isolation layer on the inner wall of the first contact hole can also isolate the first metal layer filled in the first contact hole from the metal layers filled in other contact holes except the first contact hole and the second contact hole or other device active areas except the device active area contacted by the second contact hole, effectively reducing the risk of short circuit between the source or drain and the surrounding device active area.

When the value of K is an integer greater than 2, the stacked structure includes at least three layers of second dielectric layers and at least three layers of third etch stop layers. In this case, in addition to the second contact hole directly contacting the source or drain, the semiconductor device may also include a first contact hole penetrating at least three layers of third etch stop layers and at least three layers of second dielectric layers, the first contact hole is connected to the second metal layer filled in the second contact hole, and the first metal layer and the first isolation layer are arranged in the first contact hole, the first metal layer contacts the second metal layer through the first contact hole, and the first isolation layer is arranged between the inner wall of the first contact hole and the first metal layer filled in the first contact hole. In addition to reducing the risk of short circuit between the source or drain and other device active areas, this design can also connect the source or drain to a higher plane higher than the top plane of the second layer structure through the first contact hole, so as to further disperse the routing on each plane when the density of the semiconductor device is further increased.

In another possible design, when the second contact hole is connected to the contact hole of the gate, the semiconductor device may also include a first etch stop layer, a first dielectric layer, a second etch stop layer, a second dielectric layer and a third etch stop layer stacked in sequence between the substrate and the stack structure, at least one etch stop layer may include a P-layer fourth etch stop layer, at least one dielectric layer may include a P-layer third dielectric layer, and P is a positive integer. The second contact hole penetrates the third etch stop layer, the second dielectric layer and the second etch stop layer and is connected to the gate, the gate is filled in the gate hole, the gate hole also includes a side wall surrounding the gate, the gate hole penetrates the first dielectric layer and the first etch stop layer, and the bottom of the gate hole is buried in the substrate. In this design:

When the value of P is 1, the stacked structure includes a third dielectric layer and a fourth etch stop layer. In this case, in addition to the second contact hole directly contacting the gate, the semiconductor device may also include a first contact hole penetrating a fourth etch stop layer and a third dielectric layer, the first contact hole is connected to the second metal layer filled in the second contact hole directly contacting the gate, and the first metal layer and the first isolation layer are arranged in the first contact hole, the first metal layer contacts the second metal layer through the first contact hole, and the first isolation layer is arranged between the inner wall of the first contact hole and the first metal layer filled in the first contact hole. In this way, by setting a first contact hole penetrating a dielectric layer and an etch stop layer on the second contact hole directly contacting the gate, the gate can be connected from the top plane of the 1.5-layer structure originally connected to the top plane of the 2-layer structure, so that when the density of the semiconductor device is further increased, it is possible to avoid setting too dense routing on the top plane of the 1.5-layer structure, thereby reducing the difficulty of preparation of the back-end process. At the same time, a first isolation layer is formed on the inner wall of the first contact hole, which can isolate the first metal layer filled in the first contact hole from the surrounding metal layer or the device active area while connecting the gate to a higher plane, thereby reducing the risk of short circuit between the gate and the surrounding device active area.

When the value of P is 2, the stacked structure includes two third dielectric layers and two fourth etch stop layers. In this case, in addition to the second contact hole directly contacting the gate, the semiconductor device may also include a first contact hole penetrating the two fourth etch stop layers and the two third dielectric layers, the first contact hole is connected to the second metal layer filled in the second contact hole directly contacting the gate, and the first metal layer and the first isolation layer are arranged in the first contact hole, the first metal layer is in contact with the second metal layer through the first contact hole, and the first isolation layer is arranged between the inner wall of the first contact hole and the first metal layer filled in the first contact hole. In this design, the substrate, the first etching stop layer, the first dielectric layer, the second etching stop layer, the second dielectric layer, the third etching stop layer, two third dielectric layers and two fourth etching stop layers constitute the 2.5-layer structure of the semiconductor device. By setting a first contact hole penetrating two dielectric layers and two etching stop layers on the second contact hole directly contacting the gate, the gate can be connected from the top plane of the 1.5-layer structure originally connected to the top plane of the 2.5-layer structure, and the top plane of the 2.5-layer structure is higher than the top plane of the 2-layer structure. In this way, when the density of the semiconductor device is further increased, it is possible to avoid setting too dense routing on the top plane of the 1.5-layer structure and the top plane of the 2-layer structure, thereby reducing the difficulty of preparation of the back-end process. At the same time, a first isolation layer is formed on the sidewall of the first contact hole, and the first metal layer filled in the first contact hole can be isolated from the surrounding metal layer or the device active area while connecting the gate to a higher plane, thereby reducing the risk of short circuit between the gate and the surrounding device active area.

When the value of P is an integer greater than 2, the stacked structure includes at least three third dielectric layers and at least three fourth etch stop layers. In this case, in addition to the second contact hole directly contacting the gate, the semiconductor device may also include a first contact hole that penetrates at least three fourth etch stop layers and at least three third dielectric layers, the first contact hole is connected to the second metal layer filled in the second contact hole directly contacting the gate, and the first metal layer and the first isolation layer are arranged in the first contact hole, the first metal layer contacts the second metal layer through the first contact hole, and the first isolation layer is arranged between the inner wall of the first contact hole and the first metal layer filled in the first contact hole. In addition to reducing the risk of short circuit between the gate and other device active areas, this design can also connect the gate to a higher plane higher than the top plane of the 2.5-layer structure through the first contact hole, so as to further disperse the routing on each plane when the density of the semiconductor device is further increased.

In the above situation 3, a second isolation layer may also be provided in the second contact hole, and the second isolation layer is provided between the inner wall of the second contact hole and the second metal layer. In this way, by providing an isolation layer on the inner wall of the second contact hole and the first contact hole provided on the second contact hole, the metal layers filled in the two contact holes can be isolated from the metal layers or device active areas filled in other contact holes, thereby helping to further reduce the risk of short circuits between contact holes and between contact holes and device active areas.

Furthermore, when a second isolation layer is disposed between the inner wall of the second contact hole and the second metal layer, the thickness of the second isolation layer may be less than 100 angstroms.

For example, the second isolation layer may also be deposited on the inner wall of the second contact hole by using the ALD technology to reduce the impact on the process window of the subsequent second metal layer filling process.

Furthermore, when a second isolation layer is set between the inner wall of the second contact hole and the second metal layer, the second isolation layer can be set around the entire inner wall of the second contact hole to effectively prevent the second metal layer ions filled in the second contact hole from diffusing outside the inner wall of the second contact hole, thereby improving the reliability of the second contact hole.

It should be understood that the relevant content of the above-mentioned first contact hole is also applicable to the second contact hole, the relevant content of the above-mentioned first metal layer is also applicable to the second metal layer, and the relevant content of the above-mentioned first isolation layer is also applicable to the second isolation layer, and this application will not repeat them one by one.

In the second aspect, the present application provides a method for preparing a semiconductor device, the method comprising: first forming a contact portion arranged on a substrate, then alternately stacking at least one etch stop layer and at least one dielectric layer on one side of the contact portion to obtain a stacked structure, then etching to form a first contact hole that penetrates the stacked structure and is connected to the contact portion, and finally forming a first isolation layer and a first metal layer in the first contact hole, the first isolation layer being arranged between the first metal layer and the inner wall of the first contact hole, and the first metal layer being in contact with the contact portion through the first contact hole.

In a possible design, forming a first isolation layer in the first contact hole includes: depositing the first isolation layer on the inner wall of the first contact hole by using ALD technology.

In one possible design, before etching to form a first contact hole that penetrates the stacked structure and is connected to the contact part, an organic material layer may be formed on the side of the stacked structure opposite to the contact part. In this case, etching to form a first contact hole that penetrates the stacked structure and is connected to the contact part may specifically mean: first photolithography a pattern at a position corresponding to the first contact hole on the organic material layer, then etching to form the first contact hole on the organic material layer and the stacked structure according to the pattern, and then removing the organic material layer.

In the above design, the organic material layer may include one or more layers of a spin-coated layer, a bottom anti-reflection layer, and a photoresist layer. Specifically, the number of layers of the organic material layer may also be positively correlated with the aperture of the contact hole to be etched. For example, in one example, the organic material layer may specifically include a spin-coated layer, a bottom anti-reflection layer, and a photoresist layer, and the spin-coated layer, the bottom anti-reflection layer, and the photoresist layer are sequentially stacked on a side of the stacked structure opposite to the contact portion.

In the embodiment of the present application, the contact portion may specifically be a device in any of the following situations:

Case 1: The contact is the source or drain

In this case, at least one etch stop layer and at least one dielectric layer are alternately stacked on one side of the contact portion, including: forming a substrate, a first etch stop layer, a first dielectric layer and a second etch stop layer stacked in sequence.

Case 2: The contact is the gate

In this case, the semiconductor device may also include a first etching stop layer and a first dielectric layer stacked in sequence between the substrate and the stack structure. The contact portion disposed on the substrate is formed by first forming a substrate, a first etching stop layer and a first dielectric layer stacked in sequence, then etching to form a gate hole penetrating the first etching stop layer and the first dielectric layer, and burying the bottom of the gate hole in the substrate, and then forming a gate and a sidewall surrounding the gate in the gate hole. Accordingly, at least one etching stop layer and at least one dielectric layer are alternately stacked on one side of the contact portion, including: stacking a second etching stop layer, a second dielectric layer and a third etching stop layer in sequence on the side of the first dielectric layer opposite to the first etching stop layer.

In a possible design, the second contact hole is a contact hole that directly contacts the source or drain. In this case, the semiconductor device may further include a first etching stop layer, a first dielectric layer, and a second etching stop layer that are stacked in sequence and arranged between the substrate and the stack structure. The contact portion arranged on the substrate is formed, including: first forming a substrate and a source or drain arranged on the substrate, then alternately stacking a first etching stop layer, a first dielectric layer, and a second etching stop layer on one side of the substrate, and then etching to form a second contact hole that penetrates the first etching stop layer, the first dielectric layer, and the second etching stop layer, and finally filling the second contact hole with a second metal layer, and making the second metal layer contact the source or drain. Accordingly, alternately stacking at least one etching stop layer and at least one dielectric layer on one side of the contact portion includes: alternately stacking K layers of the second dielectric layer and K layers of the third etching stop layer on the side of the second etching stop layer opposite to the first dielectric layer, where K is a positive integer.

In another possible design, the second contact hole is a contact hole that directly contacts the gate. In this case, the semiconductor device may also include a first etching stop layer, a first dielectric layer, a second etching stop layer, a second dielectric layer, and a third etching stop layer that are stacked in sequence between the substrate and the stack structure. The contact portion disposed on the substrate is formed by stacking the substrate, the first etching stop layer, and the first dielectric layer in sequence, etching to form a gate hole that penetrates the first etching stop layer and the first dielectric layer, the bottom of the gate hole is buried in the substrate, and a sidewall and a gate surrounded by the sidewall are formed in the gate hole, and then the second etching stop layer, the second dielectric layer, and the third etching stop layer are stacked on the side of the first dielectric layer opposite to the first etching stop layer, etching to form a second contact hole that penetrates the third etching stop layer, the second dielectric layer, and the second etching stop layer and is connected to the gate, and the second metal layer is filled in the second contact hole. Accordingly, at least one etching stop layer and at least one dielectric layer are alternately stacked on one side of the contact portion, including: a P-layer third dielectric layer and a P-layer fourth etching stop layer are stacked on the side of the third etching stop layer opposite to the second dielectric layer, and P is a positive integer.

In a possible design, filling the second metal layer in the second contact hole includes: forming a second isolation layer and the second metal layer in the second contact hole, and the second isolation layer is arranged between the inner wall of the second contact hole and the second metal layer.

In a possible design, forming the first isolation layer in the first contact hole includes: arranging the first isolation layer around the entire inner wall of the first contact hole.

It should be understood that the relevant design content of the above-mentioned first aspect is also applicable to the second aspect, and this application will not repeat them one by one.

In a third aspect, the present application provides an electronic device comprising a printed circuit board (PCB) and a semiconductor device as described in any one of the first aspects above, wherein the semiconductor device is arranged on a surface of the PCB.

Specifically, the electronic device includes but is not limited to: a smart phone, a smart watch, a tablet computer, a virtual reality (VR) device, an augmented reality (AR) device, a vehicle-mounted device, a desktop computer, a personal computer, a handheld computer or a personal digital assistant.

The above-mentioned various aspects or other aspects of the present application will be described in detail in the following embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 exemplarily shows a schematic structural diagram of a CMOS device provided in an embodiment of the present application;

FIG2 exemplarily shows a schematic diagram of a preparation process of a contact hole structure provided by the industry;

FIG3 exemplarily shows a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

FIG4 exemplarily shows a schematic diagram of a configuration of a contact portion and a substrate provided in an embodiment of the present application;

FIG5 exemplarily shows a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

FIG6 exemplarily shows a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

FIG7 exemplarily shows a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

FIG8 exemplarily shows a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

FIG9 exemplarily shows a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

FIG10 exemplarily shows a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

FIG. 11 exemplarily shows a schematic diagram of a process for preparing a semiconductor device provided in an embodiment of the present application;

FIG12 exemplarily shows a schematic diagram of a manufacturing process of another semiconductor device provided in an embodiment of the present application;

FIG13 exemplarily shows a schematic diagram of a manufacturing process of another semiconductor device provided in an embodiment of the present application;

FIG. 14 exemplarily shows a schematic diagram of a preparation process of another semiconductor device provided in an embodiment of the present application.

Detailed ways

The scheme disclosed in the present application can be applied to semiconductor devices with contact holes, including but not limited to logic devices or memory devices. Among them, the logic device may include, for example, a microprocessor, a sensor or an integrated circuit (IC) chip. The memory device may be a memory with only a storage function, such as a complementary metal oxide semiconductor (CMOS) device, a disk, a hard disk or a memory, or an electronic device with a storage function and other functions (such as a read and write function). The electronic device may be a portable electronic device including functions such as a personal digital assistant and/or a music player, such as a mobile phone, a tablet computer, a wearable device with a wireless communication function (such as a smart watch), or a vehicle-mounted device. Exemplary embodiments of portable electronic devices include but are not limited to devices equipped with

Or a portable electronic device with other operating systems. The portable electronic device may also be a laptop computer with a touch-sensitive surface (e.g., a touch panel). It should also be understood that in some other embodiments of the present application, the electronic device may also be a desktop computer with a touch-sensitive surface (e.g., a touch panel).

Exemplarily, the memory can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. The volatile memory can be a random access memory (RAM) that acts as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), flash eprom (FE), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM) and direct rambus RAM (DR RAM), as well as new types of memory such as ferroelectric random access memory (FeRAM), phase change random access memory (PCRAM), magnetic random access memory (MRAM) or resistive random access memory (ReRAM). The non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. It should be noted that the memory described in this application is intended to include, but is not limited to, these and any other suitable types of memory.

In a specific application scenario, the solution disclosed in the present application can be applied to CMOS devices. FIG1 exemplarily shows a schematic diagram of the structure of a CMOS device provided in an embodiment of the present application. As shown in FIG1 , in this example, the CMOS device may include a substrate 110 , a first etch stop layer 211 , a first dielectric layer 221 , a second etch stop layer 212 , a source 101 , a drain 102 , a gate 103 , and a sidewall 104 surrounding the gate 103 . The substrate 110, the first etching stop layer 211, the first dielectric layer 221 and the second etching stop layer 212 are stacked in sequence, the source 101 and the drain 102 are arranged in the substrate 110, and the upper surfaces of the source 101 and the drain 102 are exposed on a side plane of the substrate 110 relative to the first etching stop layer 211, the gate 103 and the sidewall 104 are located in the gate hole, the gate hole penetrates the first dielectric layer 221 and the first etching stop layer 211, and the bottom of the gate hole is buried in the substrate 110, and the upper surface of the gate 103 is exposed on a side plane of the first dielectric layer 221 relative to the second etching stop layer 212. In this example, the sidewall 104 can isolate the gate 103 from other device active areas (such as the source 101 and the drain 102), and prevent the gate 103 from being insufficiently filled in the gate hole to form a void.

It should be understood that the illustrated CMOS device is only an example, and the CMOS device may have more or fewer layers than those shown in the figure, may combine two or more layers, or may have different layer configurations. For example, in another example, the upper surface of the source 101 or the drain 102 may also be buried inside the substrate 110 without being exposed on a side plane of the substrate 110 relative to the first etching stop layer 211. In this case, the source 101 or the drain 102 may also be connected to a side plane of the substrate 110 relative to the first etching stop layer 211 through a conductive medium. For another example, in another example, if the complexity of the same-layer routing is not considered, the gate 103 may also be buried in the substrate 110 like the source 101 or the drain 102, and the upper surface may be exposed on a side plane of the substrate 110 relative to the first etching stop layer 211. In this case, the first dielectric layer 221 and the second etching stop layer 212 may no longer be provided in the CMOS device. It should be noted that there are many possible deformation methods, which are not listed here one by one.

In the embodiment of the present application, the gate, source and drain are referred to as the device active area, and the device active area also needs to be connected to other devices or lines in the chip, such as other transistors in the chip (such as back-end transistors), control circuits, or signal lines. Among them, the connection between the device active area and other devices in the chip can be achieved by preparing a contact hole structure in the semiconductor device and performing signal wiring on the contact hole structure. Exemplarily, based on the CMOS device shown in FIG1, FIG2 shows a schematic diagram of a preparation process of a contact hole structure provided by the industry. As shown in FIG2, the process includes:

Step 1, as shown in FIG. 2 (A), a source contact hole 120 (i.e., a contact hole directly contacting the source 101), a drain contact hole 121 (i.e., a contact hole directly contacting the drain 102) and a gate contact hole 122 (i.e., a contact hole directly contacting the gate 103) are formed by etching, wherein the source contact hole 120 at least penetrates the second etch stop layer 212, the first dielectric layer 221 and the first etch stop layer 211 and is connected to the source 101, the drain contact hole 121 at least penetrates the second etch stop layer 212, the first dielectric layer 221 and the first etch stop layer 211 and is connected to the drain 102, and the gate contact hole 122 at least penetrates the second etch stop layer 212 and is connected to the gate 103;

In step two, as shown in (B) in FIG2 , a metal layer 130 is filled in the source contact hole 120, the drain contact hole 121 and the gate contact hole 122. The metal layer 130 filled in the source contact hole 120 is used to connect the source 101 and other devices in the chip corresponding to the source 101, the metal layer 130 filled in the drain contact hole 121 is used to connect the drain 102 and other devices in the chip corresponding to the drain 102, and the metal layer 130 filled in the gate contact hole 122 is used to connect the gate 103 and other devices in the chip corresponding to the gate 103.

By adopting the preparation method shown in FIG. 2 , the source 101, the gate 103 and the drain 102 can be connected to a side plane (i.e., plane H) of the second etching stop layer 212 opposite to the first dielectric layer 221 through the metal layer 130 filled in the source contact hole 120, the drain contact hole 121 and the gate contact hole 122. Then, wiring can be set on the side plane H to connect the metal layer 130 filled in the source contact hole 120 and other devices in the chip corresponding to the source 101, the metal layer 130 filled in the drain contact hole 121 and other devices in the chip corresponding to the drain 102, and the metal layer 130 filled in the gate contact hole 122 and other devices in the chip corresponding to the gate 103, so as to realize the connection between the source 101, the drain 102 and the gate 103 and other devices in the chip. However, when the density of CMOS devices increases, the substrate 110 of the same area as shown in FIG. 2 will include more sources 101, gates 103 or drains 102. In this case, the number of contact holes required to be set on the plane perpendicular to the stacking direction will also increase accordingly, which makes the distance between any two contact holes and between the contact holes and other device active areas other than the device active area connected to the contact holes (such as the source contact hole 120 and the gate 103 or drain 102, the drain contact hole 121 and the gate 103 or source 101, and the gate contact hole 122 and the source 101 or drain 102) smaller. In this way, the metal layer 130 filled in any contact hole will more easily penetrate into other contact holes or other device active areas, resulting in an increased risk of short circuits between contact holes and between contact holes and other device active areas, and a reduced reliability of the CMOS device. Although the contact holes can be miniaturized to indirectly increase the spacing between the contact holes and between the contact holes and other device active areas, small-diameter contact holes are difficult to etch and are prone to voids during subsequent filling. This solution increases the difficulty of manufacturing CMOS devices and reduces the manufacturing yield of CMOS devices. In addition, the above-mentioned manufacturing method connects the source 101, the gate 103, and the drain 102 to the same plane H through the contact hole structure. As the density of CMOS devices increases, the wiring on the plane H will become more and more dense. The dense wiring is not only not conducive to the preparation of the back-end process (including setting the connection between the semiconductor device and other devices in the chip after the semiconductor is prepared), but may also cause short circuits between the wiring due to the short spacing between the wiring, further reducing the manufacturing yield and reliability of the CMOS device.

In view of this, an embodiment of the present application provides a semiconductor device for setting an isolation layer between the inner wall of a contact hole and the metal layer filled in the contact hole, and at the same time connecting different device active areas to different layers of the semiconductor device through the contact hole as much as possible. In this way, the risk of short circuit between the contact holes and between the contact holes and the device active areas can be reduced through the isolation effect of the isolation layer without making the aperture of the contact hole very small, which helps to reduce the difficulty of preparing the semiconductor device and improve the preparation yield and reliability of the semiconductor device. It can also minimize the number of routings required to be set in the same layer of the semiconductor device, reduce the difficulty of preparation of the subsequent process, and further improve the preparation yield and reliability of the semiconductor device.

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

It should be pointed out that in the following description of the present application, "multiple" can be understood as "at least two". "And/or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. "The following one or more items" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, one or more items of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or plural.

Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. For example, the "first etch stop layer", "second etch stop layer", "third etch stop layer" and "fourth etch stop layer" mentioned below are only used to indicate etch stop layers at different positions, and do not have different sequences, priorities or importance.

In addition, for the convenience of description, the following embodiments of the present application refer to the contact hole and the various layers or electrodes filled in the contact hole as the contact hole structure. For example, when the contact hole is completely filled with a metal layer, the contact hole structure refers to the contact hole and the metal layer filled inside. When the contact hole is filled with a metal layer and an isolation layer surrounding the metal layer, the contact hole structure refers to the contact hole, the metal layer filled in the contact hole, and the isolation layer disposed between the inner wall of the contact hole and the metal layer.

[Example 1]

FIG3 exemplarily shows a schematic structural diagram of a semiconductor device provided by an embodiment of the present application. As shown in FIG3 , in this example, the semiconductor device includes a contact portion 100, a stacked structure 200, a first isolation layer 310, and a first metal layer 320. The contact portion 100 is disposed on a substrate 110, the stacked structure 200 is stacked on one side of the contact portion 100, the stacked structure 200 includes at least one etch stop layer 210 and at least one dielectric layer 220 alternately stacked, the stacked structure 200 has a first contact hole 300, the first contact hole 300 penetrates the stacked structure 200 and is connected to the contact portion 100, the first metal layer 320 contacts the contact portion 100 through the first contact hole 300, the first isolation layer 310 is disposed between the first metal layer 320 and the inner wall of the first contact hole 300, and the material of the first isolation layer 310 includes a dense material. Among them, dense material refers to a material without residual pores or with a relative density of not less than 98%. Dense material has greater anti-breakdown strength than general dielectric materials. In this way, by setting a first isolation layer 310 made of dense material between the inner wall of the first contact hole 300 and the first metal layer 320 filled in the first contact hole 300, even if the metal ions of the first metal layer 320 filled in the first contact hole 300 move, they can be isolated in the first contact hole 300 by the first isolation layer 310 and will not move to other contact holes or device active areas outside the first contact hole 300. It can be seen that the first isolation layer 310 can isolate the first metal layer 320 filled in the first contact hole 300 from other contact holes or device active areas outside the first contact hole 300, and can effectively prevent the short circuit between the first contact hole 300 and other contact holes or device active areas.

It should be noted that the material used to implement the first isolation layer 310 includes a dense material, which may mean that the first isolation layer 310 is entirely made of dense material, or that the first isolation layer is made of a mixture of dense material and other materials, such as dense material and other materials with strong anti-breakdown strength. The embodiments of the present application do not make specific limitations on this.

In the embodiment of the present application, the dense material can be a single material or a composite material with a high K value (K value is understood as a density parameter value, and the larger the K value of a material, the denser the material), for example, it can include but is not limited to: silicon nitride (SiN); a composite material of silicon nitride and silicon oxide (SiO ₂ ); a composite material of silicon nitride and metal oxide, wherein the metal oxide can be, for example, aluminum oxide; metal oxide, etc. In this way, by using a material with a high K value as a dense material, its density can meet the requirements of anti-breakdown strength, and the isolation function of the first isolation layer 310 can be effectively realized.

In the embodiment of the present application, with the development of semiconductor technology, more and more contact holes need to be prepared in semiconductor devices of the same size, and the smaller the aperture of the contact hole, the thinner the isolation layer arranged between the inner wall of the contact hole and the metal layer needs to be, so as to reduce the process difficulty of filling the metal layer in the contact hole with a small aperture. However, it is very difficult to deposit a thinner isolation layer in a contact hole with a small aperture in terms of manufacturing process. To solve this problem, in one possible design, the first isolation layer 310 can be deposited on the inner wall of the first contact hole 300 by atomic layer deposition (ALD) technology. Among them, the ALD technology has good consistency and can tightly fit a very thin (for example, less than 100 angstroms) first isolation layer 310 on the inner wall of the first contact hole 300. In this way, the aperture of the first contact hole 300 after deposition can be as close as possible to the aperture of the first contact hole 300 before deposition, thereby reducing the impact on the subsequent filling of the first metal layer 320, increasing the process window for subsequent filling of the first metal layer 320 in the first contact hole 300, and using as little first isolation layer material as possible to minimize the cost impact on the semiconductor device.

In the embodiment of the present application, the contact portion 100 is disposed on the substrate 110 , which may mean that the contact portion 100 partially or completely contacts the substrate 110 . By way of example, FIG4 shows a schematic diagram of a contact portion and a substrate arrangement method provided in an embodiment of the present application, wherein the contact portion 100 is arranged on the substrate 110, which may refer to the contact portion 100 as shown in FIG4 (A) being entirely buried in the substrate 110 and connected to a side plane of the substrate 110 relative to the first etch stop layer 210 through a conductive medium, or may refer to the contact portion 100 as shown in FIG4 (B) being buried in the substrate 110 and a side surface of the contact portion 100 (the upper surface as shown in FIG4 (B)) being exposed on a side plane of the substrate 110 relative to the first etch stop layer 210, or may refer to the contact portion 100 as shown in FIG4 (C) being partially buried in the substrate 110 and another part being exposed outside a side plane of the substrate 110 relative to the first etch stop layer 210, or may refer to the contact portion 100 as shown in FIG4 (D) being entirely exposed outside the substrate 110 and a side surface (the lower surface as shown in FIG4 (D)) being in contact with a side plane of the substrate 110 relative to the first etch stop layer 210. Among them, the conductive medium can be a single medium or a mixed medium with conductive ability, such as metal, alloy (such as copper alloy or aluminum alloy, etc.), composite metal, conductive plastic, conductive rubber, conductive fiber fabric, conductive coating, conductive adhesive, transparent conductive film and its composite material, etc., without specific limitation.

It should be understood that the contact portion 100 may be disposed on the substrate 110 in other ways, and the embodiments of the present application do not specifically limit this.

In the embodiment of the present application, the metal layer 320 is also called a metal plug, which is an electrode with conductive ability made of metal material, and the material can include copper, cobalt, tungsten, rubidium or other metal materials with strong conductivity, so as to utilize the strong conductivity of these metal materials to improve the effect of the first metal layer 320 connecting the device active area. The metal layer 320 can be solid or hollow, such as a circular column surrounded by a thin layer of metal material.

In the embodiment of the present application, the dielectric layer 220 is also called a dielectric layer, an interlayer dielectric layer or an interlayer dielectric layer (ILD), which is an electrical insulating layer disposed between different layers of a semiconductor device and acts as an isolation film. In one example, the dielectric layer 220 can be made of a silicon dioxide (SiO ₂ ) material having a dielectric constant of 3.9 to 4.0, so as to utilize the strong insulation of the silicon dioxide material to better isolate other layers disposed on both sides of the dielectric layer 220.

In the embodiment of the present application, the etching stop layer 210 is a layer used to limit the etching process to prevent over-etching. In one example, the etching stop layer 210 can be made of silicon nitride (SiN) material, so as to use the high stress of silicon nitride to neutralize the tensile stress of the dielectric layer 220 adjacent to the silicon nitride, thereby changing the interface characteristics of the dielectric layer 220, improving the breakdown voltage of the dielectric layer 220, and effectively improving the reliability of the semiconductor device.

In the embodiment of the present application, the etching selectivity ratio between any etch stop layer 210 and the adjacent dielectric layer 220 in the stacked structure 200 can be set to be greater than 1. That is, the speed of etching the dielectric layer 220 using the same etching material will be faster than the speed of etching the adjacent etch stop layer 210, so that while ensuring that the dielectric layer 220 can be quickly etched to the bottom, the etch stop layer 210 can be accurately stopped at the desired position by slowly etching.

In the embodiment of the present application, the stack structure 200 may include N ₁ layers of etch stop layers 210 and N ₂ layers of dielectric layers 220 that are alternately stacked, and the values of N ₁ and N ₂ are the same or differ by 1. In one example, in order to avoid the phenomenon that the stack structure 200 is stacked with too many layers in the stacking direction and causes the semiconductor device to be too thick, N ₁ and N ₂ can be set to integers greater than or equal to 1 and less than or equal to 50. When the values of N ₁ and N ₂ are the same, the substrate 110 and the stack structure 200 can be stacked in the manner of substrate 110, etch stop layer 210, dielectric layer 220, ..., etch stop layer 210, dielectric layer 220, or can be stacked in the manner of substrate 110, dielectric layer 220, etch stop layer 210, ..., dielectric layer 220, etch stop layer 210. When the value of _N1 is greater than the value of _N2 by 1, the substrate 110 and the stacked structure 200 can be stacked in the manner of substrate 110, etch stop layer 210, dielectric layer 220, ..., etch stop layer 210, dielectric layer 220, etch stop layer 210. When the value of _N1 is less than the value of _N2 by 1, the substrate 110 and the stacked structure 200 can be stacked in the manner of substrate 110, dielectric layer 220, etch stop layer 210, ..., dielectric layer 220, etch stop layer 210, dielectric layer 220. In one example, the value of _N1 can be greater than the value of _N2 by 1, that is, any dielectric layer 220 in the stacked structure 200 can be sandwiched by two layers of etch stop layers 210, so that even if more layers need to be etched, the etching speed can be mitigated by the etch stop layers 210 disposed on both sides of the dielectric layer 220, ensuring that the etching stops accurately at the desired position.

Exemplarily, referring to FIG. 3 , the first isolation layer 310 is disposed between the first metal layer 320 and the inner wall of the first contact hole 300, which may specifically refer to the first isolation layer 310 being disposed between the first metal layer 320 and the entire inner wall of the first contact hole 300. In this way, the entire peripheral area of the first metal layer 320 filled in the first contact hole 300 can be surrounded by the first isolation layer 310, thereby effectively avoiding the phenomenon that the ions of the first metal layer 320 diffuse outward from the inner wall of the first contact hole 300, and better improving the reliability of the contact hole structure. It should be understood that in other examples, the first isolation layer 310 may be disposed around the entire inner wall of the first contact hole 300, and then a step of removing part of the first isolation layer 310 may be added, so that the first isolation layer 310 is only surrounded on part of the inner wall of the first contact hole 300. Among them, part of the inner wall of the contact hole can be set according to actual conditions. For example, in a specific implementation, when other contact holes or device active areas only partially overlap with the layer penetrated by the first contact hole 300, the first isolation layer 310 can be set around the inner wall corresponding to the overlapping layer, and there is no need to set the first isolation layer 310 around the inner wall corresponding to the non-overlapping layer. In this way, it can prevent the metal layer filled in the first contact hole 300 from penetrating through the inner wall corresponding to the overlapping layer to other contact holes or device active areas, and save the material of the first isolation layer 310, which helps to improve the reliability of the contact hole structure on the basis of reducing costs.

Exemplarily, referring to FIG. 3 , the contact portion 100 contacts the first metal layer 320, which may specifically mean that the contact portion 100 contacts both the first metal layer 320 and the first isolation layer 310. In this way, the entire lower surface of the first metal layer 320 shown in FIG. 3 can contact the contact portion 100, thereby helping to expand the flow area of the first metal layer 320 and effectively improve the conductive performance of the contact hole structure. It should be understood that in other examples, the contact portion 100 contacts the first metal layer 320 may also mean that the contact portion 100 contacts the first metal layer 320 but does not contact the first isolation layer 310, for example, the contact portion 100 partially contacts the first metal layer 320, and the embodiments of the present application do not specifically limit this.

For example, referring to FIG. 3 , the first contact hole 300 may be an inclined hole, that is, the hole wall of the first contact hole 300 is inclined along the stacking direction of the stacked structure 200 (i.e., the vertical direction shown in the figure). Generally, inclined holes are easier to prepare because, in the process of etching to form holes, the further down the holes are etched, the fewer the number of etching ions is, and thus the smaller the hole diameter is, the easier it is to form an inclined hole that is wide at the top and narrow at the bottom. However, in other implementations, if the process can be guaranteed, the first contact hole 300 may also be a vertical hole rather than an inclined hole, and the embodiments of the present application do not specifically limit this.

For example, the thickness of the first isolation layer 310 may be less than

Thus, even if a first isolation layer 310 is deposited on the inner wall of the first contact hole 300, since the first isolation layer 310 is a very thin layer, the operation of depositing the first isolation layer 310 has little effect on the aperture of the first contact hole 300, thereby reducing the impact on the process window of the subsequent filling of the first metal layer 320.

In the embodiment of the present application, the material of the substrate 110 may include one or more of single crystal silicon, silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN) or indium nitride (InN).

In the above-mentioned first embodiment, by providing a first isolation layer made of a relatively thin material (for example, less than 100 angstroms thick) between the inner wall of the first contact hole and the first metal layer filled in the first contact hole, the first isolation layer can be used to isolate the first metal layer filled in the first contact hole from the metal layers or device active regions filled in other contact holes, thereby reducing the risk of short circuits between the first contact hole and other contact holes and between the first contact hole and the device active region, and the aperture of the first contact hole after the first isolation layer is surrounded can be as close as possible to the aperture of the first contact hole before the first isolation layer is surrounded, thereby reducing the impact on the subsequent filling process of the first metal layer and the cost impact on the semiconductor device. In addition, the scheme does not need to make the aperture of the first contact hole very small, so it can also improve the process window of the etching process of the first contact hole and the subsequent filling process, which helps to reduce the difficulty of manufacturing semiconductor devices.

In the embodiment of the present application, the contact portion may specifically be a device active region, such as a source, a drain or a gate. In this case, one end of the first metal layer filled in the first contact hole contacts the device active region, and the other end of the first metal layer may be connected to other devices in the chip, so that the semiconductor device may directly connect the device active region to other devices in the chip through the first contact hole structure.

Based on the CMOS device shown in FIG1 , the following further introduces the application of the contact hole design scheme in the first embodiment when the contact portion is the device active region in the CMOS device through the second embodiment. Moreover, for the convenience of description, the contact hole directly contacting the source is referred to as the source contact hole, the contact hole directly contacting the drain is referred to as the drain contact hole, and the contact hole directly contacting the gate is referred to as the gate contact hole.

[Example 2]

FIG5 exemplarily shows a schematic structural diagram of another semiconductor device provided in an embodiment of the present application, as shown in FIG5 :

In one example, as shown in (A) of FIG. 5 , the contact portion 100 may specifically refer to the source 101 . In this case, the at least one etching stop layer 210 may include a first etching stop layer 211 and a second etching stop layer 212 , and the at least one dielectric layer 220 may include a first dielectric layer 221 . Specifically, referring to (A) in FIG. 5 , in this example, the CMOS device may include: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, and a second etch stop layer 212 stacked in sequence; a source 101 disposed on the substrate 110, and the configuration may be any one of those shown in (A) to (D) in FIG. 4 , and the configuration illustrated in (A) in FIG. 5 corresponds to the configuration illustrated in (B) in FIG. 4 ; a source contact hole penetrating the second etch stop layer 212, the first dielectric layer 221, and the first etch stop layer 211 and connected to the source 101; a first isolation layer 310 and a first metal layer 320 disposed in the source contact hole, the first isolation layer 310 being disposed between the inner wall of the source contact hole and the first metal layer 320, and the first metal layer 320 contacting the source 101 through the source contact hole. In this embodiment, by providing an isolation layer between the inner wall of the source contact hole and the first metal layer 320 filled in the source contact hole, the first metal layer 320 filled in the source contact hole can be isolated from the metal layers filled in other contact holes (such as the gate contact hole and the drain contact hole) and other device active areas (such as the gate 103 and the drain 102), thereby effectively avoiding the short circuit between the source 101 and the gate 103 or the drain 102.

In another example, as shown in (B) of Figure 5, the contact portion 100 may specifically refer to the drain 102. In this case, at least one etching stop layer 210 may include a first etching stop layer 211 and a second etching stop layer 212, and at least one dielectric layer 220 may include a first dielectric layer 221. Specifically, referring to (B) in FIG. 5 , in this example, the CMOS device may include: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, and a second etch stop layer 212 stacked in sequence; a drain 102 disposed on the substrate 110, and the configuration may be any one of those shown in (A) to (D) in FIG. 4 , and the configuration illustrated in (A) in FIG. 5 corresponds to the configuration illustrated in (B) in FIG. 4 ; a drain contact hole penetrating the second etch stop layer 212, the first dielectric layer 221, and the first etch stop layer 211 and connected to the drain 102; a first isolation layer 310 and a first metal layer 320 disposed in the drain contact hole, the first isolation layer 310 being disposed between the inner wall of the drain contact hole and the first metal layer 320, and the first metal layer 320 contacting the drain 102 through the drain contact hole. In this embodiment, by providing an isolation layer between the inner wall of the drain contact hole and the first metal layer 320 filled in the source contact hole, the first metal layer 320 filled in the drain contact hole can be isolated from the metal layers filled in other contact holes (such as the gate contact hole and the source contact hole) and other device active areas (such as the gate 103 and the source 101), thereby effectively avoiding the short circuit between the drain 102 and the gate 103 or the source 101.

In another example, as shown in (C) of Figure 5, the contact portion 100 may specifically refer to the gate 103. In this case, at least one etching stop layer 210 may include a second etching stop layer 212 and a third etching stop layer 213, and at least one dielectric layer 220 may include a second dielectric layer 222. Specifically, referring to (C) in FIG. 5 , in this example, the CMOS device may include: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, a second etch stop layer 212, a second dielectric layer 222, and a third etch stop layer 213 stacked in sequence; a gate hole penetrating the first dielectric layer 221 and the first etch stop layer 211, the bottom of the gate hole being buried in the substrate 110, and the gate hole being filled with a gate 103 and a sidewall 104 surrounding the gate 103, the sidewall 104 being arranged around the inner wall and the bottom of the gate 103; a gate contact hole penetrating the third etch stop layer 213, the second dielectric layer 222, and the second etch stop layer 212 and connected to the gate 103; a first isolation layer 310 and a first metal layer 320 arranged in the gate contact hole, the first isolation layer 310 being arranged between the inner wall of the gate contact hole and the first metal layer 320, and the first metal layer 320 contacting the gate 103 through the gate contact hole. In this embodiment, by setting a first isolation layer 310 between the inner wall of the gate contact hole and the first metal layer 320 filled in the gate contact hole, the first metal layer 320 filled in the gate contact hole can be isolated from the metal layers filled in other contact holes (such as the source contact hole and the drain contact hole) and other device active areas (such as the source 101 and the drain 102), thereby effectively avoiding the short circuit between the gate 103 and the source 101 or the drain 102.

In the above examples, the material for realizing the source 101 and/or the drain 102 may include a semiconductor material, and the semiconductor material may refer to a material in which other elements are doped in silicon, such as silicon germanium (SiGe) or silicon phosphorus (SiP). The material for realizing the gate 103 may include a metal material or a semiconductor material, such as tantalum, tungsten or silicon oxynitride (SiON). The material for realizing the sidewall 104 may include a nitride, such as silicon nitride (SiN), silicon carbide nitride (SiCN) or silicon oxynitride (SiON).

The above FIG. 5 (A) to FIG. 5 (C) introduce the related implementation of applying the contact hole setting scheme in the first embodiment alone in one device active region in the source, drain or gate. The embodiment of the present application can also combine the contact hole setting scheme in the first embodiment and apply it in multiple device active regions, and can also perform some deformation on the contact hole setting scheme corresponding to one or more device active regions to obtain a deformed contact hole structure. For example, FIG. 6 exemplarily shows a structural schematic diagram of another semiconductor device provided in the embodiment of the present application, wherein:

In a possible combination design, as shown in (A) of FIG6 , the above-mentioned contact hole setting scheme can be applied to the source and drain. In this case, the CMOS device may include: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, and a second etch stop layer 212 stacked in sequence; a source 101 and a drain 102 arranged on the substrate 110, and the setting method may be, for example, that the source 101 and the drain 102 are buried in the substrate 110 and the upper surface is exposed on a side plane of the substrate 110 relative to the first etch stop layer 211; a source contact hole penetrating the second etch stop layer 212, the first dielectric layer 221, and the first etch stop layer 211 and conducting to the source 101; and a source contact hole penetrating the second etch stop layer 212 , a first dielectric layer 221 and a first etching stop layer 211 and a drain contact hole connected to the drain 102; a first isolation layer 310 and a first metal layer 320 are arranged in the source contact hole and the drain contact hole, the first isolation layer 310 is arranged between the inner wall of the source contact hole and the first metal layer 320 filled in the source contact hole and between the inner wall of the drain contact hole and the first metal layer 320 filled in the drain contact hole, the first metal layer 320 filled in the source contact hole contacts the source 101 through the source contact hole, and the first metal layer 320 filled in the drain contact hole contacts the drain 102 through the drain contact hole.

In another possible combination design, as shown in FIG6 (B), the above contact hole arrangement scheme can be applied to the source, drain and gate. In this case, the CMOS device may include: a substrate 110, a first etching stop layer 211, a first dielectric layer 221, a second etching stop layer 212, a second dielectric layer 222 and a third etching stop layer 213 stacked in sequence; a source 101 and a drain 102 arranged on the substrate 110, and the arrangement method can be exemplarily the source 101 and the drain 102 is buried in the substrate 110 and the upper surface is exposed on a side plane of the substrate 110 relative to the first etch stop layer 211; a gate hole that penetrates the first dielectric layer 221 and the first etch stop layer 211, the bottom of the gate hole is buried in the substrate 110, and the gate hole is provided with a gate 103 and an inner wall and a side wall 104 surrounding the gate 103; a source contact hole that penetrates the second etch stop layer 212, the first dielectric layer 221 and the first etch stop layer 211 and is connected to the source 101; a drain contact hole that penetrates the second etch stop layer 212, the first dielectric layer 221 and the first etch stop layer 211 and is connected to the drain 102; a drain contact hole that penetrates the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and is connected to the drain 102; A gate contact hole connected to the gate 103; a first isolation layer 310 and a first metal layer 320 are arranged in the source contact hole, the drain contact hole and the gate contact hole, the first isolation layer 310 is arranged between the inner wall of the source contact hole and the first metal layer 320 filled in the source contact hole, between the inner wall of the drain contact hole and the first metal layer 320 filled in the drain contact hole, and between the inner wall of the gate contact hole and the first metal layer 320 filled in the gate contact hole, the first metal layer 320 filled in the source contact hole contacts the source 101 through the source contact hole, the first metal layer 320 filled in the drain contact hole contacts the drain 102 through the drain contact hole, and the first metal layer 320 filled in the gate contact hole contacts the gate 103 through the gate contact hole.

In another possible combination design, as shown in (C) of Figure 6, the above-mentioned contact hole setting scheme can be applied to the source, drain and gate, and the source contact hole structure can be deformed so that the source contact hole structure connects the source to the same top plane as the gate. In this case, the CMOS device may include: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, a second etch stop layer 212, a second dielectric layer 222 and a third etch stop layer 213 stacked in sequence; a source 101 and a drain 102 arranged on the substrate 110, and the arrangement method can be exemplarily that the source 101 and the drain 102 are buried in the substrate 110 and the upper surface is exposed on a side plane of the substrate 110 relative to the first etch stop layer 211; a gate hole penetrating the first dielectric layer 221 and the first etch stop layer 211, the bottom of the gate hole is buried in the substrate 110, and a gate 103 and a sidewall 104 surrounding the inner wall and the bottom of the gate 103 are arranged in the gate hole; a source contact hole penetrating the third etch stop layer 213, the second dielectric layer 222, the second etch stop layer 212, the first dielectric layer 221 and the first etch stop layer 211 and connected to the source 101; a gate hole penetrating the second etch stop layer 212 , a drain contact hole that penetrates the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and is connected to the gate 103; a first isolation layer 310 and a first metal layer 320 are arranged in the source contact hole, the drain contact hole and the gate contact hole, the first isolation layer 310 is arranged between the inner wall of the source contact hole and the first metal layer 320 filled in the source contact hole, between the inner wall of the drain contact hole and the first metal layer 320 filled in the drain contact hole, and between the inner wall of the gate contact hole and the first metal layer 320 filled in the gate contact hole, the first metal layer 320 filled in the source contact hole contacts the source 101 through the source contact hole, the first metal layer 320 filled in the drain contact hole contacts the drain 102 through the drain contact hole, and the first metal layer 320 filled in the gate contact hole contacts the gate 103 through the gate contact hole.

In the above-mentioned combined design, by setting the first isolation layer 310 on the inner wall of the source contact hole, the inner wall of the drain contact hole and the inner wall of the gate contact hole, the first metal layer 320 filled in any contact hole of the source contact hole, the drain contact hole and the gate contact hole can be isolated from the other two device active areas and the metal layer filled in the contact holes connected to the other two device active areas, thereby effectively reducing the risk of short circuit between any two device active areas among the source 101, the drain 102 and the gate 103. Moreover, in the above-mentioned CMOS device, the substrate 110, the first etch stop layer 211, the first dielectric layer 221, the second etch stop layer 212 can constitute the first layer structure of the CMOS device, the substrate 110, the first etch stop layer 211, the first dielectric layer 221, the second etch stop layer 212, the second dielectric layer 222 and the third etch stop layer 213 can constitute the 1.5 layer structure of the CMOS device, the CMOS device illustrated in (A) of FIG6 connects the source 101 and the drain 102 to the top plane H1 of the first layer structure through the source contact hole structure and the drain contact hole structure, and the CMOS device illustrated in (B) of FIG6 connects the source 101 and the drain 102 to the top plane H1 of the first layer structure through the source contact hole structure and the drain contact hole structure. The gate 102 is connected to the top plane H1 of the 1st layer structure, and the gate 103 is connected to the top plane H2 of the 1.5th layer structure through the gate contact hole structure. The CMOS device shown in (C) in FIG6 connects the drain 102 to the top plane H1 of the 1st layer structure through the drain contact hole structure, and connects the gate 103 and the source 101 to the top plane H2 of the 1.5th layer structure through the gate contact hole structure and the source contact hole structure, and the plane H1 and the plane H2 are located at different layers in the CMOS device. In this way, by staggering the connection of the gate 103, the source 101 and the drain 102 to different layers of the CMOS device, not only can it be avoided to set too dense routing on the same layer, reducing the difficulty of preparation of the back-end process, but also the routing required to connect the two electrodes located on different layers in the back-end process can be separated as much as possible, further reducing the risk of short circuit between the gate 103, the source 101 and the drain 102.

It should be noted that, in the above-mentioned CMOS device, the wiring located at the topmost layer of the CMOS device can be arranged in a direction perpendicular to the stacking direction shown in the figure, while the wiring located in the inner layer of the CMOS device can be arranged in a direction perpendicular to the drawing surface. For example, assuming that the CMOS device presents a structure as shown in (B) in FIG. 6 , the first metal layer 320 filled in the gate contact hole and the other devices in the chip to be connected to the gate 103 can be connected by wires along the stacking direction perpendicular to the figure on plane H2, and the first metal layer 320 filled in the source contact hole and the other devices in the chip to be connected to the source 101 can be connected by wires along the direction perpendicular to the drawing surface on plane H1, and the first metal layer 320 filled in the drain contact hole and the other devices in the chip to be connected to the drain 102 can be connected by wires along the direction perpendicular to the drawing surface.

It should be understood that in the combination schemes illustrated in FIG. 6 (A) to FIG. 6 (C) above, a first isolation layer 310 is disposed on the inner wall of each contact hole, which is only an optional implementation. In order to simplify the manufacturing process of the CMOS device, in another optional implementation, a first isolation layer 310 may be provided only on the inner wall of some contact holes, while other contact holes may be directly filled with the first metal layer 320. For example, the first isolation layer 310 may be provided on the inner wall of the source contact hole and the drain contact hole and the first metal layer 320 may be filled in the first isolation layer 310, while the gate contact hole may be directly filled with the first metal layer 320, or the first isolation layer 310 may be provided on the inner wall of the gate contact hole and the first metal layer 320 may be filled in the first isolation layer 310, while the source contact hole and the drain contact hole may be directly filled with the first metal layer 320, or the first isolation layer 310 may be provided on the inner wall of the source contact hole and the gate contact hole and the first metal layer 320 may be filled in the first isolation layer 310, while the drain contact hole may be directly filled with the first metal layer 320, etc. There are many possible configuration methods, and the embodiments of the present application will not list them one by one.

In addition, in the combination schemes shown in FIG. 6 (A) to FIG. 6 (C), although the isolation layer provided on the inner wall of each contact hole is called the first isolation layer 310, and the metal layer filled in the isolation layer is called the first metal layer 320, this is only for the convenience of introducing the scheme. In actual operation, the first isolation layer 310 provided on the inner walls of different contact holes can be made of the same material or different materials, the first metal layer 320 filled in different contact holes can be made of the same material or different materials, and the isolation layer surrounding the inner walls of different contact holes or the first metal layer 320 filled can also have different names, and the embodiment of the present application does not specifically limit this.

In the above-mentioned second embodiment, by setting a first isolation layer on the inner wall of the source contact hole, the inner wall of the drain contact hole or the inner wall of the gate contact hole, the first metal layer filled in the contact hole can be isolated from the other two device active areas or the metal layer filled in the contact hole connected to the device active area through the isolation effect of the first isolation layer, thereby effectively reducing the risk of short circuit between the device active area connected to the contact hole and other device active areas. Moreover, through the combined design of the source contact hole structure, the drain contact hole structure and the gate contact hole structure, at least two of the source, drain and gate can be connected to different layers of the semiconductor device, and then the source, drain and gate can be set on different layers to connect the routing of other devices in the chip, and the difficulty of the preparation of the back-end process can be reduced by dispersing the same-layer routing pressure of the semiconductor device.

In the embodiment of the present application, the contact portion 100 may also be a second metal layer filled in the second contact hole, that is, the contact hole design scheme in the above embodiment 1 may also be applied to the scenario where the first contact hole and the second contact hole are connected. Among them, the second contact hole may be a contact hole adjacent to the first contact hole in the stacking direction of the stacking structure, and may be, for example, a gate contact hole connected to the gate, a source contact hole connected to the source, a drain contact hole connected to the drain, or a contact hole connected to the third metal layer filled in the third contact hole. Moreover, the second contact hole may be completely filled with the second metal layer, or a second isolation layer may be first arranged around the inner wall of the second contact hole and then the second metal layer may be filled inside the second isolation layer as shown in the above embodiment 1 or embodiment 2, and the material for implementing the second isolation layer includes a dense material. Moreover, one end of the second metal layer filled in the second contact hole contacts one end of the first metal layer filled in the first contact hole, the other end of the second metal layer filled in the second contact hole is connected to the device active area, and the other end of the first metal layer filled in the first contact hole is connected to other devices in the chip. In this way, the semiconductor device can realize the connection between the device active area and other devices in the chip through at least two contact hole structures, the first contact hole structure and the second contact hole structure.

Based on the CMOS device shown in (B) of FIG6 , the following further describes how to apply the contact hole design scheme proposed in the above-mentioned embodiment 1 in the scenario where two contact holes are connected through embodiment 3. Moreover, for the convenience of description, the contact hole directly contacting the metal layer filled in the source contact hole is referred to as a secondary source contact hole, the contact hole directly contacting the metal layer filled in the drain contact hole is referred to as a secondary drain contact hole, and the contact hole directly contacting the metal layer filled in the gate contact hole is referred to as a secondary gate contact hole.

[Example 3]

In an optional implementation, when the second contact hole is a source contact hole or a drain contact hole, the stacked structure may specifically include K layers of second dielectric layers and K layers of third etching stop layers, where K is a positive integer:

The value of K is 1

When the value of K is 1, the stacked structure includes a second dielectric layer and a third etching stop layer. In this case, FIG. 7 exemplarily shows a structural schematic diagram of another semiconductor device provided in an embodiment of the present application, wherein:

In one example, referring to FIG. 7 (A), when the second contact hole is a source contact hole, the CMOS device includes: a substrate 110, a first etching stop layer 211, a first dielectric layer 221, a second etching stop layer 212, a second dielectric layer 222, and a third etching stop layer 213 stacked in sequence; a source electrode 101 disposed on the substrate 110, and the configuration method can be exemplarily that the source electrode 101 is buried in the substrate 110 and the upper surface shown in the figure is exposed on a side plane of the substrate 110 relative to the first etching stop layer 211; a substrate 101 is formed by passing through the second etching stop layer 212, the first dielectric layer 221, the second etching stop layer 212, the second dielectric layer 222, and the third etching stop layer 213. 221 and the first etching stop layer 211 and are connected to the source contact hole of the source 101, and the second metal layer 420 is filled in the source contact hole; the secondary source contact hole penetrates the third etching stop layer 213 and the second dielectric layer 222 and is connected to the second metal layer 420 filled in the source contact hole; the first isolation layer 310 and the first metal layer 320 are arranged in the secondary source contact hole, the first isolation layer 310 is arranged between the inner wall of the secondary source contact hole and the first metal layer 320, and the first metal layer 320 contacts the second metal layer 420 filled in the source contact hole through the secondary source contact hole. In this example, by setting another secondary source contact hole structure above the illustrated source contact hole structure, the source 101 can be connected from the plane H1 originally connected to it to a higher plane H2, while the drain 102 is still connected to the plane H1, which can further reduce the routing pressure in the plane H1. At the same time, a first isolation layer 310 is formed on the inner wall of the secondary source contact hole, which can isolate the first metal layer 320 filled in the secondary source contact hole from the surrounding metal layer or device active area while connecting the source 101 to the higher plane H2, thereby reducing the risk of short circuit between the source 101 and the surrounding device active area;

In another example, referring to FIG. 7 (B), when the second contact hole is a drain contact hole, the CMOS device includes: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, a second etch stop layer 212, a second dielectric layer 222, and a third etch stop layer 213 stacked in sequence; a drain 102 disposed on the substrate 110, and the arrangement manner is exemplarily that the drain 102 is buried in the substrate 110 and the upper surface of the drain 102 is exposed in the substrate 110 relative to the first etch stop layer 211. On one side plane; a drain contact hole penetrating the second etch stop layer 212, the first dielectric layer 221 and the first etch stop layer 211 and connected to the drain 102, and the drain contact hole is filled with the second metal layer 420; a secondary drain contact hole penetrating the third etch stop layer 213 and the second dielectric layer 222 and connected to the second metal layer 420 filled in the drain contact hole; a first isolation layer 310 and a first metal layer 320 arranged in the secondary drain contact hole, the first isolation layer 310 is arranged between the inner wall of the secondary drain contact hole and the first metal layer 320, and the first metal layer 320 contacts the second metal layer 420 filled in the drain contact hole through the secondary drain contact hole. In this example, by setting another secondary drain contact hole structure above the diagram of the drain contact hole structure, the drain 102 can be connected from the plane H1 originally connected to a higher plane H2, while the source 101 is still connected to the plane H1, which can further reduce the routing pressure in the plane H1. At the same time, a first isolation layer 310 is formed on the inner wall of the secondary drain contact hole, which can isolate the first metal layer 320 filled in the secondary drain contact hole from the surrounding metal layer or device active area while connecting the drain 102 to a higher plane H2, thereby reducing the risk of short circuit between the drain 102 and the surrounding device active area.

The value of K is 2

When the value of K is 2, the stacked structure includes two second dielectric layers and two third etch stop layers. In this case, FIG. 8 exemplarily shows a structural schematic diagram of another semiconductor device provided in an embodiment of the present application, wherein:

In one example, referring to FIG. 8 (A), when the second contact hole is a source contact hole, the CMOS device includes: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, a second etch stop layer 212, a first second dielectric layer 222, a first third etch stop layer 213, a second second dielectric layer 223, and a second third etch stop layer 214 stacked in sequence; a source electrode 101 disposed on the substrate 110, and the configuration method can be exemplarily that the source electrode 101 is buried in the substrate 110 and the upper surface shown in the figure is exposed on a side plane of the substrate 110 relative to the first etch stop layer 211; and a substrate 101 is formed by passing through the second etch stop layer 212, the first dielectric layer 222, the first third etch stop layer 213, the second second dielectric layer 223, and the second third etch stop layer 214. 221 and the first etch stop layer 211 and are connected to the source contact hole of the source 101, and the second metal layer 420 is filled in the source contact hole; a secondary source contact hole that penetrates the second third etch stop layer 214, the second second dielectric layer 223, the first third etch stop layer 213 and the first second dielectric layer 222 and is connected to the second metal layer 420 filled in the source contact hole; a first isolation layer 310 and a first metal layer 320 are arranged in the secondary source contact hole, the first isolation layer 310 is arranged between the inner wall of the secondary source contact hole and the first metal layer 320, and the first metal layer 320 contacts the second metal layer 420 filled in the source contact hole through the secondary source contact hole. In this example, the substrate 110, the first etch stop layer 211, the first dielectric layer 221, the second etch stop layer 212, the first second dielectric layer 222, the first third etch stop layer 213, the second second dielectric layer 223 and the second third etch stop layer 214 constitute the second layer structure of the CMOS device. By providing a secondary source contact hole structure that penetrates two dielectric layers and two etch stop layers above the source contact hole structure, the source 101 can be connected from the top plane H1 of the first layer structure originally connected to the top plane H3 of the second layer structure, and the plane H3 is higher than the top plane H2 of the 1.5 layer structure to which the gate 103 is connected, and the drain 102 is still connected to the top plane H1 of the first layer structure. In this way, by connecting the gate 103, the source 101 and the drain 102 to three different layers, the routing on each layer in the CMOS device can be arranged as evenly as possible. At the same time, a first isolation layer 310 is formed on the inner wall of the secondary source contact hole, which can isolate the first metal layer 320 filled in the secondary source contact hole from the surrounding metal layer or device active area while connecting the source 101 to a higher plane H3, thereby reducing the risk of short circuit between the source 101 and the surrounding device active area.

In another example, referring to FIG. 8 (B), when the second contact hole is a drain contact hole, the CMOS device includes: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, a second etch stop layer 212, a first second dielectric layer 222, a first third etch stop layer 213, a second second dielectric layer 223, and a second third etch stop layer 214 stacked in sequence; a drain 102 disposed on the substrate 110, the arrangement of which can be exemplarily that the drain 102 is buried in the substrate 110 and the upper surface shown in the figure is exposed on a side plane of the substrate 110 relative to the first etch stop layer 211; and a drain 102 disposed on the substrate 110. A drain contact hole that is connected to the drain 102 through the second etch stop layer 212, the first dielectric layer 221 and the first etch stop layer 211, and the drain contact hole is filled with the second metal layer 420; a secondary drain contact hole that penetrates the second third etch stop layer 214, the second second dielectric layer 223, the first third etch stop layer 213 and the first second dielectric layer 222 and is connected to the second metal layer 420 filled in the drain contact hole; a first isolation layer 310 and a first metal layer 320 are arranged in the secondary drain contact hole, the first isolation layer 310 is arranged between the inner wall of the secondary drain contact hole and the first metal layer 320, and the first metal layer 320 contacts the second metal layer 420 filled in the drain contact hole through the secondary drain contact hole. In this example, by setting a secondary drain contact hole structure penetrating two dielectric layers and two etching stop layers above the illustrated drain contact hole structure, the drain 102 can be connected from the top plane H1 of the first layer structure originally connected to the top plane H3 of the second layer structure, and the plane H3 is higher than the top plane H2 of the 1.5 layer structure to which the gate 103 is connected, and the source 101 is still connected to the top plane H1 of the first layer structure. In this way, by connecting the gate 103, the source 101 and the drain 102 to three different layers, the routing on each layer in the CMOS device can be laid out as evenly as possible. At the same time, a first isolation layer 310 is formed on the inner wall of the secondary drain contact hole, and while connecting the drain 102 to a higher plane H3, the first metal layer 320 filled in the secondary drain contact hole can be isolated from the surrounding metal layer or the device active area, thereby reducing the risk of short circuit between the drain 102 and the surrounding device active area.

The value of K is an integer greater than or equal to 3

When K is a positive integer greater than or equal to 3, the stacked structure specifically includes at least three layers of second dielectric layers and at least three layers of third etching stop layers stacked alternately. In this case, a secondary source contact hole structure penetrating at least three layers of second dielectric layers and at least three layers of third etching stop layers may be provided above the source contact hole structure in the CMOS device, or a secondary drain contact hole structure penetrating at least three layers of second dielectric layers and at least three layers of third etching stop layers may be provided above the drain contact hole structure, and the inner wall of the secondary source contact hole or the secondary drain contact hole is surrounded by a first isolation layer 310, and the first isolation layer 310 is filled with a first metal layer 320. In this way, in addition to reducing the risk of short circuit between the source 101 or the drain 102 and other device active areas, the design can also connect the source 101 or the drain 102 to a higher plane higher than the H3 plane shown in FIG. 8 (A) or FIG. 8 (B) through the secondary source contact hole structure or the secondary drain contact hole structure, so as to further evenly disperse the routing on each plane when the density of the CMOS device is further increased. It should be understood that the specific implementation method of this situation can refer to the above content, and the embodiments of the present application will not repeat them one by one.

It should be noted that when the second contact hole is a source contact hole or a drain contact hole, the source contact hole or the drain contact hole may include a second isolation layer 410 arranged on the inner wall and a second metal layer 420 filled in the second isolation layer 410 as shown in (A) or (B) in FIG. 8 , or may include the second metal layer 420 filled in the source contact hole or the drain contact hole but not include the second isolation layer 410. The embodiments of the present application do not specifically limit this.

In another optional implementation, when the second contact hole is a gate contact hole, the stacked structure may specifically include a P-layer third dielectric layer and a P-layer fourth etching stop layer, where P is a positive integer. illustratively, FIG9 shows a schematic structural diagram of another semiconductor device provided in an embodiment of the present application, wherein:

In one example, referring to (A) in FIG. 9 , when the value of P is 1, the stacked structure includes a third dielectric layer and a fourth etch stop layer. In this case, the CMOS device includes: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, a second etch stop layer 212, a second dielectric layer 222, a third etch stop layer 213, a third dielectric layer 223 and a fourth etch stop layer 214 stacked in sequence; a gate hole penetrating the first dielectric layer 221 and the first etch stop layer 211, the bottom of the gate hole being buried in the substrate 110, and a gate 103 and an inner wall and a bottom sidewall 104 surrounding the gate 103 being arranged in the gate hole; a gate contact hole penetrating the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and connected to the gate 103, the gate contact hole being filled with the second metal layer 420; a gate hole penetrating the fourth etch stop layer 214, the second dielectric layer 222 and the second etch stop layer 214 being ... hole being filled with the second metal layer 420; a gate hole penetrating the first dielectric layer 221 and the first etch stop layer 211, the bottom of the gate hole being buried in the substrate 110, and the gate hole being provided with the gate 103 and the inner wall and the bottom sidewall 104 surrounding the gate 103; a gate contact hole penetrating the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer The gate 103 is connected to the second metal layer 420 filled in the gate contact hole by connecting the second dielectric layer 214 and the third dielectric layer 223; the first isolation layer 310 and the first metal layer 320 are arranged in the secondary gate contact hole, the first isolation layer 310 is arranged between the inner wall of the secondary gate contact hole and the first metal layer 320, and the first metal layer 320 contacts the second metal layer 420 filled in the gate contact hole through the secondary gate contact hole. In this example, by setting a secondary gate contact hole structure that penetrates a dielectric layer and an etching stop layer above the illustrated diagram of the gate contact hole structure, the gate 103 can be connected from the top plane H2 of the 1.5-layer structure originally connected to the top plane H3 of the 2-layer structure, so that when the density of the CMOS device is further increased, it can avoid setting too dense routing on the plane H2, thereby reducing the difficulty of preparation of the back-end process. At the same time, a first isolation layer 310 is formed on the inner wall of the secondary gate contact hole, which can isolate the first metal layer 320 filled in the secondary gate contact hole from the surrounding metal layer or device active area while connecting the gate 103 to a higher plane H3, thereby reducing the risk of short circuit between the gate 103 and the surrounding device active area.

In one example, as shown in (B) of FIG. 9 , when the value of P is 2, the stacked structure includes two third dielectric layers and two fourth etch stop layers. In this case, the CMOS device includes: a substrate 110, a first etch stop layer 211, a first dielectric layer 221, a second etch stop layer 212, a second dielectric layer 222, a third etch stop layer 213, a first third dielectric layer 223, a first fourth etch stop layer 214, a second third dielectric layer 224, and a second fourth etch stop layer 215 stacked in sequence; a gate hole penetrating the first dielectric layer 221 and the first etch stop layer 211, the bottom of the gate hole being buried in the substrate 110, and the gate hole being provided with a gate 103 and a side wall and a bottom surrounding the gate 103. The invention relates to a gate wall 104; a gate contact hole penetrating the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and connected to the gate 103, wherein the second metal layer 420 is filled in the gate contact hole; a secondary gate contact hole penetrating the second fourth etch stop layer 215, the second third dielectric layer 224, the first fourth etch stop layer 214 and the first third dielectric layer 223 and connected to the second metal layer 420 filled in the gate contact hole; a first isolation layer 310 and a first metal layer 320 are arranged in the secondary gate contact hole, wherein the first isolation layer 310 is arranged between the inner wall of the secondary gate contact hole and the first metal layer 320, and the first metal layer 320 contacts the second metal layer 420 filled in the gate contact hole through the secondary gate contact hole. In this example, the substrate 110, the first etch stop layer 211, the first dielectric layer 221, the second etch stop layer 212, the second dielectric layer 222, the third etch stop layer 213, the first third dielectric layer 223, the first fourth etch stop layer 214, the second third dielectric layer 224 and the second fourth etch stop layer 215 constitute the 2.5 layer structure of the CMOS device. By setting a secondary gate contact hole structure that penetrates two dielectric layers and two etch stop layers above the illustrated gate contact hole structure, the gate 103 can be connected from the top plane H2 of the 1.5 layer structure originally connected to the top plane H4 of the 2.5 layer structure, and the plane H4 is higher than the plane H3. In this way, when the density of the CMOS device is further increased, it is possible to avoid setting too dense routing on the plane H2 and the plane H3, thereby reducing the difficulty of preparation of the subsequent process. At the same time, a first isolation layer 310 is formed on the inner wall of the secondary gate contact hole, which can isolate the first metal layer 320 filled in the secondary gate contact hole from the surrounding metal layer or device active area while connecting the gate 103 to a higher plane H4, thereby reducing the risk of short circuit between the gate 103 and the surrounding device active area.

In another example, when P is a positive integer greater than or equal to 3, the stacked structure includes at least three layers of the third dielectric layer and at least three layers of the fourth etching stop layer that are alternately stacked. In this case, a sub-gate contact hole structure that penetrates at least three layers of the third dielectric layer and at least three layers of the fourth etching stop layer can also be provided above the illustrated gate contact hole structure in the CMOS device, and the inner wall of the sub-gate contact hole is surrounded by a first isolation layer 310, and the first isolation layer 310 is filled with a first metal layer 320. In this way, in addition to reducing the risk of short circuit between the gate 103 and other device active areas, the design can also connect the gate 103 to a higher plane higher than the H4 plane shown in FIG. 9 (B) through the sub-gate contact hole structure, so as to further evenly disperse the routing on each plane when the density of the CMOS device is further increased. It should be understood that the specific implementation of this situation can refer to the above content, and the embodiments of the present application will not be repeated one by one.

It should be noted that when the second contact hole is a gate contact hole, the gate contact hole may include a second isolation layer 410 arranged on the inner wall and a second metal layer 420 filled in the second isolation layer 410 as shown in FIG. 9 (A) or FIG. 9 (B), or may include a second metal layer 420 filled in the gate contact hole but not include the second isolation layer 410. The embodiment of the present application does not specifically limit this.

Furthermore, the above-mentioned FIGS. 7 to 9 introduce the related implementation of applying the contact hole arrangement scheme in the first embodiment alone to a single secondary contact hole. The embodiment of the present application can also combine the contact hole arrangement scheme in the first embodiment and apply it to multiple secondary contact holes, and can also perform some deformation on one or more of the secondary contact holes to obtain a deformed secondary contact hole structure. For example, FIG. 10 exemplarily shows a structural schematic diagram of another semiconductor device provided in the embodiment of the present application, wherein:

In a possible combination design, the secondary source contact hole structure can be arranged in the manner shown in FIG. 8 (A), and the secondary drain contact hole structure can be arranged in the manner shown in FIG. 8 (B), to obtain a CMOS device as shown in FIG. 10 (A). In this CMOS device, the source 101 is connected to the top plane H3 of the second layer structure through the source contact hole structure and the secondary source contact hole structure, the drain 102 is connected to the top plane H3 of the second layer structure through the drain contact hole structure and the secondary drain contact hole structure, and the gate 103 is connected to the top plane H2 of the 1.5 layer structure through the gate contact hole structure. In this way, by connecting the source 101 and the drain 102 to a plane different from the gate 103, the routing on each plane can be dispersedly deployed;

In another possible combination design, the secondary drain contact hole structure can be arranged in the manner shown in FIG. 7 (B), and the secondary gate contact hole structure can be arranged in the manner shown in FIG. 9 (A), to obtain a CMOS device as shown in FIG. 10 (B). In this CMOS device, the source 101 is connected to the top plane H1 of the 1st layer structure through the source contact hole structure, the drain 102 is connected to the top plane H2 of the 1.5th layer structure through the drain contact hole structure and the secondary drain contact hole structure, and the gate 103 is connected to the top plane H3 of the 2nd layer structure through the gate contact hole structure and the secondary gate contact hole structure. In this way, by connecting the source 101, the gate 103 and the drain 102 to three different planes, the routing on each plane can be balanced;

In another possible combination design, the secondary source contact hole structure can be arranged in the manner shown in FIG. 7 (A), and the secondary drain contact hole structure can be arranged in the manner shown in FIG. 8 (B), to obtain a CMOS device as shown in FIG. 10 (C). In this CMOS device, the source 101 is connected to the top plane H2 of the 1.5-layer structure through the source contact hole structure and the secondary source contact hole structure, the drain 102 is connected to the top plane H3 of the 2-layer structure through the drain contact hole structure and the secondary drain contact hole structure, and the gate 103 is connected to the top plane H2 of the 1.5-layer structure through the gate contact hole structure. In this way, by connecting the source 101 and the gate 103 to a plane different from the drain 102, the routing on each plane can be dispersedly deployed.

It should be understood that there are many possible variations, which are not listed one by one in the embodiments of the present application.

It should be noted that, in the combination schemes illustrated in FIG. 10 (A) to FIG. 10 (C) above, an isolation layer is disposed around the inner wall of each contact hole, which is only an optional implementation method. In order to simplify the manufacturing process of the CMOS device, in another optional implementation, an isolation layer may be arranged around the inner wall of only some of the contact holes, while other contact holes may be directly filled with metal layers. For example, an isolation layer may be arranged around the inner wall of one or more of the source contact hole, the drain contact hole and the gate contact hole, and the metal layer may be filled in the isolation layer, while the sub-source contact hole, the sub-drain contact hole and the sub-gate contact hole may be directly filled with metal layers, or an isolation layer may be arranged around the inner wall of one or more of the sub-source contact hole, the sub-drain contact hole and the sub-gate contact hole, and the metal layer may be filled in the isolation layer, while the source contact hole, the drain contact hole and the gate contact hole may be directly filled with metal layers, or an isolation layer may be arranged around the inner wall of one or more of the contact holes of the source contact hole and the sub-source contact hole, the drain contact hole and the sub-drain contact hole, or the gate contact hole and the sub-gate contact hole, and the metal layer may be filled in the isolation layer, while other contact holes of the combination may be directly filled with metal layers, etc. There are many possible configuration methods, which are not listed one by one in the embodiments of the present application.

In addition, in the combination schemes shown in FIG. 10 (A) to FIG. 10 (C), although the isolation layer disposed around the inner wall of each contact hole is referred to as the first isolation layer or the second isolation layer, and the metal layer filled in the first isolation layer or the second is referred to as the first metal layer or the second metal layer, this is only for the convenience of introducing the scheme. In actual operation, the isolation layers disposed around the inner walls of different contact holes may be made of the same material or different materials, the metal layers filled in different contact holes may be made of the same material or different materials, and the isolation layers or metal layers filled in the inner walls of different contact holes may also have different names, and the embodiments of the present application do not specifically limit this.

In the above-mentioned third embodiment, by setting up another contact hole structure on the contact hole structure, the metal layer filled in the lower contact hole structure can be connected to a higher layer through the set contact hole structure, and then when the number of routing lines on the layer corresponding to the lower contact hole structure is large, part of the routing lines on the layer corresponding to the lower contact hole structure can be dispersed to other layers, so as to evenly deploy the number of routing lines in each layer of the semiconductor device and reduce the routing pressure of each layer. Moreover, by forming an isolation layer surrounding the metal layer in the set contact hole structure, it is also possible to connect the metal layer in the lower contact hole structure to a higher layer while ensuring that the metal layer filled in the set contact hole does not short-circuit with the surrounding metal layer or the device active area as much as possible, thereby effectively ensuring the preparation yield and reliability of the CMOS device.

In addition, each implementation method in the above-mentioned embodiment 1 is also applicable to the above-mentioned embodiment 2 and embodiment 3, and this application will not repeat them one by one.

Based on the semiconductor devices shown in the first to third embodiments, the present application also provides a method for preparing a semiconductor device. FIG11 exemplarily shows a schematic diagram of a preparation process of a semiconductor device provided in an embodiment of the present application. As shown in FIG11 , the preparation process includes:

Step 1: forming a contact portion 100 on a substrate 110 to obtain a structure as shown in FIG. 11 (A). The contact portion 100 on the substrate 110 may be in the form shown in FIG. 11 (A), or in other forms, such as the form shown in FIG. 4 (A), FIG. 4 (C), or FIG. 4 (D), without limitation.

Step 2: alternately stack at least one etching stop layer 210 and at least one dielectric layer 220 on one side of the contact portion 100 on the substrate 110 to obtain a stacking structure 200 as shown in FIG. 11 (B).

Step three: etching to form a first contact hole 300 penetrating the stacked structure 200 and connected to the contact portion 100, to obtain a structure as shown in (C4) in FIG. 11 .

Step four, depositing a first isolation layer 310 on the top of the stacked structure 200, the bottom of the first contact hole 300 and the inner wall of the first contact hole 300, wherein the material for realizing the first isolation layer 310 includes a dense material, and obtaining a structure as shown in FIG. 11 (D).

Exemplarily, the ALD technology can be used to deposit and form the first isolation layer 310 so that the first isolation layer 310 fits tightly against the inner wall of the first contact hole 300, reducing the impact on the subsequent filling of the metal layer. At the same time, the aperture of the first contact hole 300 after deposition is as close as possible to the aperture of the first contact hole 300 before deposition, thereby increasing the process window for subsequently filling the metal layer in the first contact hole 300.

Step five, etching the first isolation layer 310 at the top of the stacked structure 200 and the first isolation layer 310 at the bottom of the first contact hole 300, leaving only the first isolation layer 310 on the inner wall of the first contact hole 300, to obtain the structure shown in FIG. 11 (E).

Step 6: Fill the first metal layer 320 in the first isolation layer 310 to obtain a structure as shown in (F) of FIG. 11 . The filling method may be electrochemical plating (ECP), also known as electroplating.

Step seven, remove the first metal layer 320 on the surface of the CMOS device through chemical mechanical polishing (CMP) technology, and polish the surface until it is flat and scratch-free, to obtain the structure shown in (G) in Figure 11.

In an optional implementation manner, after obtaining the structure shown in FIG. 11 (B) according to the above step 2, etching may be performed according to the following steps 8 to 11 to obtain the structure shown in FIG. 11 (C4):

Step eight, stacking an organic material layer 400 on the side of the stacked structure 200 opposite to the contact portion 100, to obtain a structure as shown in (C1) in FIG. 11. The organic material layer 400 may include one or more layers of a spin-on coating 410 (spin-on coating, SOC), a bottom anti-reflective coating 420 (bottom anti-reflective coating, Barc) and a photoresist coating 430 (photo-resist coating, PRC), and the number of layers of the organic material layer 400 may be positively correlated with the aperture of the contact hole to be etched. For example, in one example, the organic material layer 400 may specifically include a spin-on coating 410, a bottom anti-reflective coating 420 and a photoresist layer 430, and the spin-on coating 410, the bottom anti-reflective coating 420 and the photoresist layer 430 are sequentially stacked on the side of the stacked structure 200 opposite to the contact portion 100. Among them, the thickness of the photoresist layer 430 is not much different from the thickness of the bottom anti-reflection layer 420, and the thickness of the spin-coated layer 410 is much greater than the thickness of the photoresist layer 430 or the thickness of the bottom anti-reflection layer 420, for example, it can be at least 4 times the thickness of the photoresist layer 430 or the thickness of the bottom anti-reflection layer 420.

Step nine, photolithography a pattern corresponding to the first contact hole 300 on the organic material layer 400. Specifically, a concave pattern may be formed at a position corresponding to the contact hole on the photoresist layer 430, and the concave pattern penetrates the photoresist layer 430 to obtain a structure as shown in (C2) in FIG. 11. In some examples, the bottom of the concave pattern may also penetrate the photoresist layer 430 and stop inside the bottom anti-reflection layer 420.

Step ten, etching the organic material layer 400 and the stacked structure 200. Since there is already a recessed pattern on the photoresist layer 430, the etching ions further etch along the recessed pattern, so that the etching progress at the recessed pattern is faster than the etching progress at other positions, so that a first contact hole 300 penetrating the organic material layer 400 and the stacked structure 200 and connected to the contact portion 100 can be formed. In addition, under normal circumstances, after the etching is completed, the photoresist layer 430 and the bottom anti-reflection layer 420 will also be completely etched, so that only a part of the spin-coated layer 410 is retained in the organic material layer 400. Therefore, the semiconductor device after the etching is completed usually presents a structure as shown in (C3) in Figure 11. In addition, the first contact hole 300 formed by etching can be an inclined hole as shown in (C3) in Figure 11, or a vertical hole, which is not specifically limited.

Step 11, removing the organic material layer 400, specifically, removing the remaining spin-coated layer 410 in the organic material layer 400 to obtain a structure as shown in (C4) in Figure 11. The removal method may be burning or other methods capable of removing organic materials.

It should be noted that the above step nine can be implemented by placing the semiconductor device stacked with the organic material layer 400 into a photolithography machine for photolithography, and the above steps ten and eleven can be implemented by placing the semiconductor device after photolithography in the photolithography machine into an etching machine for etching. Moreover, the operation of removing the organic material layer 400 in the above step eleven can be completed simultaneously with the operation of etching to form the contact hole in the above step ten, or can be performed separately after the contact hole is etched in the above step ten, and there is no specific limitation.

In the above preparation process, before filling the first metal layer 320 in the first contact hole 300, a first isolation layer 310 is deposited on the inner wall of the first contact hole 300. The first isolation layer 310 can isolate the first metal layer 320 filled in the first contact hole 300 from the surrounding metal layer or the device active area, thereby reducing the risk of short circuit between the device active area connected to the first contact hole 300 and other device active areas. It can be seen that the preparation process only needs to add a step of depositing the first isolation layer 310 and etching the first isolation layer 310 on the top of the stack structure 200 and the bottom of the first contact hole 300 after etching the first contact hole 300, which can effectively improve the short circuit risk between the first contact hole 300 and other contact holes and between the first contact hole 300 and the device active area, improve the reliability and preparation yield of the semiconductor device, and there is no need to change the preparation rules and pattern density of the first contact hole 300, nor to make the aperture of the first contact hole 300 very small. Therefore, while maintaining low cost, sufficient process windows are left for the etching process of the first contact hole 300 and the subsequent filling process, effectively reducing the difficulty of preparing semiconductor devices.

It should be noted that the above step eleven is an optional step. In other embodiments, the first metal layer 320 may be deposited only in the first contact hole 300 without depositing the first metal layer 320 on the surface of the CMOS device, or the first metal layer 320 deposited on the surface of the CMOS device may be retained, or other technical methods may be used to remove the first metal layer 320 deposited on the surface of the CMOS device, etc., without specific limitation.

In addition, the related implementation methods in the above-mentioned embodiments 1 to 3 are also applicable to the above-mentioned preparation method, and the embodiments of the present application will not repeat them one by one.

Further, for ease of understanding, the following exemplarily takes the preparation of a contact hole structure on a CMOS device as shown in FIG1 as an example to further introduce the specific application of the preparation method in the embodiment of the present application. For ease of introduction, it is assumed that the organic material layer 400 includes a spin coating layer 410, a bottom anti-reflection layer 420, and a photoresist layer 430, the first metal layer 320 and the second metal layer 420 are collectively referred to as a metal layer 20, the first isolation layer 310 and the second isolation layer 410 are collectively referred to as an isolation layer 10, and the implementation material of the isolation layer 10 includes a dense material.

In addition, it is assumed in the following that the CMOS device shown in FIG. 1 has been prepared in advance, and the preparation process may specifically include: first forming a substrate 110, then forming a source 101 and a drain 102 on the substrate 110, then depositing a first etching stop layer 211 and a first dielectric layer 221 on one side of the source 101 and the drain 102 on the substrate 110 in sequence, and then etching to form a gate hole penetrating the first dielectric layer 221 and the first etching stop layer 211, the bottom of the gate hole is buried in the substrate 110, and then a layer of sidewall 104 is surrounded on the inner wall and the bottom of the gate hole, and the gate 103 is filled in the sidewall 104, and finally a second etching stop layer 212 is deposited on the side of the first dielectric layer 221 opposite to the first etching stop layer 211, so as to prepare the CMOS device shown in FIG. The specific implementation of the preparation process can be referred to the prior art, and the embodiments of the present application will not be described in detail.

Application 1: Fabricating contact hole structures on the first layer of CMOS devices

Exemplarily, when the CMOS device shown in (A) of FIG. 6 is prepared, FIG. 12 exemplarily shows a schematic diagram of a preparation process of another semiconductor device provided in an embodiment of the present application. As shown in FIG. 12 , the process includes:

Step 1: On the side of the second etch stop layer 212 opposite to the first dielectric layer 221 , a spin-on coating layer 410 , a bottom anti-reflection layer 420 and a photoresist layer 430 are sequentially stacked to obtain a structure as shown in FIG. 12 (A).

Step 2: Photolithography patterns are formed at positions corresponding to the source contact hole 301 and the drain contact hole 302 on the photoresist layer 430 to obtain a structure as shown in FIG. 12 (B).

Step three, by etching the photoresist layer 430, the bottom anti-reflection layer 420, the spin-coated layer 410, the second etch-stop layer 212, the first dielectric layer 221 and the first etch-stop layer 211, a source contact hole 301 penetrating the spin-coated layer 410, the second etch-stop layer 212, the first dielectric layer 221 and the first etch-stop layer 211 and connected to the source 101, and a drain contact hole 302 penetrating the spin-coated layer 410, the second etch-stop layer 212, the first dielectric layer 221 and the first etch-stop layer 211 and connected to the drain 102 are obtained, and a structure as shown in (C) in FIG. 12 is obtained.

Step 4: remove the spin-coated layer 410 to obtain the structure shown in FIG. 12 (D).

Step five, forming an isolation layer 10 on the upper surface of the second etching stop layer 212, the inner wall and bottom of the source contact hole 301, and the inner wall and bottom of the drain contact hole 302, respectively, to obtain the structure shown in FIG. 12 (E).

Step six, etching away the isolation layer 10 on the upper surface of the second etch stop layer 212, the isolation layer 10 on the bottom of the source contact hole 301, and the isolation layer 10 on the bottom of the drain contact hole 302, leaving only the isolation layer 10 on the inner wall of the source contact hole 301 and the isolation layer 10 on the inner wall of the drain contact hole 302, to obtain the structure as shown in (F) in Figure 12.

Step seven: fill the isolation layer 10 with a metal layer 20 to obtain a structure as shown in FIG. 12 (G).

Step eight, remove the metal layer 20 on the surface of the CMOS device by CMP technology, and polish the surface until it is flat and scratch-free, to obtain a structure as shown in (H) in FIG. 12 .

In the above application 1, the substrate 110, the first etching stop layer 211, the first dielectric layer 221 and the second etching stop layer 212 constitute the first layer structure of the CMOS device, and the source contact hole structure and the drain contact hole structure connect the source 101 and the drain 102 to the top plane of the first layer structure, and then the wiring can be set on the top plane to connect the source 101 and the drain 102 to other devices in the chip that need to be connected. In addition, by surrounding a layer of isolation layer 10 on the inner wall of the source contact hole 301 and the drain contact hole 302, it is possible to ensure that the metal layer 20 filled in the source contact hole 301 and the drain contact hole 302 used for connection does not short-circuit with the surrounding metal layer or the device active area while dispersing the wiring pressure of each layer of the CMOS device, and ensuring that the reliability and manufacturing yield of the CMOS device are not reduced.

Application 2: Fabrication of contact hole structure on the 1.5th layer structure of CMOS devices

Exemplarily, when preparing the CMOS device shown in (B) of FIG. 6 above, FIG. 13 exemplarily shows a schematic diagram of a preparation process of another semiconductor device provided in an embodiment of the present application. As shown in FIG. 13, the process may further include the following steps after step eight in the above application one:

Step nine: stack the second dielectric layer 222 and the third dielectric layer 213 in sequence on the side of the second etch stop layer 212 opposite to the first dielectric layer 221 to obtain the structure shown in FIG. 13 (A).

Step ten: stacking a spin-on coating layer 410 , a bottom anti-reflection layer 420 and a photoresist layer 430 in sequence on a side of the third etch stop layer 213 opposite to the second dielectric layer 222 to obtain a structure as shown in FIG. 13 (B).

Step eleven, photolithography is performed to form a pattern at a position corresponding to the gate contact hole 303 on the photoresist layer 430 to obtain a structure as shown in FIG. 13 (C).

Step twelve, by etching the photoresist layer 430, the bottom anti-reflection layer 420, the spin-coated layer 410, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212, a gate contact hole 303 is obtained that penetrates the spin-coated layer 410, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and is connected to the gate 103, and a structure as shown in (D) in Figure 13 is obtained.

Step 13: remove the spin-coated layer 410 to obtain the structure shown in FIG. 13 (E).

Step fourteen: forming an isolation layer 10 on the upper surface of the third etching stop layer 213, the inner wall of the gate contact hole 303 and the bottom of the gate contact hole 303 to obtain a structure as shown in FIG. 13 (F).

In step fifteen, the isolation layer 10 on the upper surface of the third etch stop layer 213 and the isolation layer 10 on the bottom of the gate contact hole 303 are etched away by etching, leaving only the isolation layer 10 on the inner wall of the gate contact hole 303, to obtain the structure shown in (G) in FIG. 13 .

Step sixteen: fill the metal layer 20 in the isolation layer 10 to obtain the structure as shown in (H) of FIG. 13 .

Step seventeen: remove the metal layer 20 on the surface of the CMOS device by CMP technology, and polish the surface until it is flat and scratch-free, to obtain a structure as shown in (I) in FIG. 13 .

In the above application 2, the substrate 110, the first etching stop layer 211, the first dielectric layer 221, the second etching stop layer 212, the second dielectric layer 222 and the third etching stop layer 213 constitute the 1.5 layer structure of the CMOS device, and the gate contact hole structure connects the gate 103 to the top plane of the 1.5 layer structure, and then the wiring connection can be set on the top plane to connect the gate 103 to other devices in the chip. In this way, by connecting the gate 103 and the source 101 and the drain 102 to different layers, the wiring pressure of the same layer in the CMOS device can be dispersed. In addition, by surrounding a layer of isolation layer 10 on the inner wall of the gate contact hole 303, it is also possible to ensure that the metal layer 20 filled in the gate contact hole 303 used for connection does not short-circuit with the surrounding metal layer or the device active area while connecting the gate 103 to the top plane of the 1.5 layer structure, so as to ensure that the reliability and manufacturing yield of the CMOS device are not reduced while dispersing the wiring pressure of each layer of the CMOS device.

Application 3: Fabricating contact hole structures on the second layer structure of CMOS devices

Exemplarily, when the CMOS device shown in (A) of FIG. 10 is prepared, FIG. 14 exemplarily shows a schematic diagram of a preparation process of another semiconductor device provided in an embodiment of the present application. As shown in FIG. 14 , the process may further include the following steps after step seventeen in the above application two:

In step eighteen, a third dielectric layer 223 (i.e., a second dielectric layer) and a fourth dielectric layer 214 (i.e., a second third dielectric layer) are sequentially stacked on the side of the third etch stop layer 213 (i.e., the first third etch stop layer) opposite to the second dielectric layer 222 (i.e., the first dielectric layer) to obtain a structure as shown in (A) of FIG. 14 .

In step nineteen, a spin-coated layer 410 , a bottom anti-reflection layer 420 and a photoresist layer 430 are sequentially stacked on a side of the fourth etch stop layer 214 opposite to the third dielectric layer 223 to obtain a structure as shown in FIG. 14 (B).

Step 20: photolithography patterns are formed at positions corresponding to the secondary source contact hole 304 and the secondary drain contact hole 305 on the photoresist layer 430 to obtain a structure as shown in FIG. 14 (C).

Step 21, by etching the photoresist layer 430, the bottom anti-reflection layer 420, the spin-coated layer 410, the fourth etch stop layer 214, the third dielectric layer 223, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212, a secondary source contact hole 304 is obtained that penetrates the spin-coated layer 410, the fourth etch stop layer 214, the third dielectric layer 223, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and is connected to the metal layer filled in the source contact hole 301, and a secondary drain contact hole 305 is obtained that penetrates the spin-coated layer 410, the fourth etch stop layer 214, the third dielectric layer 223, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and is connected to the metal layer filled in the drain contact hole 302, so as to obtain the structure as shown in (D) in Figure 14.

Step 22: remove the spin-coated layer 410 to obtain the structure shown in FIG. 14 (E).

Step 23: forming an isolation layer 10 on the upper surface of the fourth etching stop layer 214, the inner wall and bottom of the secondary source contact hole 304, and the inner wall and bottom of the secondary drain contact hole 305 to obtain a structure as shown in FIG. 14 (F).

Step twenty-four, etching away the isolation layer 10 on the upper surface of the fourth etch stop layer 214, the isolation layer 10 on the bottom of the secondary source contact hole 304, and the isolation layer 10 on the bottom of the secondary drain contact hole 305, leaving only the isolation layer 10 on the inner wall of the secondary source contact hole 304 and the isolation layer 10 on the inner wall of the secondary drain contact hole 305, to obtain the structure as shown in (G) in Figure 14.

Step 25: Fill the isolation layer 10 with a metal layer 20 to obtain a structure as shown in FIG. 14 (H).

Step 26: Remove the metal layer 20 on the surface of the CMOS device by CMP technology, and polish the surface until it is flat and scratch-free, to obtain the structure shown in (I) in FIG. 14 .

It should be noted that, in the above preparation process, in order to save process flow and cost, the isolation layer 10 may be formed only on the inner wall of some contact holes, for example, the isolation layer 10 may be formed only on the inner wall of the secondary source contact hole 304 and the inner wall of the secondary drain contact hole 305, but not on the inner wall of the source contact hole 301 and the inner wall of the drain contact hole 302. In this case, the above steps 5 to 7 may be replaced by the following step 27:

Step 27: Fill the source contact hole 301 and the drain contact hole 302 with the metal layer 20 .

In addition, in the above preparation process, the secondary source contact hole 304 and the secondary drain contact hole 305 penetrate two etch stop layers and two dielectric layers. This is only an optional implementation. In actual operation, the secondary source contact hole 304 and the secondary drain contact hole 305 can penetrate the K-layer etch stop layer and the K-layer dielectric layer, and K can be any positive integer. For example, when the value of K is 1, the above steps 18 to 21 are replaced by the following steps 28 to 30:

Step 28: stacking a spin-on coating layer 410 , a bottom anti-reflection layer 420 and a photoresist layer 430 in sequence on a side of the third etch stop layer 213 opposite to the second dielectric layer 222 .

Step 29: photolithography patterns at positions corresponding to the secondary source contact hole 304 and the secondary drain contact hole 305 on the photoresist layer 430 .

Step 30, by etching the photoresist layer 430, the bottom anti-reflection layer 420, the spin-coated layer 410, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212, a secondary source contact hole 304 is obtained, which penetrates the spin-coated layer 410, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and is connected to the metal layer 20 filled in the source contact hole 301, and a secondary drain contact hole 305 is obtained, which penetrates the spin-coated layer 410, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and is connected to the metal layer 20 filled in the drain contact hole 302.

For another example, when the value of K is 3, the above steps 18 to 21 are replaced by the following steps 31 to 30:

Step 31: stacking the third dielectric layer 223 , the fourth dielectric layer 214 , the fourth dielectric layer 224 and the fifth dielectric layer 224 in sequence on the side of the third dielectric layer 213 opposite to the second dielectric layer 222 .

Step 32: stacking a spin-on coating layer 410 , a bottom anti-reflection layer 420 and a photoresist layer 430 in sequence on a side of the fifth etch stop layer opposite to the fourth dielectric layer 224 .

Step 33: photolithography patterns at positions corresponding to the secondary source contact hole 304 and the secondary drain contact hole 305 on the photoresist layer 430 .

Step thirty-four, by etching the photoresist layer 430, the bottom anti-reflection layer 420, the spin-coated layer 410, the fifth etch stop layer, the fourth dielectric layer 224, the fourth etch stop layer 214, the third dielectric layer 223, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212, a secondary source contact hole 304 is obtained, which penetrates the spin-coated layer 410, the fifth etch stop layer, the fourth dielectric layer 224, the fourth etch stop layer 214, the third dielectric layer 223, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and is connected to the metal layer 20 filled in the source contact hole 301, and a secondary drain contact hole 305 is obtained, which penetrates the spin-coated layer 410, the fifth etch stop layer, the fourth dielectric layer 224, the fourth etch stop layer 214, the third dielectric layer 223, the third etch stop layer 213, the second dielectric layer 222 and the second etch stop layer 212 and is connected to the metal layer 20 filled in the drain contact hole 302.

It should be understood that the case where the value of K is other positive integers can be directly implemented by referring to the above content, and the embodiments of the present application will not be repeated one by one.

In the above application three, the substrate 110, the first etching stop layer 211, the first dielectric layer 221, the second etching stop layer 212, the second dielectric layer 222, the third etching stop layer 213, the third dielectric layer 223 and the fourth etching stop layer 214 constitute the second layer structure of the CMOS device, and the secondary source contact hole structure and the secondary drain contact hole structure further connect the source 101 and the drain 102 from the top plane of the first layer structure to the top plane of the second layer structure, and then the wiring can be set on the top plane to connect the source 101 and the drain 102 to other devices in the chip that need to be connected. In this way, by setting another contact hole structure on the contact hole structure, the source 101 and the drain 102 can be further connected to a higher layer, and then when the wiring pressure on the top plane of the first layer structure is large, part of the wiring can be dispersed to the second layer structure to adapt to a denser CMOS device layout. Moreover, by surrounding the inner wall of the secondary source contact hole 304 and the inner wall of the secondary drain contact hole 305 with an isolation layer 10, it is possible to connect the source 101 and the drain 102 to the top plane of the second layer structure while ensuring as much as possible that the metal layer 20 filled in the secondary source contact hole 304 and the secondary drain contact hole 305 for connection does not short-circuit with the surrounding metal layers or the device active area, so as to disperse the routing pressure of a certain layer of the CMOS device while ensuring as much as possible that the reliability and manufacturing yield of the CMOS device are not reduced.

It should be noted that the scheme in the embodiment of the present application is applicable to all types of contact holes, including but not limited to source contact holes that directly contact the source, drain contact holes that directly contact the drain, gate contact holes that directly contact the gate, sub-source contact holes that directly or indirectly contact the source contact holes, sub-drain contact holes that directly or indirectly contact the drain, sub-gate contact holes that directly or indirectly contact the gate contact holes, etc. Moreover, the embodiment of the present application can set an isolation layer in one or more layers of contact holes of the semiconductor device according to actual needs. For example, an isolation layer can be set in the contact holes of a certain layer alone while no isolation layer is set in the contact holes of other layers, or an isolation layer can be set in the contact holes of multiple layers. In addition, the scheme in the embodiment of the present application also has good traceability. Any scheme in which an isolation layer is set between the inner wall of the contact hole of the semiconductor structure and the metal layer electrode is within the protection scope of the embodiment of the present application.

The present application also provides an electronic device, comprising a PCB and the semiconductor device as described above, wherein the semiconductor device is arranged on the surface of the PCB.

Exemplarily, the electronic device includes, but is not limited to: a smart phone, a smart watch, a tablet computer, a VR device, an AR device, a vehicle-mounted device, a desktop computer, a personal computer, a handheld computer, or a personal digital assistant.

Although some possible embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the embodiments of the present application and all changes and modifications falling within the scope of the present application.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the protection scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

A semiconductor device, comprising:

a contact portion disposed on the substrate;

A stacked structure stacked on one side of the contact portion, the stacked structure comprising at least one etch stop layer and at least one dielectric layer alternately stacked, the stacked structure having a first contact hole, the first contact hole passing through the stacked structure and conducting to the contact portion;

a first metal layer, contacting the contact portion through the first contact hole; and

The first isolation layer is arranged between the first metal layer and the inner wall of the first contact hole, and the realization material of the first isolation layer includes a dense material.
The semiconductor device of claim 1, wherein the dense material comprises silicon nitride.
The semiconductor device according to claim 2, characterized in that the dense material also includes silicon oxide or metal oxide.
The semiconductor device of claim 1, wherein the dense material comprises a metal oxide.
The semiconductor device according to any one of claims 1 to 4, characterized in that

The contact portion is specifically a source electrode or a drain electrode;

The at least one etch stop layer includes a first etch stop layer and a second etch stop layer, and the at least one dielectric layer includes a first dielectric layer.
The semiconductor device according to any one of claims 1 to 4, characterized in that the semiconductor device further comprises a first etch stop layer and a first dielectric layer stacked in sequence and arranged between the substrate and the stack structure;

The contact portion is specifically a gate, the gate is located in a gate hole, the gate hole further includes a sidewall surrounding the gate, the gate hole penetrates the first etching stop layer and the first dielectric layer, and the bottom of the gate hole is buried in the substrate;

The at least one etch stop layer includes a second etch stop layer and a third etch stop layer, and the at least one dielectric layer includes a second dielectric layer.
The semiconductor device according to any one of claims 1 to 4, characterized in that the semiconductor device further comprises a first etch stop layer, a first dielectric layer, and a second etch stop layer stacked in sequence and arranged between the substrate and the stack structure;

The contact portion is specifically a second metal layer filled in a second contact hole, the second contact hole penetrates the first etching stop layer, the first dielectric layer and the second etching stop layer, and is connected to a source electrode or a drain electrode, and the source electrode or the drain electrode is arranged on the substrate;

The at least one etching stop layer includes K third etching stop layers, and the at least one dielectric layer includes K second dielectric layers, where K is a positive integer.
The semiconductor device according to claim 7 is characterized in that a second isolation layer is further provided between the inner wall of the second contact hole and the second metal layer.
The semiconductor device according to any one of claims 1 to 8, characterized in that

The first isolation layer is disposed around the entire inner wall of the first contact hole;

and / or,

The second isolation layer is disposed around the entire inner wall of the second contact hole.
The semiconductor device according to any one of claims 1 to 9, characterized in that, for any etch stop layer from the first etch stop layer to the third etch stop layer, the etching selectivity ratio of the etch stop layer and the dielectric layer adjacent to the etch stop layer from the first dielectric layer to the second dielectric layer is greater than 1.
The semiconductor device according to any one of claims 1 to 10, characterized in that the contact portion contacts the first metal layer and the first isolation layer.
The semiconductor device according to any one of claims 1 to 11, characterized in that the semiconductor device is implemented by one or more of the following designs:

The material for implementing any one of the first etch stop layer to the third etch stop layer comprises silicon nitride;

The first metal layer and/or the second metal layer are made of copper, cobalt, tungsten or rubidium.
A method for preparing a semiconductor device, characterized by comprising:

forming a contact portion disposed on the substrate;

At least one etching stop layer and at least one dielectric layer are alternately stacked on one side of the contact portion to obtain a stacked structure;

Etching to form a first contact hole penetrating the stacked structure and connected to the contact portion;

A first metal layer and a first isolation layer are formed in the first contact hole, the first metal layer contacts the contact portion through the first contact hole, the first isolation layer is arranged between the first metal layer and the inner wall of the first contact hole, and the implementation material of the first isolation layer includes a dense material.
The method according to claim 13, characterized in that

Before etching to form a first contact hole penetrating the stacked structure and connected to the contact portion, the method further includes:

forming an organic material layer on a side of the stacked structure opposite to the contact portion;

The etching forms a first contact hole penetrating the stacked structure and connected to the contact portion, comprising:

Photolithography a pattern at a position corresponding to the first contact hole on the organic material layer;

Etching the first contact hole on the organic material layer and the stacked structure according to the pattern;

The organic material layer is removed.
The method of claim 14, wherein the organic material layer comprises one or more layers of a spin-coated layer, a bottom anti-reflective layer, and a photoresist layer.
The method according to any one of claims 13 to 15, characterized in that the contact portion is specifically a source or a drain;

The alternate stacking of at least one etching stop layer and at least one dielectric layer on one side of the contact portion comprises:

A first etch stop layer, a first dielectric layer, and a second etch stop layer are sequentially stacked on one side of the substrate.
The method according to any one of claims 13 to 15, characterized in that the contact portion is specifically a gate, and the semiconductor device further comprises a first etch stop layer and a first dielectric layer stacked in sequence and arranged between the substrate and the stack structure;

The forming of the contact portion disposed on the substrate comprises:

forming the substrate, the first etching stop layer and the first dielectric layer stacked in sequence;

Etching to form a gate hole penetrating the first etching stop layer and the first dielectric layer, wherein the bottom of the gate hole is buried in the substrate;

forming a gate and a sidewall surrounding the gate in the gate hole;

The alternate stacking of at least one etching stop layer and at least one dielectric layer on one side of the contact portion comprises:

A second etch stop layer, a second dielectric layer and a third etch stop layer are sequentially stacked on a side of the first dielectric layer opposite to the first etch stop layer.
The method according to any one of claims 13 to 15, characterized in that the contact portion is specifically a second metal layer filled in the second contact hole, and the semiconductor device further comprises a first etch stop layer, a first dielectric layer, and a second etch stop layer stacked in sequence and arranged between the substrate and the stack structure;

The forming of the contact portion disposed on the substrate comprises:

forming the substrate and a source electrode or a drain electrode disposed on the substrate;

Alternately stacking the first etch stop layer, the first dielectric layer, and the second etch stop layer on one side of the substrate;

Etching to form the second contact hole penetrating the first etch stop layer, the first dielectric layer and the second etch stop layer;

Filling a second metal layer in the second contact hole, wherein the second metal layer contacts the source electrode or the drain electrode;

The alternate stacking of at least one etching stop layer and at least one dielectric layer on one side of the contact portion comprises:

K second dielectric layers and K third dielectric layers are alternately stacked on a side of the second etch stop layer opposite to the first dielectric layer, where K is a positive integer.
The method according to claim 18, wherein filling the second contact hole with a second metal layer comprises:

A second isolation layer and the second metal layer are formed in the second contact hole, and the second isolation layer is arranged between an inner wall of the second contact hole and the second metal layer.
The method according to any one of claims 13 to 19, characterized in that forming a first isolation layer in the first contact hole comprises:

The first isolation layer is disposed around the entire inner wall of the first contact hole.
An electronic device, comprising a printed circuit board (PCB) and a semiconductor device as claimed in any one of claims 1 to 12, wherein the semiconductor device is arranged on a surface of the PCB.