CN105990403B - Grid and forming method thereof - Google Patents
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- CN105990403B CN105990403B CN201510048272.3A CN201510048272A CN105990403B CN 105990403 B CN105990403 B CN 105990403B CN 201510048272 A CN201510048272 A CN 201510048272A CN 105990403 B CN105990403 B CN 105990403B
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000010410 layer Substances 0.000 claims abstract description 87
- 229910052751 metal Inorganic materials 0.000 claims abstract description 69
- 239000002184 metal Substances 0.000 claims abstract description 69
- 239000002245 particle Substances 0.000 claims abstract description 32
- 230000008569 process Effects 0.000 claims abstract description 16
- 239000002356 single layer Substances 0.000 claims abstract description 14
- 230000001105 regulatory effect Effects 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 8
- -1 TiTa Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 229910052593 corundum Inorganic materials 0.000 claims description 6
- 229910052742 iron Inorganic materials 0.000 claims description 6
- 229910052749 magnesium Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
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- 238000004519 manufacturing process Methods 0.000 abstract description 4
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- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
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- 229920005591 polysilicon Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- IRPGOXJVTQTAAN-UHFFFAOYSA-N 2,2,3,3,3-pentafluoropropanal Chemical compound FC(F)(F)C(F)(F)C=O IRPGOXJVTQTAAN-UHFFFAOYSA-N 0.000 description 1
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
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- 239000011521 glass Substances 0.000 description 1
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- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
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Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a method for forming a grid electrode, which comprises the following steps: forming a single-layer and doped metal work function adjusting layer on the gate dielectric layer so that the target work function is between the work function of the metal work function layer and the work function of the doped particles; and forming other gate layers on the metal work function adjusting layer. The method is easy to adjust the threshold voltage, simple in process, free of realization of multiple layers of metal grids, and low in manufacturing cost.
Description
Technical field
The present invention relates to field of semiconductor devices, in particular to a kind of grid and forming method thereof.
Background technique
With the continuous reduction of device size, using " high-k/metal gate (high-k gate dielectric material and metal gates) " technology as core
The cmos device grid engineering research of the heart is most representative core process in 22 nanometers and following technology.
In the gate structure of high-k/metal gate, play the role of adjusting threshold voltage Vt by the work function of metal gate,
And in order to obtain suitable threshold voltage, it usually needs deposit the different metal gate material of multilayer respectively, complex process and
It is unsuitable for realizing, especially for three-dimensional fin device, is more not easy to realize.
Summary of the invention
The purpose of the present invention aims to solve the problem that above-mentioned technological deficiency, provides a kind of grid and forming method thereof, simple and be easy to
Carry out the adjusting of the threshold voltage of grid.
The present invention provides a kind of forming methods of grid, comprising:
Semiconductor substrate is provided, and the first hard exposure mask is formed on the substrate；
Etched substrate forms fin；
It is planarized, and forms separation layer；
Pseudo- gate dielectric material and pseudo- grid material are deposited, and forms pseudo- gate dielectric layer and dummy grid after patterning；
Side wall is formed on the side wall of dummy grid；
In the end epitaxial growth source-drain area of fin, and form pseudo- gate device；
Pseudo- gate dielectric layer and dummy grid are removed, to form opening, and deposits and forms gate dielectric layer；
The metal work function regulating course that single layer and doping are formed on gate dielectric layer, so that target workfunction is between metal
Between work-function layer and the work function of the particle of doping；
Other grid layers are formed on metal work function regulating course.
Optionally, the step of formation gate dielectric layer includes:
Gate dielectric layer is formed on the fin of fin formula field effect transistor.
Optionally, the gate dielectric layer is formed on the inner wall of opening, is open to be formed after the pseudo- grid of removal.
Optionally, the metal work function regulating course is TiN, TiTa, TiAl or Al2O3。
Optionally, the particle of doping includes: Al, Fe, Mg, Ni, W, C, N or H.
It include: in deposit metal work function in the step of forming the metal work function regulating course of single layer and doping on gate dielectric layer
While several layers, it is passed through the gas containing doping particle, is then annealed.
Include: in the step of forming the metal work function regulating course of single layer and doping on gate dielectric layer
Using atom layer deposition process, the metal work function regulating course of single layer is deposited；
Using chemical vapor deposition process, continue to deposit metal work function regulating course, and be passed through the gas containing doping particle
Body, to obtain target workfunction；
It anneals, to activate doping.
In addition, the present invention also provides a kind of grids, comprising:
Semiconductor substrate；
The fin formed on substrate；
In the end epitaxial growth source-drain area of fin, and form pseudo- gate device；
The gate dielectric layer of formation is deposited after removing pseudo- gate dielectric layer and dummy grid formation opening；
Metal work function regulating course on gate dielectric layer has doping particle in metal work function layer, so that target function
Function is between metal work function layer and the work function of the particle of doping；Metal work function regulating course successively uses atomic layer deposition
Product technique and chemical vapor deposition process are formed；It adulterates particle and carries out chemical vapor deposition process in metal work function regulating course
When by containing doping particle gas formed；
Other grid layers on metal work function regulating course.
Optionally, the metal work function regulating course is TiN, TiTa, TiAl or Al2O3。
Optionally, the particle of doping includes: Al, Fe, Mg, Ni, W, C, N or H.
Grid provided in an embodiment of the present invention and forming method thereof forms the metal work function regulating course of single layer, passes through
It is doped wherein, the adjusting of Lai Shixian target workfunction, by this method there is metal work function regulating course desired
Threshold voltage is easy to carry out the adjusting of threshold voltage, and simple process is reduced without being realized by multiple layer metal grid
Manufacturing cost.
Detailed description of the invention
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Obviously and it is readily appreciated that, in which:
Fig. 1 shows the flow chart of the forming method of grid according to an embodiment of the present invention；
Fig. 2-4 shows each formation stages of method of forming gate progress device fabrication according to an embodiment of the present invention
Structural schematic diagram.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not construed as limiting the claims.
The invention proposes a kind of forming methods of grid, refering to what is shown in Fig. 1, including: to form single layer on gate dielectric layer
Metal work function regulating course；Metal work function regulating course is doped, so that target workfunction is between metal work function
Between layer and the work function of the particle of doping；Contact metal layer is formed on metal work function regulating course.
In the present invention, the metal work function regulating course for foring single layer, by being doped wherein, Lai Shixian target
The adjusting of work function makes metal work function regulating course have desired threshold voltage, is easy to carry out threshold voltage by this method
Adjusting, and simple process reduces manufacturing cost without realizing by multiple layer metal grid.
Grid in the present invention can be formed in planar device, three-dimensional device and nano-wire devices etc., and planar device is half
The gate dielectric layer and grid of device are formed on conductor substrate, three-dimensional device such as fin formula field effect transistor forms device on fin
Gate dielectric layer and grid, nano-wire devices form the gate dielectric layer and grid of device on nano wire.The forming method can be with
It is the grid formed in preceding grid technique, is also possible to remove the grid formed after pseudo- grid in rear grid technique.
Technical solution and technical effect in order to better understand the present invention, below with reference to specific embodiment to this hair
Bright embodiment is described in detail, in the following embodiments, to be formed in the rear grid technique of fin formula field effect transistor
Grid.
Firstly, forming pseudo- gate device.
Specifically, pseudo- gate device can be formed by following steps.
Firstly, semiconductor substrate 100 is provided, with reference to shown in Fig. 2.
In embodiments of the present invention, the semiconductor substrate 100 can be Si substrate, Ge substrate etc..In other embodiments
In, it can also be the substrate for including other elements semiconductor or compound semiconductor, such as GaAs, InP or SiC etc. can be with
For laminated construction, such as Si/SiGe etc..In the present embodiment, the semiconductor substrate 100 is body silicon substrate.
It then, can be by forming the first hard exposure mask (not shown go out) of silicon nitride on the substrate 100 of body silicon；Then,
Using lithographic technique, such as the method for RIE (reactive ion etching), etched substrate 100 forms fin 100, so as to form lining
Fin 102 on bottom 100, with reference to shown in Fig. 2.
Then, it is filled the isolated material (not shown go out) of silica, and carries out chemical-mechanical planarization, with first
Hard exposure mask is stop-layer；Then, wet etching can be used, such as the hard exposure mask of high temperature phosphoric acid removal silicon nitride；Then, using hydrogen
The certain thickness isolated material of fluoric acid erosion removal retains the isolated material of part between fin, so as to form separation layer
104, with reference to shown in Fig. 2.
Then, pseudo- gate dielectric material and pseudo- grid material are deposited respectively, and pseudo- gate dielectric material can be situated between for thermal oxide layer or high k
Material etc. can be in the present embodiment silica, can be formed by the method for thermal oxide.Pseudo- grid material can be
Amorphous silicon, polysilicon etc. are amorphous silicon in the present embodiment.Pseudo- gate dielectric layer and dummy grid (not shown go out) is formed after patterning.
Then, side wall is formed on the side wall of dummy grid, side wall can have single or multi-layer structure, can be by nitrogenizing
Silicon, silica, silicon oxynitride, silicon carbide, fluoride-doped silica glass, low k dielectric material and combinations thereof and/or other conjunctions
Suitable material is formed.
Then, while doping in situ can be carried out by selective epitaxial process in the end epitaxial growth source-drain area of fin,
It goes forward side by side line activating, to form source-drain area.It can also be injected by doping, and carry out annealing activation, formed in the both ends of fin
Source-drain area.
Then, the material of interlayer dielectric layer, such as undoped silica (SiO are then covered2), doping silica
(such as Pyrex, boron-phosphorosilicate glass), silicon nitride (Si3N4) or other low k dielectric materials；Then, it is planarized, such as
Chemical mechanical grinding, until exposing dummy grid, to form interlayer dielectric layer.
So far, pseudo- gate device is formd.
Then, pseudo- gate dielectric layer and dummy grid are removed, to form opening.
Specifically, lithographic technique can be used, such as using the dummy grid of wet etching removal amorphous silicon, and further
Pseudo- gate dielectric layer is removed, until the surface of fin is exposed, thus, the opening of exposed fin is formd in the region of dummy grid.
Then, the formation of further progress gate dielectric layer 110 and metal work function regulating course 112, as shown in Figure 2.
It is common, before depositing gate dielectric layer, boundary layer (not shown go out), the boundary can be initially formed on the surface of fin
Surface layer can be formed by quickly aoxidizing, to improve the interfacial characteristics of device.Then, the deposit of gate dielectric layer 110, institute are carried out
Stating gate dielectric layer can be for high K medium material (for example, compare with silica, the material with high dielectric constant) or other are suitable
Dielectric material, high K medium material such as hafnium base oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc., the metal
Gate electrode can be one or more layers structure, may include metal material or polysilicon or their combination, in the present embodiment,
Boundary layer with a thickness of 0.7nm, gate dielectric layer HFO2, thickness can be 2.5nm.
Then, the deposit of metal work function regulating course 112 is carried out.
In the present invention, which is single layer structure, i.e., for by the material layer shape of a certain work function
At for target workfunction between metal work function layer and the work function of the particle of doping, which is gold
Belong to the material layer for primarily serving in grid and adjusting work function, such as can be TiN, TiTa, TiAl or Al2O3Deng thickness range can
Think that 3-10nm, the particle of doping may include the metallics such as Al, Fe, Mg, Ni or W, can also including C, N or H etc. non-gold
Belong to particle., can be while depositing technics when forming the metal work function regulating course with doping, being passed through has doping
The gas of particle, so that forming the particle of doping in metal work function regulating course, after the completion of deposit, leads to while deposit
Annealing is crossed to activate doping, to form the metal work function regulating course with Uniform Doped.Wherein, target workfunction is between gold
It, can be according to the work function of target workfunction and metal work function layer between the work function for belonging to the particle of work-function layer and doping
It selects suitably to adulterate particle, with the work function needed for obtaining, this method forms uniformly in metal work function regulating course
Doping, and then obtain the characteristic of stable threshold voltage, carry out work function without repeatedly depositing the material of different work functions
Adjusting, it is simple for process.
In the present embodiment, which is TiN, in the metal work function tune for specifically forming the TiN
When ganglionic layer, firstly, depositing the metal work function regulating course of single layer using atomic layer deposition (ALD) technique, thickness can be
The thin layer of 1.5nm, the TiN which forms have finer and close structure, can serve as the blocking of subsequent deposition and doping
Layer carries out gate dielectric layer and channel region to avoid the particle of doping；Then, using chemical vapor deposition (CVD) technique, continue
Deposit the metal work function regulating course of TiN, wherein the effective work function of TiN is 4.7eV, if (expectation is adjusted to target workfunction
Work function) be 4.3eV, can choose the doping particle of Al, in the present embodiment, the gas of aluminum fluoride can be passed through, flow can
Think 7L/min, then, carries out annealing process, to activate doping, the substantially effective work function of 4.3eV can be obtained after annealing
Work function regulating course.
Then, the filling of other grid layers is carried out.
In the present embodiment, the filling for carrying out contact grid layer 114, as shown in figure 4, the contact grid layer 114 can be
W, polysilicon, Al or W and the mixed structure of Cu etc..Then, can by flatening process, remove opening outside gate dielectric layer,
Metal work function regulating course and other grid layers, to re-form gate dielectric layer and grid in the opening.
So far, in the rear grid technique of fin formula field effect transistor, the grid of substitution is formd on fin, is wrapped in the grid
The metal work function regulating course for including single layer and doping carries out the adjusting of device work function by this layer, simple for process, and can
Control property is strong.
In addition, the present invention also provides the grids formed by the above method, refering to what is shown in Fig. 4, the grid includes: gate medium
Layer 110；Metal work function regulating course 112 on gate dielectric layer 110 has doping particle in metal work function layer 112, so that
Target workfunction is between metal work function layer and the work function of the particle of doping；Its on metal work function regulating course 112
His grid layer 114.
In an embodiment of the present invention, the metal work function regulating course can be TiN, TiTa, TiAl or Al2O3, doping
Particle may include: the metallics such as Al, Fe, Mg, Ni or W, can also including C, N or H etc. nonmetal particles.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications or equivalent example modified to equivalent change to technical solution of the present invention.Therefore,
Anything that does not depart from the technical scheme of the invention are made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, all of which are still within the scope of protection of the technical scheme of the invention.
Claims (7)
1. a kind of forming method of grid characterized by comprising
Semiconductor substrate is provided, and the first hard exposure mask is formed on the substrate；
Etched substrate forms fin；
It is planarized, and forms separation layer；
Pseudo- gate dielectric material and pseudo- grid material are deposited, and forms pseudo- gate dielectric layer and dummy grid after patterning；
Side wall is formed on the side wall of dummy grid；
In the end epitaxial growth source-drain area of fin, and form pseudo- gate device；
Pseudo- gate dielectric layer and dummy grid are removed, to form opening, and deposits and forms gate dielectric layer；
The metal work function regulating course that single layer and doping are formed on gate dielectric layer, so that target workfunction is between metal work function
Between several layers and the work function of the particle adulterated；
Other grid layers are formed on metal work function regulating course；
Formed gate dielectric layer the step of include:
Gate dielectric layer is formed on the fin of fin formula field effect transistor；
Include: in the step of forming the metal work function regulating course of single layer and doping on gate dielectric layer
Using atom layer deposition process, the metal work function regulating course of single layer is deposited；
Using chemical vapor deposition process, continue to deposit metal work function regulating course, and be passed through the gas containing doping particle, with
Obtain target workfunction；
It anneals, to activate doping.
2. being open the method according to claim 1, wherein the gate dielectric layer is formed on the inner wall of opening
To be formed after the pseudo- grid of removal.
3. the method according to claim 1, wherein the metal work function regulating course is TiN, TiTa, TiAl
Or Al2O3。
4. according to the method described in claim 3, it is characterized in that, the particle of doping includes: Al, Fe, Mg, Ni, W, C, N or H.
5. a kind of grid characterized by comprising
Semiconductor substrate；
The fin formed on substrate；
In the end epitaxial growth source-drain area of fin, and form pseudo- gate device；
The gate dielectric layer of formation is deposited after removing pseudo- gate dielectric layer and dummy grid formation opening；
Metal work function regulating course on gate dielectric layer has doping particle in metal work function layer, so that target workfunction
Between metal work function layer and the work function of the particle of doping；Metal work function regulating course successively uses atomic layer deposition work
Skill and chemical vapor deposition process are formed；It is logical when metal work function regulating course carries out chemical vapor deposition process to adulterate particle
The gas containing doping particle is crossed to be formed；
Other grid layers on metal work function regulating course.
6. grid according to claim 5, which is characterized in that the metal work function regulating course is TiN, TiTa, TiAl
Or Al2O3。
7. grid according to claim 6, which is characterized in that the particle of doping includes: Al, Fe, Mg, Ni, W, C, N or H.
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| Application Number | Priority Date | Filing Date | Title |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510048272.3A CN105990403B (en) | 2015-01-29 | 2015-01-29 | Grid and forming method thereof |
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| CN109148290B (en) * | 2017-06-28 | 2020-12-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN107221513A (en) * | 2017-07-12 | 2017-09-29 | 中国科学院微电子研究所 | CMOS device and manufacturing method thereof |
| US10665450B2 (en) * | 2017-08-18 | 2020-05-26 | Applied Materials, Inc. | Methods and apparatus for doping engineering and threshold voltage tuning by integrated deposition of titanium nitride and aluminum films |
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| CN102074469A (en) * | 2009-11-25 | 2011-05-25 | 中国科学院微电子研究所 | Method for adjusting work function of metal gate of PMOS (P-channel metal oxide semiconductor) device |
| CN102254805A (en) * | 2010-05-19 | 2011-11-23 | 中国科学院微电子研究所 | Method for adjusting work function of metal gate suitable for NMOS (N-channel metal oxide semiconductor) device |
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2015
- 2015-01-29 CN CN201510048272.3A patent/CN105990403B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074469A (en) * | 2009-11-25 | 2011-05-25 | 中国科学院微电子研究所 | Method for adjusting work function of metal gate of PMOS (P-channel metal oxide semiconductor) device |
| CN102254805A (en) * | 2010-05-19 | 2011-11-23 | 中国科学院微电子研究所 | Method for adjusting work function of metal gate suitable for NMOS (N-channel metal oxide semiconductor) device |
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| Title |
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| Work Function Tunability by Incorporating Lanthanum and Aluminum into Refractory Metal Nitrides and a Feasible Integration Process;Xin Peng Wang, et al.;《IEEE》;20061026;1-3 * |
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