CN105990403A - Gate and forming method thereof - Google Patents
Gate and forming method thereof Download PDFInfo
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- CN105990403A CN105990403A CN201510048272.3A CN201510048272A CN105990403A CN 105990403 A CN105990403 A CN 105990403A CN 201510048272 A CN201510048272 A CN 201510048272A CN 105990403 A CN105990403 A CN 105990403A
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- work function
- metal work
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- regulating course
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Abstract
The invention provides a gate forming method comprising the steps of forming a single doped metal work function adjustment layer on a gate dielectric layer to enable a target work function to be between the metal work function layer and a work function of doped particles, and forming other gate layers on the metal work function adjustment layer. Through the method, the threshold voltage can be adjusted easily, the process is simple and can be implemented without multiple metal gate layers, and the manufacturing cost is reduced.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly to a kind of grid and forming method thereof.
Background technology
Along with the continuous reduction of device size, with " high-k/metal gate (high-k gate dielectric material and metal gate
Pole) " technology be the cmos device grid engineering research of core be that 22 nanometers and techniques below most have generation
The core process of table.
In the grid structure of high-k/metal gate, play regulation threshold value electricity by the work function of metal gate
The effect of pressure Vt, and in order to obtain suitable threshold voltage, it usually needs deposit multilamellar is different respectively
Metal gate material, its complex process and be unsuitable for realizing, especially for three-dimensional fin device,
More it is not easy to realize.
Summary of the invention
The purpose of the present invention aims to solve the problem that above-mentioned technological deficiency, it is provided that a kind of grid and forming method thereof,
Simple and be prone to carry out the regulation of the threshold voltage of grid.
The invention provides the forming method of a kind of grid, including:
Gate dielectric layer is formed monolayer and the metal work function regulating course of doping, so that target work content
Number is between the work function of metal work function layer and the particle of doping；
Metal work function regulating course is formed other grid layers.
Optionally, the step forming gate dielectric layer includes:
Semiconductor substrate or fin are formed gate dielectric layer.
Optionally, described gate dielectric layer is formed on the inwall of opening, and opening is for being formed after removing pseudo-grid.
Optionally, described metal work function regulating course is TiN, TiTa, TiAl or Al2O3。
Optionally, the particle of doping includes: Al, Fe, Mg, Ni, W, C, N or H.
The step of the metal work function regulating course forming monolayer and doping on gate dielectric layer includes: forming sediment
While long-pending metal work function layer, it is passed through the gas containing doping particle, then anneals.
The step of the metal work function regulating course forming monolayer and doping on gate dielectric layer includes:
Use atom layer deposition process, the metal work function regulating course of deposit monolayer；
Use chemical vapor deposition method, continue deposit metal work function regulating course, and be passed through containing mixing
The gas of foreign particle；
Anneal.
Additionally, present invention also offers a kind of grid, including:
Gate dielectric layer；
Metal work function regulating course on gate dielectric layer, has doping particle in metal work function layer, with
Make target workfunction between the work function of metal work function layer and the particle of doping；
Other grid layers on metal work function regulating course.
Optionally, described metal work function regulating course is TiN, TiTa, TiAl or Al2O3。
Optionally, the particle of doping includes: Al, Fe, Mg, Ni, W, C, N or H.
Grid that the embodiment of the present invention provides and forming method thereof, the metal work function defining monolayer is adjusted
Ganglionic layer, by being doped wherein, realizes the regulation of target workfunction, makes gold by the method
Belong to work function regulating course and there is desired threshold voltage, it is easy to carry out the regulation of threshold voltage, and technique
Simply, it is not necessary to realized by multiple layer metal grid, reduce manufacturing cost.
Accompanying drawing explanation
Present invention aspect that is above-mentioned and/or that add and advantage are from retouching embodiment below in conjunction with the accompanying drawings
Will be apparent from easy to understand in stating, wherein:
Fig. 1 shows the flow chart of the forming method of grid according to embodiments of the present invention；
Fig. 2-4 shows that method of forming gate according to embodiments of the present invention carries out each of device fabrication
The structural representation of formation stages.
Detailed description of the invention
Embodiments of the invention are described below in detail, and the example of described embodiment is shown in the drawings, its
In the most same or similar label represent same or similar element or there is same or like merit
The element of energy.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining this
Bright, and be not construed as limiting the claims.
The present invention proposes the forming method of a kind of grid, with reference to shown in Fig. 1, including: at gate medium
The metal work function regulating course of monolayer is formed on layer；Metal work function regulating course is doped, so that
Obtain target workfunction between the work function of metal work function layer and the particle of doping；At metal work function
Contact metal layer is formed on number regulating course.
In the present invention, define the metal work function regulating course of monolayer, by being doped wherein,
Realize the regulation of target workfunction, make metal work function regulating course have desired threshold by the method
Threshold voltage, it is easy to carry out the regulation of threshold voltage, and technique is simple, it is not necessary to by multiple layer metal grid
Realize, reduce manufacturing cost.
Grid in the present invention can be formed at planar device, three-dimensional device and nano-wire devices etc., flat
Face device forms gate dielectric layer and the grid of device, three-dimensional device such as fin field effect on a semiconductor substrate
Answering transistor, form gate dielectric layer and the grid of device on fin, nano-wire devices is shape on nano wire
Become gate dielectric layer and the grid of device.This forming method can be the grid formed in front grid technique, also
It can be the grid formed after the pseudo-grid of removal in rear grid technique.
In order to be better understood from technical scheme and technique effect, below with reference to concrete reality
Execute example embodiments of the invention are described in detail, in the following embodiments, for imitating in fin field
Answer formation grid in the rear grid technique of transistor.
First, pseudo-gate device is formed.
Concrete, pseudo-gate device can be formed by following steps.
First, it is provided that Semiconductor substrate 100, with reference to shown in Fig. 2.
In embodiments of the present invention, described Semiconductor substrate 100 can be Si substrate, Ge substrate etc..?
In other embodiments, it is also possible to be the substrate including other elemental semiconductors or compound semiconductor, such as
GaAs, InP or SiC etc., it is also possible to for laminated construction, such as Si/SiGe etc..In the present embodiment,
Described Semiconductor substrate 100 is body silicon substrate.
Then, can be (not shown by forming the first hard mask of silicon nitride on the substrate 100 of body silicon
Go out)；Then, lithographic technique, the method for such as RIE (reactive ion etching), etched substrate 100 are used
Form fin 100, thus define the fin 102 on substrate 100, with reference to shown in Fig. 2.
Then, it is filled with the isolated material (not shown) of silicon dioxide, and it is smooth to carry out chemical machinery
Change, with the first hard mask as stop-layer；Then, it is possible to use wet etching, nitridation is removed such as high temperature phosphoric acid
The hard mask of silicon；Then, use the certain thickness isolated material of Fluohydric acid. erosion removal, member-retaining portion every
From material between fin, thus define sealing coat 104, with reference to shown in Fig. 2.
Then, the pseudo-gate dielectric material of deposit and pseudo-grid material respectively, pseudo-gate dielectric material can be thermal oxide
Layer or high K medium material etc., can be silicon dioxide in the present embodiment, can be by the method for thermal oxide
Formed.Pseudo-grid material can be non-crystalline silicon, polysilicon etc., in the present embodiment, for non-crystalline silicon.Patterning
The pseudo-gate dielectric layer of rear formation and dummy grid (not shown).
Then, forming side wall on the sidewall of dummy grid, side wall can have single or multiple lift structure, can
To be situated between by silicon nitride, silicon oxide, silicon oxynitride, carborundum, fluoride-doped silica glass, low k electricity
Material and combinations thereof, and/or the formation of other suitable materials.
Then, can carry out by selective epitaxial process at the end epitaxial growth source-drain area of fin simultaneously
Doping, line activating of going forward side by side in situ, thus form source-drain area.Can also be injected by doping, and anneal
Activate, the two ends of fin are formed source-drain area.
Then, the material of interlayer dielectric layer, the most unadulterated silicon oxide (SiO are then covered2), mix
Miscellaneous silicon oxide (such as Pyrex, boron-phosphorosilicate glass etc.), silicon nitride (Si3N4) or other low k
Dielectric material；Then, planarize, such as cmp, until exposing dummy grid,
Thus form interlayer dielectric layer.
So far, pseudo-gate device is defined.
Then, pseudo-gate dielectric layer and dummy grid are removed, to form opening.
Concrete, it is possible to use lithographic technique, such as use wet etching to remove the dummy grid of non-crystalline silicon,
And further remove pseudo-gate dielectric layer, until exposing the surface of fin, thus, in the district of dummy grid
Territory defines the opening exposing fin.
Then, carry out gate dielectric layer 110 and the formation of metal work function regulating course 112 further, as
Shown in Fig. 2.
Common, before deposit gate dielectric layer, boundary layer (figure can be initially formed on the surface of fin
Not shown), this boundary layer can be formed by Quick Oxidation, to improve the interfacial characteristics of device.
Then, carrying out the deposit of gate dielectric layer 110, described gate dielectric layer can be high K medium material (example
As, compare with silicon oxide, there is the material of high-k) or other suitable dielectric materials, high k
Dielectric material such as hafnio oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc., described
Metal gate electrode can be one or more layers structure, can include metal material or polysilicon or their group
Closing, in the present embodiment, the thickness of boundary layer is 0.7nm, and gate dielectric layer is HFO2, its thickness is permissible
For 2.5nm.
Then, the deposit of metal work function regulating course 112 is carried out.
In the present invention, this metal work function regulating course 112 is single layer structure, is i.e. by a certain work content
The material layer of number is formed, target workfunction between metal work function layer and the particle of doping work function it
Between, this metal work function regulating course is the material layer primarily serving regulation work function in metal gates, example
As being TiN, TiTa, TiAl or Al2O3Deng, thickness range can be 3-10nm, doping
Particle can include the metallics such as Al, Fe, Mg, Ni or W, it is also possible to includes C, N or H
Deng nonmetal particle.When forming this metal work function regulating course with doping, can be in deposit work
While skill, it is passed through the gas with doping particle, while deposit so that metal work function is adjusted
Ganglionic layer is formed the particle of doping, after deposit completes, activates doping by annealing, thus formed
There is the metal work function regulating course of Uniform Doped.Wherein, target workfunction is between metal work function layer
And between the work function of the particle of doping, can be according to target workfunction and the merit of metal work function layer
Function selects suitably to adulterate particle, and the work function needed for obtaining, the method is in metal work function
Regulating course defines uniform doping, and then obtains the characteristic of stable threshold voltage, it is not necessary to repeatedly
The material of deposit different work functions carries out the regulation of work function, simple for process.
In the present embodiment, this metal work function regulating course 112 is TiN, forms this TiN concrete
Metal work function regulating course time, first, use ald (ALD) technique, deposit monolayer
Metal work function regulating course, thickness can be 1.5nm, the thin layer of TiN that this ALD technique is formed
There is finer and close structure, the barrier layer of subsequent deposition and doping can be served as, to avoid the grain of doping
Son carries out gate dielectric layer and channel region；Then, use chemical gaseous phase deposition (CVD) technique, continue
The metal work function regulating course of continuous deposit TiN, wherein, the effective work function of TiN is 4.7eV, if mesh
Mark work function (work function that expectation is adjusted to) is 4.3eV, can select the doping particle of Al, this
In embodiment, can be passed through the gas of aluminium fluoride, flow can be 7L/min, then, anneals
Technique, to activate doping, can obtain the work function of the effective work function of substantially 4.3eV after annealing
Regulating course.
Then, the filling of other grid layers is carried out.
In the present embodiment, carry out contacting the filling of grid layer 114, as shown in Figure 4, these contact grid
Pole layer 114 can be the mixed structure etc. of W, polysilicon, Al or W and Cu.Then, Ke Yitong
Cross flatening process, remove gate dielectric layer, metal work function regulating course and other grids outside opening
Layer, thus re-formed gate dielectric layer and grid in the opening.
So far, in the rear grid technique of fin formula field effect transistor, fin defines the grid of replacement,
This grid includes the metal work function regulating course of monolayer and doping, carries out device work function by this layer
Regulation, simple for process, and controllability is strong.
Additionally, present invention also offers the grid formed by said method, with reference to shown in Fig. 4, these grid
Pole includes: gate dielectric layer 110；Metal work function regulating course 112 on gate dielectric layer 110, metal merit
Function layer 112 has doping particle, so that target workfunction is between metal work function layer and doping
Particle work function between；Other grid layers 114 on metal work function regulating course 112.
In an embodiment of the present invention, described metal work function regulating course can be TiN, TiTa, TiAl
Or Al2O3, the particle of doping may include that the metallics such as Al, Fe, Mg, Ni or W, also may be used
To include the nonmetal particles such as C, N or H.
The above, be only presently preferred embodiments of the present invention, and the present invention not makees any form
On restriction.
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention.Appoint
What those of ordinary skill in the art, without departing under technical solution of the present invention ambit, all can profit
With the method for the disclosure above and technology contents, technical solution of the present invention made many possible variations and repair
Decorations, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from technical solution of the present invention
Content, according to the technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent
Change and modification, all still fall within the range of technical solution of the present invention protection.
Claims (10)
1. the forming method of a grid, it is characterised in that including:
Gate dielectric layer is formed monolayer and the metal work function regulating course of doping, so that target work content
Number is between the work function of metal work function layer and the particle of doping；
Metal work function regulating course is formed other grid layers.
Method the most according to claim 1, it is characterised in that form the step bag of gate dielectric layer
Include:
Semiconductor substrate or fin are formed gate dielectric layer.
Method the most according to claim 1, it is characterised in that described gate dielectric layer is formed at out
On the inwall of mouth, opening is for being formed after removing pseudo-grid.
Method the most according to claim 1, it is characterised in that described metal work function regulating course
For TiN, TiTa, TiAl or Al2O3。
Method the most according to claim 4, it is characterised in that the particle of doping includes: Al,
Fe, Mg, Ni, W, C, N or H.
6. according to the method according to any one of claim 1-5, it is characterised in that at gate dielectric layer
The step of the metal work function regulating course of upper formation monolayer and doping includes: at deposit metal work function layer
While, it is passed through the gas containing doping particle, then anneals.
7. according to the method according to any one of claim 1-5, it is characterised in that at gate dielectric layer
The step of the metal work function regulating course of upper formation monolayer and doping includes:
Use atom layer deposition process, the metal work function regulating course of deposit monolayer；
Use chemical vapor deposition method, continue deposit metal work function regulating course, and be passed through containing mixing
The gas of foreign particle；
Anneal.
8. a grid, it is characterised in that including:
Gate dielectric layer；
Metal work function regulating course on gate dielectric layer, has doping particle in metal work function layer, with
Make target workfunction between the work function of metal work function layer and the particle of doping；
Other grid layers on metal work function regulating course.
Grid the most according to claim 8, it is characterised in that described metal work function regulating course
For TiN, TiTa, TiAl or Al2O3。
Grid the most according to claim 9, it is characterised in that the particle of doping includes: Al,
Fe, Mg, Ni, W, C, N or H.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510048272.3A CN105990403B (en) | 2015-01-29 | 2015-01-29 | A kind of grid and forming method thereof |
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| CN201510048272.3A CN105990403B (en) | 2015-01-29 | 2015-01-29 | A kind of grid and forming method thereof |
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| CN105990403A true CN105990403A (en) | 2016-10-05 |
| CN105990403B CN105990403B (en) | 2019-05-07 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107221513A (en) * | 2017-07-12 | 2017-09-29 | 中国科学院微电子研究所 | A kind of cmos device and its manufacture method |
| CN109148290A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor device |
| CN110870048A (en) * | 2017-08-18 | 2020-03-06 | 应用材料公司 | Method and apparatus for doping engineering and threshold voltage adjustment by integrated deposition of titanium nitride and aluminum films |
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| CN102074469A (en) * | 2009-11-25 | 2011-05-25 | 中国科学院微电子研究所 | Method for regulating metal gate work function for PMOS (P-channel Metal Oxide Semiconductor) device |
| CN102254805A (en) * | 2010-05-19 | 2011-11-23 | 中国科学院微电子研究所 | Method for adjusting work function of metal gate applied to N-channel metal oxide semiconductor (NMOS) device |
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| CN102074469A (en) * | 2009-11-25 | 2011-05-25 | 中国科学院微电子研究所 | Method for regulating metal gate work function for PMOS (P-channel Metal Oxide Semiconductor) device |
| CN102254805A (en) * | 2010-05-19 | 2011-11-23 | 中国科学院微电子研究所 | Method for adjusting work function of metal gate applied to N-channel metal oxide semiconductor (NMOS) device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148290A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor device |
| CN109148290B (en) * | 2017-06-28 | 2020-12-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN107221513A (en) * | 2017-07-12 | 2017-09-29 | 中国科学院微电子研究所 | A kind of cmos device and its manufacture method |
| CN110870048A (en) * | 2017-08-18 | 2020-03-06 | 应用材料公司 | Method and apparatus for doping engineering and threshold voltage adjustment by integrated deposition of titanium nitride and aluminum films |
| CN110870048B (en) * | 2017-08-18 | 2023-12-12 | 应用材料公司 | Method and apparatus for doping engineering and threshold voltage adjustment by integrated deposition of titanium nitride and aluminum films |
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| CN105990403B (en) | 2019-05-07 |
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