CN102386085A - Planarization method for gate-last process and device structure thereof - Google Patents
Planarization method for gate-last process and device structure thereof Download PDFInfo
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Abstract
The invention provides a flattening method and a structure for a gate-last process of an MOS (metal oxide semiconductor) device, namely, in the gate-last process processing of the MOS device, an interlayer dielectric layer is flattened by utilizing a CMP (chemical mechanical polishing) process, and a hard mask layer on a dummy gate stack layer is removed by utilizing an etching technology, so that the aims of accurately controlling the heights of a dummy gate and a metal gate are fulfilled. In addition, the MOS device of the invention forms a T-shaped gate stack, the gate length of the upper part of the T-shaped gate stack is longer than that of the lower part of the T-shaped gate stack, so that the filling space of the metal gate material in the gate trench is enlarged, and the reduction of the resistance of the metal gate is facilitated.
Description
Technical field
The present invention relates to semiconductor design and manufacturing field, particularly a kind of flattening method and device architecture thereof that is used for the back grid technique.
Background technology
Along with reducing of dimensions of semiconductor devices, especially in 22 nanometers and the following technology generation, be that the MOS device grid engineering research of core is the most representative core process with high-k gate dielectric/metal gate technique.At present; Research to high-k gate dielectric/metal gate technique can be divided into preceding grid technique (Gate first) and alternative gate or back grid technique (Replacement gate or Gate last), and a remarkable advantage of back grid technique is that grid need not bear high annealing temperature.
In the back grid technique, the planarization of grid structure is one of indispensable step, and prior art realizes through cmp (CMP, Chemical Mechanical Polish) usually.For example; At first utilize polysilicon to form false grid; Hard mask layer such as depositing nitride and/or oxide according to the integrated needs of other technologies and is above that afterwards treated other processing technologys of device, after accomplishing like grid etching, source/drain region injection, silicide preparation etc.; Deposit one deck interlayer dielectric layer (ILD) again, carry out CMP afterwards again and realize planarization.
Yet; Utilizing CMP that ILD is carried out in the planarization process, owing in the CMP equipment process of lapping is played the end point determination functional configuration of supervisory function bit, after arriving the hard mask of nitride; Be difficult to the enforcement monitoring is removed in the grinding of nitride; So generally control the grinding to nitride through the control milling time, this method often causes crossing of the false grid of polysilicon to be ground, thereby the height of the metal gate of final formation is reduced.Especially in 32nm and the following technology generation technology; The height of whole metal gate is generally below 30nm; If the control of employing time is ground; Be difficult to accurately control the height of false grid and metal gate stack, cross and grind the performance that the metal gate height that causes reduces to reduce the MOS device, so need improve traditional hard mask of the nitride based on CMP technology and false grid removal technology.In addition, in 32nm and the following technology generation, the problem that the metal gate resistance that causes owing to the metal gate dimensional effect increases also has to be solved.
Summary of the invention
The object of the invention is intended to one of solve the problems of the technologies described above at least, particularly through proposing the flattening method of a kind of back grid technique, to solve the unmanageable problem of grid height in the grid technique of back.
For achieving the above object, on the one hand, the present invention proposes a kind of flattening method that is used for the back grid technique, and may further comprise the steps: A. provides Semiconductor substrate; B. pile up and cover the hard mask layer that said false grid pile up forming false grid on the said Semiconductor substrate; C. in said Semiconductor substrate, the said false grid both sides of piling up form source/drain region; D. on said Semiconductor substrate, form interlayer dielectric layer; E. device surface is carried out cmp, to expose said hard mask layer; F. adopt etching technics to remove said hard mask layer, pile up to expose said false grid; G. removing said false grid piles up to form gate groove; H. in said gate groove, form alternative gate.
Alternatively, hard mask layer described in the step B comprises any one or more layers structure in nitride layer, oxide skin(coating), the oxynitride layer.
Preferably, before step C forms said source/drain region, be included in also that said false grid pile up and the sidewall of hard mask layer forms the step of side wall, said side wall is made up of one or more layers structure.Then step F also comprises the said hard mask layer of removal with the said side wall of expose portion, and further, step F comprises: when said side wall is one deck structure, remove said exposed portions side wall; When said side wall is multilayer, remove one or more layers exposed portions side wall.The purpose of removing the part side wall is, for after the formation of alternative gate bigger space is provided, help reducing gate resistance.
Alternatively, step H forms alternative gate and comprises in said groove: form high-k gate dielectric layer, metal gate layer and low resistive metal packed layer successively, wherein, said metal gate layer comprises individual layer or double-level-metal grid; Entire device is carried out cmp, rest on the said interlayer dielectric layer.
On the other hand, the present invention proposes a kind of semiconductor device structure that makes according to above-mentioned back grid method, comprising: Semiconductor substrate; The grid that are formed on the said Semiconductor substrate pile up; Said grid pile up and comprise top and lower part; The gate length on said top forms T type structure greater than the gate length of said lower part so that said grid pile up, and wherein the sidewall in said lower part is formed with one or more layers side wall; And pile up and the interlayer dielectric layer of said side wall around said T type grid; Source/the drain region of be formed in the said Semiconductor substrate, said grid piling up both sides.
Alternatively; The top that said T type grid pile up is formed with one or more layers side wall, needs only the side wall thicknesses sum of the side wall thicknesses sum on said top less than said lower part, and the grid that can form T type structure pile up; Thereby expansion grid space helps reducing gate resistance.
Alternatively, said T type grid pile up and comprise high-k gate dielectric layer, metal gate layer and low resistive metal packed layer.Said metal gate layer comprises individual layer or double-level-metal grid.
Flattening method and device architecture thereof behind the MOS device of the present invention in the grid technique; CMP and lithographic technique are combined; Utilize CMP technology planarization interlayer dielectric layer, utilize lithographic technique to remove the hard mask layer on the false grid stack layer, thereby realize accurately controlling the purpose of false grid and metal gate height.In addition, MOS device of the present invention has formed T type grid and has piled up, and the gate length on its top is greater than the gate length of lower part, thereby makes the metal gate material packing space in the gate groove be able to increase, and helps reducing the resistance of metal gate.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, and accompanying drawing of the present invention is schematically, does not therefore draw in proportion.Wherein:
Fig. 1-9 is the intermediate steps sketch map of the flattening method that is used for the back grid technique of the embodiment of the invention;
The semiconductor device structure figure that Figure 10-12 makes for the method according to the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
Fig. 1-9 shows the intermediate steps sketch map of the flattening method that is used for the back grid technique of the present invention's proposition, below will be described with reference to the accompanying drawings the method for optimizing of the embodiment of the invention and the device architecture that obtains thus.
Steps A. Semiconductor substrate 100 is provided, as shown in Figure 1.Substrate 100 is an example with body silicon, in the practice, can comprise any suitable semiconductor substrate materials, specifically can be but is not limited to silicon, germanium, SiGe, SOI (silicon-on-insulator), carborundum, GaAs or any III/V compound semiconductor etc.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 100 can comprise various doping configurations.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen the property.Alternatively, in Semiconductor substrate 100, form shallow trench isolation STI 101 this substrate isolation is become first area 200 and second area 300, promptly respectively as nMOS and/or pMOS active area.
Step B. forms false grid and piles up 400 and cover the hard mask layer 500 that said false grid pile up on said Semiconductor substrate 100.False grid pile up 400 and can comprise gate dielectric layer and grid layer, for example at first on Semiconductor substrate 100, form gate dielectric layer 102 and grid layer 103 successively.Wherein, gate dielectric layer 102 can adopt conventional depositing technics to form, for example sputter, PLD, MOCVD, ALD, PEALD or other suitable methods, and its material can be SiO
2, Si (O) N
x, HfO
2, HfSiO
x, HfZrO
x, HfLaO
x, LaAlO
x, Sr (O) Si
x, GeN
x, Sr (O) Ge
x, HfGeO
xIn a kind of or its combination, its thickness can be 0.3-1nm; Grid layer 103 can be amorphous silicon or polysilicon or TiN, polysilicon for example, and thickness can be 10-100nm, and is as shown in Figure 1.Need explanatorily be; Below if do not have to specify; The deposit of various dielectric materials in the embodiment of the invention (hard mask layer described as follows, side wall, interlayer dielectric layer and high-k gate dielectric layer etc.) all can be adopted above-mentioned cited formation gate dielectric layer 102 identical or similar methods, so repeat no more.
On grid layer 103, form hard mask layer then, said hard mask layer comprises any one or more layers structure in nitride layer, oxide skin(coating), the oxynitride layer, can comprise Si particularly
3N
4, TiN, SiO
2With one or more the combination among the SiON.For example; The embodiment of the invention is taked first silicon oxide layer 104 of deposit successively, silicon nitride layer 105 and second silicon oxide layer 106, and wherein, the thickness of first silicon oxide layer 104 and second silicon oxide layer 106 can be 5-30nm; The thickness of silicon nitride layer 105 is 10-70nm, and is as shown in Figure 2.
Utilize dry method and/or wet-etching technology that first area 200 and second area 300 are carried out etching then, pile up 400 and cover hard mask layer 500 above that to form false grid, as shown in Figure 3.Wherein, false grid pile up 400 and comprise gate dielectric layer 102 and grid layer 103, and hard mask layer 500 comprises first silicon oxide layer 104 and silicon nitride layer 105.Need be with pointing out; Because second silicon oxide layer 106 is very thin; So in the cleaning process after grid pile up etching; This silicon dioxide layer may involved HF cleaning fluid etch away fully or only keep very thin one deck, so second silicon oxide layer 106 is not shown among Fig. 3, previous second silicon oxide layer 106 that forms can play the effect of protection to aspects such as the height of the hard mask layer under it and stress.
Preferably, form false grid pile up 400 with hard mask layer 500 after, can false grid pile up 400 and the sidewall of hard mask layer 500 form side wall 107, side wall 107 comprises one or more layers structure, and is as shown in Figure 4.Side wall 107 can be by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low k or high-k dielectric material and combination thereof, and/or other suitable materials form; The shape of side wall can for common, only be formed on false grid and pile up 400 and the sidewall of hard mask layer 500, also can comprise L type side wall, the present invention does not limit this.The embodiment of the invention is the example explanation with the side wall of three-decker, and wherein, ground floor side wall 107-1 can be silicon nitride, and thickness is 5-15nm; Second layer side wall 107-2 can be silica, can be the L type, and thickness is 2-10nm; The 3rd layer of side wall 107-3 can be silicon nitride, and thickness is 5-15nm.Wherein, the material of ground floor side wall is preferably and hard mask layer 500 identical materials, like silicon nitride, so that when follow-up removal hard mask layer, remove the ground floor side wall in the lump.
Step C. in said Semiconductor substrate 100, said false grid pile up 400 both sides and form source/drain region 600, and are as shown in Figure 5.For example, can through comprise that photoetching, ion are injected, diffusion, annealing and/or other appropriate process form source/drain extension region and source/drain regions, for example 200 carry out respectively with second area 300 that n type source/leakages injected and p type source/leakage injection in the first area.Alternatively, on source/drain region, form metal silicide 108, for example; Form metal silicide through autoregistration, earlier deposit metallic material, for example Co, Ni, Mo, Pt and W etc. on said device; Then anneal; The surface of silicon substrate reaction at metal and 600 places, said source/drain region generates metal silicide, removes unreacted metal then, forms self aligned metal silicide.
Step D. forms interlayer dielectric layer 109 on said Semiconductor substrate, as shown in Figure 5, interlayer dielectric layer 109 covers the device architecture of substrate surface fully.The material of interlayer dielectric layer can comprise the silica (like fluorine silex glass, Pyrex, phosphorosilicate glass, boron-phosphorosilicate glass) of silica, doping, a kind of or its combination in the low K dielectrics material (like porous silicon, black diamond, coral etc.), and present embodiment is example with the silica.
Step e. device surface is carried out cmp (CMP), to expose said hard mask layer 500, as shown in Figure 6.Be with noting, do not need this moment CMP equipment that the nitride in the hard mask layer 500 is implemented accurately monitoring, be removed as long as can monitor out interlayer dielectric layer 109 (silica), promptly the surface with hard mask layer 500 is the stop surface.
Step F. adopt etching technics to remove said hard mask layer 500, pile up 400 to expose said false grid, as shown in Figure 7.Particularly, can adopt dry method or wet method that silicon nitride layer 105 is carried out etching, alternatively, available dry etching falls first silicon oxide layer 104 under it; Perhaps after etching away silicon nitride layer 105, clean and remove simultaneously first silicon oxide layer 104.Owing to adopted dry method or wet etching technique but not the CMP technology is removed hard mask layer, the thickness that the height of final grid structure can be through the false grid of control and on thickness and the accurately control of hard mask layer.
If formed side wall 107 among the step B; Alternatively, this step can also be removed exposed portions ground floor side wall 107-1 except that etching away hard mask layer 500; The part with hard mask layer 500 height such as grade that is ground floor side wall 107-1 is removed; Thereby for alternative gate afterwards forms bigger space is provided, has helped reducing gate resistance, as shown in Figure 7.Certainly, alternatively, when etching away hard mask layer 500, can remove exposed portions ground floor side wall 107-1 and second layer side wall 107-2, promptly the part with hard mask layer 500 height such as grade of ground floor side wall 107-1 and second layer side wall 107-2 is removed respectively.In like manner alternatively; When etching away hard mask layer 500; Can remove exposed portions ground floor side wall 107-1, second layer side wall 107-2 and the 3rd layer of side wall 107-3, promptly the part with hard mask layer 500 height such as grade of ground floor side wall 107-1, second layer side wall 107-2 and the 3rd layer of side wall 107-3 is removed respectively.The method of removing side wall can be dry method or wet etching.The material of ground floor side wall 107-1 is a silicon nitride in the present embodiment, so can preferably carry out in the lump with the etching of silicon nitride hard mask layer 500.Need be, the purpose of removing the part side wall be to expand the packing space of gate groove with pointing out, therefore is not limited to remove the full-thickness of certain layer of side wall; That is to say; Even this layer side wall only segment thickness is removed,, also be feasible as long as can satisfy actual needs.
Step G. removes said false grid and piles up 400 to form gate groove 110, and is as shown in Figure 8.Particularly, can utilize dry method or wet-etching technology to remove the polysilicon gate layer 103 in the present embodiment, can remove the gate dielectric layer 102 under it in the lump, but preferably, keep gate dielectric layer.Owing to preferably remove the part of ground floor side wall 107-1 in the step F, step forms T type gate groove 110.
Step H. forms alternative gate 700 in said gate groove 110.The method that forms alternative gate can adopt any known method in this area.Present embodiment illustrates the method that a preferred high-k gate dielectric-metal gate-low resistive metal multilayer is filled, and is as shown in Figure 9.Particularly, in gate groove 110, form high-k gate dielectric layer 111, metal gate layer 112 and low resistive metal packed layer 113 successively.Wherein, high-k gate dielectric material comprises for example hafnium sill, like hafnium oxide (HfO
2), a kind of or its combination and/or other suitable material of hafnium silicon oxide (HfSiO), nitrogen hafnium silicon oxide (HfSiON), hafnium oxide tantalum (HfTaO), lanthana hafnium (HfLaO), hafnium oxide titanium (HfTiO), hafnium oxide zirconium (HfZrO), like lanthana aluminium (LaAlO), gadolinium oxide (Gd
2O
3) etc.; Metal gate material comprises like a kind of or its combination among Ti, Co, Ni, Al, W, Ru, TiN, TiC, HfN, HfC, TaN, TaC, MoN, the TiAlN and/or other suitable material; Low resistive metal comprises like Ti, Al, Cu, TiAl
xWith a kind of of W and/or material that other is suitable.The deposit of high-k gate dielectric material can be adopted the deposition process of aforementioned dielectric material; The formation of metal gate and low-resistance metal material can be adopted (the Physical Vapor Deposition (physical vapor deposition) like PVD; Comprise evaporation, sputter, electron beam etc.), CVD (Chemical Vapor Deposition, chemical vapor deposition), electroplate or other suitable methods.
Preferably; Adopt metal gate layer 112 can be the bimetal gate layer; For example, can be in the gate groove 110 of second area 300 deposit pMOS metal gate 112B, deposit nMOS metal gate 112A and pMOS metal gate 112B respectively in the gate groove of first area 200; To form bimetal gate layer structure, as shown in Figure 9.
Then entire device is carried out planarization,, and rest on the interlayer dielectric layer 109 like CMP.So far just obtained the semiconductor device structure of the embodiment of the invention, shown in figure 10.This device architecture comprises: Semiconductor substrate 100, the grid that are formed on the substrate 100 pile up 700, pile up 700 interlayer dielectric layer 109 around said grid, and be formed in the Semiconductor substrate 100, source/drain region 600 that grid pile up 700 both sides.Wherein, comprise metal silicide 108 on source/drain region; Grid pile up 700 T type structures preferably; Grid pile up 700 sidewall and are formed with one or more layers side wall; Be example (ground floor side wall 107-1, second layer side wall 107-2 and the 3rd layer of side wall 107-3) with three layers among the figure; Wherein the top of ground floor side wall 107-1 is lower than the top of second layer side wall 107-2 and the 3rd layer of side wall 107-3, and the top of second layer side wall 107-2 and the 3rd layer of side wall 107-3 and grid pile up 700 top and flush basically, constitute T type structures thereby make grid pile up 700.Alternatively, be formed with shallow trench isolation STI 101 in the Semiconductor substrate 100, this substrate isolation is become first area 200 and second area 300.Preferably; Grid pile up 700 and comprise high-k gate dielectric layer 111, metal gate layer 112 and low resistive metal packed layer 113; Wherein, metal gate layer 112 can use the bimetal gate layer to replace, for example as shown in Figure 10; The grid of first area 200 pile up 700 and comprise nMOS metal gate 112A and pMOS metal gate 112B, and the grid of second area 300 pile up 700 and comprise pMOS metal gate 112B.
In step F, if remove the expose portion of ground floor side wall 107-1 and second layer side wall 107-2 simultaneously, then final structure chart is shown in figure 11.Compare with structure shown in Figure 10, the difference of structure shown in Figure 11 only is that the top of ground floor side wall 107-1 and second layer side wall 107-2 is lower than the top of the 3rd layer of side wall 107-3, thereby has bigger gate groove space, can further reduce gate resistance.
In step F, if remove the expose portion of ground floor side wall 107-1, second layer side wall 107-2 and the 3rd layer of side wall 107-3 simultaneously, then final structure chart is shown in figure 12.And compare with structure shown in Figure 11 with Figure 10; The difference of structure shown in Figure 12 only is; The top of ground floor side wall 107-1, second layer side wall 107-2 and the 3rd layer of side wall 107-3 all is lower than grid and piles up 700 top; So have the gate groove space bigger, can further reduce gate resistance than structure shown in Figure 11.
Need be with pointing out, more than the side wall number of plies of cited semiconductor device structure be not used for limiting the present invention, any semiconductor device structure with same or similar design philosophy all is included within the protection range of the present invention.
The present invention proposes the flattening method and the structure thereof of grid technique behind a kind of MOS of being used for device; Promptly in the back grid technique processing of MOS device; Utilize CMP technology planarization interlayer dielectric layer; Utilize lithographic technique to remove the hard mask layer on the false grid stack layer, thereby realize accurately controlling the purpose of false grid and metal gate height.In addition, MOS device of the present invention has formed T type grid and has piled up, and the gate length on its top is greater than the gate length of lower part, thereby makes the metal gate material packing space in the gate groove be able to increase, and helps reducing the resistance of metal gate.
Although illustrated and described embodiments of the invention; For those of ordinary skill in the art; Be appreciated that under the situation that does not break away from principle of the present invention and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present invention is accompanying claims and be equal to and limit to these embodiment.
Claims (10)
1. one kind is used for the flattening method of grid technique afterwards, may further comprise the steps:
A., Semiconductor substrate is provided;
B. pile up and cover the hard mask layer that said false grid pile up forming false grid on the said Semiconductor substrate;
C. in said Semiconductor substrate, the said false grid both sides of piling up form source/drain region;
D. on said Semiconductor substrate, form interlayer dielectric layer;
E. device surface is carried out cmp, to expose said hard mask layer;
F. adopt etching technics to remove said hard mask layer, pile up to expose said false grid;
G. adopting etching technics to remove said false grid piles up to form gate groove;
H. in said gate groove, form alternative gate.
2. the method for claim 1 is characterized in that, hard mask layer described in the said step B comprises any one or more layers structure in nitride layer, oxide skin(coating), the oxynitride layer.
3. the method for claim 1 is characterized in that, before said step C, is included in also that said false grid pile up and the sidewall of hard mask layer forms the step of side wall, and said side wall is made up of one or more layers structure.
4. method as claimed in claim 3 is characterized in that, said step F comprises: remove said hard mask layer with the said side wall of expose portion.
5. method as claimed in claim 4 is characterized in that, said step F further comprises:
When said side wall is one deck, remove said exposed portions side wall;
When said side wall is multilayer, remove one or more layers exposed portions side wall.
6. the method for claim 1 is characterized in that, said step H comprises:
In said gate groove, form high-k gate dielectric layer, metal gate layer and low resistive metal packed layer, wherein, said metal gate layer comprises individual layer or double-level-metal grid;
Entire device is carried out cmp, rest on the said interlayer dielectric layer.
7. one kind is passed through the semiconductor device structure that the back grid technique forms, and comprising:
Semiconductor substrate;
The grid that are formed on the said Semiconductor substrate pile up; Said grid pile up and comprise top and lower part; The gate length on said top forms T type structure greater than the gate length of said lower part so that said grid pile up, and wherein the sidewall in said lower part is formed with one or more layers side wall; And
Pile up and the interlayer dielectric layer of said side wall around said T type grid;
Source/the drain region of be formed in the said Semiconductor substrate, said grid piling up both sides.
8. device architecture as claimed in claim 7 is characterized in that, the sidewall on the top that said T type grid pile up is formed with one or more layers side wall.
9. device architecture as claimed in claim 7 is characterized in that, said T type grid pile up and comprise high-k gate dielectric layer, metal gate layer and low resistive metal packed layer.
10. device architecture as claimed in claim 9 is characterized in that, said metal gate layer comprises individual layer or double-level-metal grid.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137489A (en) * | 2011-12-02 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1296639A (en) * | 1998-09-28 | 2001-05-23 | 皇家菲利浦电子有限公司 | Method of manufacturing semiconductor device with field effect transistor |
| CN1405894A (en) * | 2001-08-04 | 2003-03-26 | 三星电子株式会社 | Semiconductor device structure and its producing method |
| US20100112798A1 (en) * | 2008-11-03 | 2010-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for gap filling in a gate last process |
-
2010
- 2010-09-06 CN CN201010274285XA patent/CN102386085A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1296639A (en) * | 1998-09-28 | 2001-05-23 | 皇家菲利浦电子有限公司 | Method of manufacturing semiconductor device with field effect transistor |
| CN1405894A (en) * | 2001-08-04 | 2003-03-26 | 三星电子株式会社 | Semiconductor device structure and its producing method |
| US20100112798A1 (en) * | 2008-11-03 | 2010-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for gap filling in a gate last process |
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| CN103594420B (en) * | 2012-08-17 | 2017-12-12 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| WO2014040213A1 (en) * | 2012-09-12 | 2014-03-20 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| US9331172B2 (en) | 2012-09-12 | 2016-05-03 | Institute of Microelectronics, Chinese Academy of Sciences | Method for making HKMG dummy gate structure with amorphous/ONO masking structure and procedure |
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