CN103165447B - Fin formula field effect transistor and preparation method thereof - Google Patents
Fin formula field effect transistor and preparation method thereof Download PDFInfo
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- CN103165447B CN103165447B CN201110406764.7A CN201110406764A CN103165447B CN 103165447 B CN103165447 B CN 103165447B CN 201110406764 A CN201110406764 A CN 201110406764A CN 103165447 B CN103165447 B CN 103165447B
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Abstract
The present invention provides a kind of fin formula field effect transistor and preparation method thereof, and the method includes: form fin on a semiconductor substrate；Forming dummy gate in the Semiconductor substrate be formed with fin, it is across fin；Form the first side wall in the both sides of dummy gate, fin is carried out ion implanting, to form the source electrode of fin formula field effect transistor, drain electrode；Remove dummy gate, form opening in the position of dummy gate, be sequentially depositing high-K gate dielectric layer, metal gate material layer to fill opening, formation metal gates；Remove the high-K gate dielectric layer on the first side wall and metal gates sidewall successively.In the fin formula field effect transistor of the present invention, the high-K gate dielectric layer of metal gates both sides is removed efficiently, avoid generation parasitic capacitance between metal gates and source/drain, and other semiconductor structure will not be caused damage during removing, make the fin formula field effect transistor of formation have good electric property.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of fin formula field effect transistor and
Its manufacture method.
Background technology
Since semiconductor integrated circuit develops, its performance steadily improves always.The raising of performance is mainly
By constantly reducing what the size of semiconductor element in integrated circuit realized.Wherein, CMOS transistor
It it is a kind of vital semiconductor element.Along with the development of semiconductor technology, the spy of CMOS transistor
Levy size and narrow down to 45 nanometer nodes.But below 45 nanometer nodes, traditional plane CMOS
Technology is difficult to development further, and new technology must produce in good time.In the various technology proposed, many
Gate transistor technology is considered as the technology being hopeful most can be applied after sub-45 nanometer nodes.With biography
The single gate transistor of system is compared, and multiple-gate transistor has higher short channel rejection ability, more preferable subthreshold spy
Property, higher driving force and higher current densities can be brought.
At present, fin formula field effect transistor (FinFET) because of its self-alignment structure can be by conventional plane
CMOS technology realizes, thus becomes the multiple-gate transistor being hopeful most to be used widely.It was both
Can be formed on body silicon (Bulk Silicon) substrate, it is also possible to silicon (Silicon On on insulator
Insulator, SOI) formed on substrate.It addition, the grid of fin formula field effect transistor both can be by polysilicon
Also can be formed by grid materials such as metals.Fin formula field effect transistor structurally can be divided into double grid fin field
Effect transistor and three grid fin formula field effect transistors.A kind of double grid fin field effect crystal in prior art
The manufacture method of pipe is as follows:
As shown in Figure 1A, it is provided that Semiconductor substrate 1, Semiconductor substrate 1 is body silicon substrate.At quasiconductor
Sequentially forming pad oxide 2, hard mask layer 3 on substrate 1, hard mask layer 3 is in subsequent chemical-mechanical polishing
(CMP) can serve as polish stop during, its material can be silicon nitride.Then at hard mask layer 3
Upper formation photoresist layer 4, is exposed photoresist layer 4, develops, and forms graphical photoresist.Successively
To not being patterned immediately hard mask layer 3 that photoresist layer 4 covers, pad oxide 2, Semiconductor substrate 1 are entered
Row etching, at least forms two grooves 5 in Semiconductor substrate 1.Therefore, half between adjacent trenches 5
Conductor substrate 1 protrudes (protruding upward along the direction being perpendicular to semiconductor substrate surface 1a), and convex
This part semiconductor substrate gone out constitutes the fin 6 of fin formula field effect transistor.It follows that serve as a contrast at quasiconductor
The purpose of groove 5 is formed in order to form fin formula field effect transistor on semiconductor substrate 1 at the end 1
Fin 6.
As shown in Figure 1B, remove photoresist layer 4, the Semiconductor substrate 1 be formed with groove 5 deposits
Insulation material layer is so that groove 5 is filled by it.Insulation material layer can be silicon oxide.Utilize chemical machinery
Insulation material layer is processed by shot blasting by glossing until hard mask layer 3 exposes.Remove hard mask successively
Layer 3, pad oxide 2, form fleet plough groove isolation structure 8 on semiconductor substrate 1.Shallow trench isolation junction
Structure 8 top 8a is higher than Semiconductor substrate 1 surface 1a.
As shown in Figure 1 C, fleet plough groove isolation structure 8 is performed etching, make the shallow trench isolation junction after etching
Structure 8 ' top 8a ' is less than the fin between Semiconductor substrate 1 surface 1a, i.e. adjacent shallow trench isolation structure 8 '
The fin 6 of field-effect transistor is higher than fleet plough groove isolation structure 8 ' top 8a ', and comes out.In follow-up work
This part fin 6 come out in skill can be used for forming the source electrode of fin formula field effect transistor, drain electrode, ditch
Road.Fig. 3 A is the top view of Fig. 1 C, in conjunction with Fig. 1 C, Fig. 3 A, it can be seen that fin 6 is along being parallel to half
The first direction A-A of conductor substrate surface 1a extends.
In order to enable to obtain the higher height of quality between the grid and Semiconductor substrate of fin formula field effect transistor
K gate dielectric layer, available post tensioned unbonded prestressed concrete technique (gate-last approach) forms fin formula field effect transistor
Grid and high-K gate dielectric layer.The ultimate principle of post tensioned unbonded prestressed concrete technique is: sink the most on a semiconductor substrate
Long-pending polysilicon layer, forms graphical photoresist on the polysilicon layer, covers not being patterned immediately photoresist
Polysilicon layer perform etching, to form dummy gate；Side wall is formed in the both sides of dummy gate；Remove
Dummy gate, after dummy gate is removed, the position at place forms opening；Be sequentially depositing high-K gate dielectric layer,
Metal gate material layer is to fill described opening；Utilize CMP process to metal gate material layer,
High-K gate dielectric layer carries out planarization process, thus can form metal gates.Utilize post tensioned unbonded prestressed concrete technique
The manufacture method forming fin formula field effect transistor grid and high-K gate dielectric layer is as follows:
In conjunction with Fig. 2 A, Fig. 1 D (Fig. 1 D is Fig. 2 A sectional view along another cross section) and Fig. 3 B
Shown in the top view of Fig. 2 A (Fig. 3 B be), it is being formed with the Semiconductor substrate of fleet plough groove isolation structure 8 '
Depositing dummy gate material layer on 1, such as polysilicon layer, dummy gate material layer covers at fin 6 and shallow trench
Isolation structure 8 ' top.Dummy gate material layer forms graphical photoresist layer, then to virtual grid
Pole material layer performs etching, to form dummy gate 9.Dummy gate 9 is along being parallel to Semiconductor substrate table
Second direction B-B (second direction B-B is different from first direction A-A) of face 1a extends, and across
The fin 6 of fin formula field effect transistor, i.e. its part (two end portions up and down of fin 6 in Fig. 3 B)
It is positioned at the both sides of fin 6 and is positioned at fleet plough groove isolation structure 8 ' top, a part (centre of fin 6 in Fig. 3 B
Part) it is positioned at above fin 6.Fin 6 surrounded by dummy gate 9 part (in Fig. 3 B two dotted lines it
Between part) in order to form the raceway groove 10 of fin formula field effect transistor.
As shown in Figure 2 B, the sidewall (left and right two vertical sidewall) at dummy gate 9 forms side wall 11.So
Afterwards the subregion of fin 6 is carried out ion implanting, to form the source of fin formula field effect transistor in fin 6
Pole/drain electrode 16.
As shown in Figure 2 C, deposition interlayer it is formed with in the Semiconductor substrate 1 of side wall 11 at dummy gate 9
Dielectric layer 12.Utilize CMP process that interlayer dielectric layer 12 is processed by shot blasting until virtual grid
Pole 9 is exposed.Remove dummy gate 9, form opening 13 in dummy gate 9 position.
As shown in Figure 2 D, the Semiconductor substrate 1 after dummy gate 9 is removed is sequentially depositing high K grid
Dielectric layer 14, metal gate material layer 15, to fill opening 13, utilize CMP process to gold
Belong to gate material layers 15, high-K gate dielectric layer 14 is processed by shot blasting until interlayer dielectric layer 12 exposes,
Form metal gates 15.So far, fin formula field effect transistor completes.But send out in actual applications
Existing, utilize in the fin formula field effect transistor that above-mentioned manufacture method formed between metal gates and source/drain
There is bigger parasitic capacitance, had a strong impact on the electric property of fin formula field effect transistor.
Summary of the invention
The problem to be solved in the present invention is: in fin formula field effect transistor between metal gates and source/drain
There is bigger parasitic capacitance, had a strong impact on the electric property of fin formula field effect transistor.
For solving this problem, the invention provides the manufacture method of a kind of fin formula field effect transistor, institute
State manufacture method to comprise the following steps:
Thering is provided Semiconductor substrate, form fin on the semiconductor substrate, described fin is partly led along being parallel to
The first direction of body substrate surface extends；
Forming dummy gate in the described Semiconductor substrate being formed with fin, described dummy gate is along parallel
Second direction in semiconductor substrate surface extends, and across described fin；
Form the first side wall in the both sides of described dummy gate, fin is carried out ion implanting, described to be formed
The source electrode of fin formula field effect transistor, drain electrode；
Remove described dummy gate, form opening in the position of described dummy gate, be sequentially depositing high K
Gate dielectric layer, metal gate material layer, to fill described opening, form metal gates；
Remove described first side wall, and the high-K gate dielectric layer on metal gates sidewall successively.
Optionally, the both sides at described dummy gate form the first side wall and described fin are carried out ion implanting
Afterwards, the second side wall, described second side wall, the material of the first side wall are formed in the both sides of described dummy gate
Matter differs, and the most described fin is carried out ion implanting.
Optionally, the described ion implanting that carries out fin is low concentration ion implanting, described again carries out fin
Ion implanting is intermediate concentration or high concentration ion injection.
Optionally, the material of described first side wall is porous material.
Optionally, the material of described first side wall is amorphous carbon.
Optionally, the minimizing technology of described first side wall is that ashing processes, and its etching gas used includes
O2、CO2、N2、H2、NH3、CH4In at least one.
Optionally, described Semiconductor substrate is body silicon substrate, forms the step of fin on the semiconductor substrate
Suddenly include: in described Semiconductor substrate, form groove, the quasiconductor of the protrusion between adjacent described groove
Substrate constitutes described fin.
Optionally, the step forming dummy gate in the described Semiconductor substrate being formed with fin includes:
Filling material in described groove is the insulation material layer of silicon oxide, to form fleet plough groove isolation structure,
Then fleet plough groove isolation structure is performed etching, make the top of described fleet plough groove isolation structure less than described half
The surface of conductor substrate；
Deposition dummy gate material layer, forms graphical photoresist on described dummy gate material layer, right
Dummy gate material layer covered by photoresist is not had to perform etching, to form dummy gate, described virtual
A part for grid is positioned at above the fleet plough groove isolation structure of fin both sides, and a part is positioned at the top of described fin.
Optionally, described Semiconductor substrate is silicon-on-insulator substrate, comprising: the substrate stacked gradually,
Material is the buried oxide layer of silicon oxide, silicon layer, and the step forming fin on the semiconductor substrate includes:
Form graphical photoresist layer on the semiconductor substrate, the silicon layer not being photo-etched glue-line covering is entered
Row etching, forms described fin.
Optionally, the step forming dummy gate in the described Semiconductor substrate being formed with fin includes:
The Semiconductor substrate be formed with fin deposits dummy gate material layer, at described dummy gate material
Graphical photoresist is formed on layer, to not having dummy gate material layer covered by photoresist to perform etching,
To form dummy gate, above the buried oxide layer of the both sides that a part for described dummy gate is positioned at fin,
A part is positioned at the top of fin.
Optionally, the minimizing technology of the high-K gate dielectric layer on described metal gates sidewall is wet etching,
Its etching agent used to the etch rate of high-K gate dielectric layer more than being pointed to below high-K gate dielectric layer
The etch rate of fleet plough groove isolation structure.
Optionally, the minimizing technology of the high-K gate dielectric layer on described metal gates sidewall is wet etching,
Its etching agent used to the etch rate of high-K gate dielectric layer more than being pointed to below high-K gate dielectric layer
The etch rate of silicon layer.
Optionally, described etching agent is absolute alcohol.
Optionally, the thickness of described first side wall is 5nm～10nm.
Accordingly, the present invention also provides for a kind of fin formula field effect transistor, comprising:
Form fin on a semiconductor substrate；
High-K gate dielectric layer, a part for high-K gate dielectric layer is positioned at the both sides of described fin, and a part is positioned at
The top of described fin；
Being formed at the metal gates above high-K gate dielectric layer, the both sides of described metal gates are formed with interlayer
, between described interlayer dielectric layer and the sidewall of metal gates, there is gap in dielectric layer.
Optionally, between the sidewall of described interlayer dielectric layer and described metal gates, it is formed with the second side wall,
Gap is there is between described second side wall and the sidewall of described metal gates.
Optionally, the width in described gap is 5nm～10nm.
Compared with prior art, the invention have the advantages that
In fin formula field effect transistor, the high-K gate dielectric layer on metal gates two side is removed efficiently, and keeps away
Exempt to produce between metal gates and source/drain parasitic capacitance, and will not be to fin during removing
Other semiconductor structure in field-effect transistor causes damage, and makes the fin formula field effect transistor of formation have
There is good electric property.
Accompanying drawing explanation
In order to enable clearer explanation the technical problem to be solved in the present invention and technical scheme, attached
Figure have employed multiple view simultaneously (along the vertical view corresponding to the sectional view of varying cross-section and sectional view
Figure) illustrate with the structure to fin formula field effect transistor.
Figure 1A to Fig. 1 D be existing a kind of fin formula field effect transistor manufacture method in fin field effect brilliant
Body pipe is along the sectional view of a cross section.
Fig. 2 A to 2D be existing a kind of fin formula field effect transistor manufacture method in fin field effect crystal
Pipe along the sectional view of another cross section, another cross section described here and above-mentioned Figure 1A to Fig. 1 D
Described in a cross section be mutually perpendicular to.
Fig. 3 A is the top view of Fig. 1 C, and Fig. 3 B is Fig. 2 A top view.
Fig. 4 be the manufacture method of the fin formula field effect transistor of the present invention embodiment in fin field effect brilliant
The Making programme figure of body pipe.
Fig. 5 A to Fig. 5 E be the fin formula field effect transistor manufacture method of the present invention an embodiment in fin
Formula field-effect transistor is along the sectional view of a cross section.
Fig. 6 A to Fig. 6 F be the fin formula field effect transistor manufacture method of the present invention an embodiment in fin
Formula field-effect transistor is along the sectional view of another cross section, and another cross section described here is with above-mentioned
Described in Fig. 5 A to Fig. 5 E a cross section is mutually perpendicular to.
Fig. 7 A is the top view of Fig. 5 D, and Fig. 7 B is the top view of Fig. 6 A.
Fig. 8 A to Fig. 8 C is in another embodiment of the fin formula field effect transistor manufacture method of the present invention
Fin formula field effect transistor is along the sectional view of a cross section.
Fig. 9 be the fin formula field effect transistor manufacture method of the present invention another embodiment in fin field effect
Answering transistor along the sectional view of another cross section, another cross section described here and Fig. 8 A are to figure
Described in 8C a cross section is mutually perpendicular to.
Figure 10 A is the top view of Fig. 8 B, and Figure 10 B is the top view of 9.
Detailed description of the invention
As described in the background art, the metal gates of fin formula field effect transistor and source/drain in prior art
There is between pole bigger parasitic capacitance, had a strong impact on the electric property of fin formula field effect transistor.Send out
A person of good sense learns by analysis, and the reason producing this phenomenon is: as shown in Figure 2 D, utilizes post tensioned unbonded prestressed concrete technique
When forming the metal gates 15 of fin formula field effect transistor, although the higher high-K gate dielectric of quality can be formed
Layer 14, but while deposition high-K gate dielectric layer 14, metal gates 15 two side (Fig. 2 D can be caused
Middle left and right vertical sides wall) it is attached with high-K gate dielectric layer 14, high-K gate dielectric layer 14 is that a kind of dielectric is normal
The material that number is the biggest, in this fin formula field effect transistor structure, metal gates 15, source/drain 16
And high-K gate dielectric layer 14 can produce the parasitic capacitance that capacitance is bigger.
For solving the problems referred to above, the invention provides a kind of fin formula field effect transistor and preparation method thereof,
As shown in Figure 4, described manufacture method includes following Making programme:
S1., Semiconductor substrate is provided, forms the fin of fin formula field effect transistor, fin edge on a semiconductor substrate
The first direction extension being parallel to semiconductor substrate surface.
S2. forming dummy gate in the Semiconductor substrate be formed with fin, dummy gate is partly led along being parallel to
The second direction of body substrate surface extends, and across fin.
S3. the both sides at dummy gate form the first side wall, fin carry out ion implanting to form fin field effect
Answer the source/drain of transistor.
S4. form interlayer dielectric layer, remove dummy gate, to form opening in dummy gate position.
S5. it is sequentially depositing high-K gate dielectric layer, metal gate material layer to fill opening, removes inter-level dielectric
Metal gate material layer on Ceng, high-K gate dielectric layer, form metal gates.
Remove the high-K gate dielectric layer on the first side wall, and metal gates sidewall the most successively.
Below in conjunction with the accompanying drawings, by specific embodiment, technical scheme is carried out clear, complete
Description, it is clear that described embodiment is only a part for the embodiment of the present invention, and not
It is that they are whole.According to these embodiments, those of ordinary skill in the art is before without creative work
Put obtainable other embodiments all, broadly fall into protection scope of the present invention.
It should be noted that, in order to enable clearer explanation technical scheme, embodiments of the invention
Accompanying drawing have employed multiple view simultaneously (along bowing corresponding to the sectional view of varying cross-section and sectional view
View) illustrate with the structure to fin formula field effect transistor.Should be by multiple accompanying drawings when understanding the present invention
It is combined to understand.
Step S1 is first carried out: Semiconductor substrate is provided, forms fin field effect on a semiconductor substrate brilliant
The fin of body pipe, fin extends along the first direction being parallel to semiconductor substrate surface.
As shown in Figure 5A, it is provided that Semiconductor substrate 100, Semiconductor substrate 100 can be body silicon substrate,
Can also be silicon-on-insulator substrate (Silicon On Insulator, SOI).In the present embodiment, partly lead
Body substrate 100 is body silicon substrate.Sequentially form pad oxide 101, hard mask on a semiconductor substrate 100
Layer 102, photoresist layer 103.Pad oxide 101 can be silicon oxide, and hard mask layer 102 can be nitrogen
SiClx.It is special that pad oxide 101 can strengthen the interface between hard mask layer 102 and Semiconductor substrate 100
Property, it can utilize thermal oxide growth technique, chemical gaseous phase to deposit (CVD) technique, ald
Methods such as (Atomic Layer Deposition, ALD) is formed.Hard mask layer 102 is in subsequent technique
Can be used as polish stop, it can utilize chemical gaseous phase to deposit (CVD) technique, ald
Methods such as (Atomic Layer Deposition, ALD) is formed.
Photoresist layer 103 is exposed, is developed to graphical photoresist, on graphical photoresist
It is formed with opening.It is pointed to the hard mask layer 102 below opening, pad oxide 101, quasiconductor lining successively
The end 100, performs etching at least to form groove 105 in Semiconductor substrate 100.So, adjacent trenches
Semiconductor substrate 100 between 105 is protruded (convex along the direction being perpendicular to semiconductor substrate surface 100a
Go out), this part semiconductor substrate of protrusion constitutes the fin 106 of fin formula field effect transistor.Fin 106 can be used
In forming the source electrode of fin formula field effect transistor, drain electrode, raceway groove.
From the foregoing, when fin formula field effect transistor is to make formation on body silicon substrate, fin field
The fin of effect transistor is to utilize shallow trench isolation (Shallow Trench Isolation) technique definition to be formed.
Then step S2 is performed: in the Semiconductor substrate be formed with fin, form dummy gate, dummy gate
Extend along the second direction being parallel to semiconductor substrate surface, and across fin.
As shown in Figure 5 B, photoresist layer 103 is removed.It is being formed with the Semiconductor substrate 100 of groove 105
Upper deposition of insulative material layer 107, to fill groove 105.Insulation material layer 107 can be but not limited to oxygen
SiClx, its forming method can be chemical gaseous phase deposition (Chemical Vapor Deposition, CVD) or
Thermal oxide growth technique.As, silicon oxide can utilize TEOS (tetraethyl orthosilicate) and pass through chemical gaseous phase
Depositing operation is formed.Before deposition of insulative material layer 107, can be at groove 105 deposited on sidewalls liner
Oxide layer, with the interfacial characteristics between reinforced insulation material layer 107 and Semiconductor substrate 100.Liner oxygen
Change layer and can be but not limited to silicon oxide.Utilize CMP process to remove and be positioned at hard mask layer 102
The insulation material layer 107 of top, until hard mask layer 102 exposes.Insulation material layer 107 is being changed
Learning in mechanical polishing process, hard mask layer 102 is used as polish stop.
As shown in Figure 5 C, remove hard mask layer 102, pad oxide 101 successively, form shallow trench isolation
Structure 107, fleet plough groove isolation structure 107 top 107a is higher than Semiconductor substrate 100 surface 100a.
Shown in Fig. 5 D, Fig. 7 A top view of Fig. 5 D (Fig. 7 A be), remove part shallow trench every
From structure 107, make fleet plough groove isolation structure 107 ' the top 107a ' after removal processes less than quasiconductor
Substrate 100 surface 100a.That is, the part fin 106 between adjacent shallow trench isolation structure 107 ' exposes
Come.Fleet plough groove isolation structure 107 is performed etching by technique can to utilize eat-back (etch back), until portion
Fin 106 is divided to come out.The fin 106 come out can be used for forming fin field effect after subsequent treatment
Answer the source electrode of transistor, drain electrode, raceway groove.As shown in Figure 7 A, fin 106 is along being parallel to Semiconductor substrate
The first direction A-A of surface 100a extends.
In conjunction with Fig. 6 A, Fig. 5 E (Fig. 5 E is Fig. 6 A sectional view along another cross section) and Fig. 7 B (figure
7B is the top view of Fig. 6 A) shown in, it is removed in fleet plough groove isolation structure 107 part, part fin 106
After coming out, deposition dummy gate material layer on a semiconductor substrate 100, dummy gate material layer
Material can be polysilicon.Dummy gate material layer forms graphical photoresist, to not being patterned immediately
The dummy gate material layer that photoresist covers performs etching, to form dummy gate 111.Dummy gate 111
Along second direction B-B (second direction B-B and the present embodiment of being parallel to semiconductor substrate surface 100a
In the first direction A-A that mentions different) extend, and across the fin 106 of fin formula field effect transistor.
That is, a part (two end portions of dummy gate 111) for dummy gate 111 is positioned at the both sides (figure of fin 106
Upper and lower both sides in 7B), specifically, it is in fleet plough groove isolation structure 107 ' upper of fin 106 both sides
Side, a part (mid portion of dummy gate 111) is positioned at the top of fin 106.Fin 106 empty
Intend part (in Fig. 7 B mid portion) between two dotted lines that grid 111 surrounds in order to form fin field
The raceway groove 112 of effect transistor.
Then step S3 is performed: form the first side wall in the both sides of dummy gate, fin is carried out ion implanting
To form the source/drain of fin formula field effect transistor.
The source/drain of fin formula field effect transistor can be injected by primary ions and be formed, it is possible to by two secondary ions
Inject (i.e. the injection technology of falling dopant ion) to be formed.When the source/drain of fin formula field effect transistor is by one
Secondary ion injects when being formed, and as shown in Figure 6B, forms the first side wall 113 in the both sides of dummy gate 111,
Then fin 106 is carried out ion implanting, so that the fin 106 being positioned at dummy gate 111 both sides forms fin
The source/drain 114 of field-effect transistor.When the source/drain of fin formula field effect transistor be by twice from
Son injects when being formed, and after dummy gate 111 both sides form the first side wall 113, carries out low to fin 106
Concentration ion implanting；Then the both sides at dummy gate 111 form the second side wall 115, then enter fin 106
Row intermediate concentration or high concentration ion inject.When the source/drain 114 of fin formula field effect transistor is by mixing
When heteroion injection technology is formed, it is possible to reduce the generation of fin formula field effect transistor channel leakage stream.By
It is formed at fleet plough groove isolation structure 107 ' top, adjacent fin field effect in Semiconductor substrate 100 in fin 106
Answering between the source/drain 114 of the fin 106 of transistor, each fin formula field effect transistor 106 is isolation
, decrease the generation of leakage current.
In subsequent technique, the first side wall 113 can be removed, in order to make the first side wall 113 be removed
During without compromising on other semiconductor structure in Semiconductor substrate 100, the material of the first side wall 113
Matter can be porous material, and porous material is a kind of material being removed easily, and during removing
Without compromising on other semiconductor structure.In the present embodiment, described porous material is amorphous carbon, certainly,
It may also is that other similar material.For its position formation after making the first side wall 113 be removed
Gap is less, and the thickness W of the first side wall 113 is 5nm～10nm.
When the both sides of fin formula field effect transistor dummy gate 111 are also formed with the second side wall 115, first
Side wall 113 differs with the material of the second side wall 115, and the i.e. second side wall 115 is non-porous materials.So,
The second side wall 115 will not be damaged when the first side wall 113 is removed.The material of the second side wall 115 can be
Silicon nitride, silicon oxynitride etc..
Then perform step S4: form interlayer dielectric layer, remove dummy gate, with at dummy gate place
Position forms opening.
As shown in Figure 6 C, deposit silicide 116 on the source/drain 114 of fin formula field effect transistor,
To reduce the sheet resistance of the source/drain 114 of fin formula field effect transistor.Then it is being formed with silicide
Interlayer dielectric layer 117 in the Semiconductor substrate 100 of 116.Utilize CMP process to interlayer
Dielectric layer 117 is processed by shot blasting.Removing dummy gate 111, dummy gate 111 position is formed and opens
Mouth 108.
Then step S5 is performed: be sequentially depositing high-K gate dielectric layer, metal gate material layer to fill opening,
Remove the metal gate material layer on interlayer dielectric layer, high-K gate dielectric layer, form metal gates.
As shown in Figure 6 D, the Semiconductor substrate 100 after dummy gate 111 is removed is sequentially depositing height
K gate dielectric layer 118, metal gate material layer 119 are to fill opening 108.On a semiconductor substrate 100
After deposition high-K gate dielectric layer 118, metal gate material layer 119, sidewall (Fig. 6 D of opening 108
Middle left and right two vertical sidewall) also deposition have high-K gate dielectric layer 118.
The material of high-K gate dielectric layer 118 can be HfO2, HfSiO, HfSiON, HfZrO etc. suitable
Hafnium, its forming method can be that chemical gaseous phase deposits (CVD), ald (ALD) etc..
In the present embodiment, the material of high-K gate dielectric layer 118 is HfO2。
Metal gate material layer 119 can include layer of metal or the different metal of multi-layer material, metal gates
The material of material layer 119 comprise the steps that Ta (tantalum), TaN (tantalum nitride), TaC (ramet), W (tungsten),
WN (tungsten nitride), Al (aluminum), TiAl (titanium aluminide), TiAlN (TiAlN), TiN (titanium nitride)
Deng.The material of metal gate material layer 119 need to be arranged according to the application demand of fin formula field effect transistor,
As when fin formula field effect transistor is designed as PMOS, the material of metal gate material layer 119 can include
W (tungsten) or Al (aluminum), TiN (titanium nitride), WN (tungsten nitride), TiAl (titanium aluminide), TiAlN
(TiAlN)；As when fin formula field effect transistor is designed as NMOS, metal gate material layer 119
Material can include W (tungsten) or Al (aluminum), TiN (titanium nitride), TaN (tantalum nitride), TiAl (aluminum
Change titanium).Available physical vapour deposition (PVD) (PVD), chemical gaseous phase deposition (CVD), ald (ALD)
Metal gate material layer 119 is formed etc. technique.
After deposition high-K gate dielectric layer 118, before metal gate material layer 119, also can be at high K
Deposit diffusion barriers 120 on gate dielectric layer 118, to prevent the metal in metal gate material layer 119 from expanding
It is scattered to high-K gate dielectric layer 118, thus affects the characteristic of high-K gate dielectric layer 118.Diffusion impervious layer 120
Material can be TiAl (titanium aluminide) etc..
Can utilize CMP process successively to metal gate material layer 119, high-K gate dielectric layer
118 are processed by shot blasting, until interlayer dielectric layer 117 exposes, form metal gates.
Then step S6 is performed: remove the high-K gate dielectric on the first side wall, and metal gates sidewall successively
Layer.
As it was previously stated, when the material of the first side wall 113 is amorphous carbon, easily remove it, and
And during removing, other semiconductor structure will not be damaged.As illustrated in fig. 6e, available ashing
(ashing) the first side wall 113 is removed by technique, and etching agent includes O2、CO2、N2、H2、NH3、
CH4In at least one.It is, of course, also possible to use other method to be removed by the first side wall 113.
As fig 6 f illustrates, after removing the first side wall 113, then remove sidewall (Fig. 6 E of metal gates
In two vertical sidewalls) on high-K gate dielectric layer 118.The minimizing technology of high-K gate dielectric layer 118 has many
Kind, in the present embodiment, high-K gate dielectric layer 118 is removed by available wet etching, and etching agent pair
It is silicon oxide that the etching speed of high-K gate dielectric layer 118 is more than material below high-K gate dielectric layer 118
The etching speed of fleet plough groove isolation structure.So, during etching high-K gate dielectric layer 118, no
Semiconductor structure below can be damaged.Inventor finds, when etching agent is absolute alcohol, can reach
State purpose.On the contrary, when utilizing the aqueous solutions such as Fluohydric acid. to remove high-K gate dielectric layer 118, Fluohydric acid.
Deng aqueous solution, the etching speed of high-K gate dielectric layer 118 is much larger than the etching speed of silicon oxide, it is impossible to
Reach above-mentioned purpose.
After fin formula field effect transistor is formed, also Semiconductor substrate 100 can be carried out other quasiconductor and add
Work is to form semiconductor integrated circuit.
In another embodiment of the present invention, Semiconductor substrate 100 is silicon-on-insulator (Silicon On
Insulator) substrate, i.e. fin formula field effect transistor are formed in silicon-on-insulator substrate.Such as Fig. 8 A institute
Show, substrate 201 that silicon-on-insulator substrate 100 includes stacking gradually, buried oxide layer 202, silicon layer 203.
In the present embodiment, the material of buried oxide layer 202 can be silicon oxide.By forming figure on silicon layer
Change photoresist, then the silicon layer 203 not being patterned immediately photoresist covering is performed etching, such as Fig. 8 B institute
Showing, can form fin 106 on buried oxide layer 202, in conjunction with Figure 10 A, (Figure 10 A is bowing of Fig. 8 B
View) shown in, fin 106 extends along the first direction A-A being parallel to semiconductor substrate surface 100a.
As can be seen here, when fin formula field effect transistor is formed in silicon-on-insulator substrate, fin 106 can pass through
The silicon layer 203 of etching silicon-on-insulator substrate is formed.With on body silicon substrate make fin time, this making work
Skill is the simplest.
In conjunction with Fig. 9, Fig. 8 C (Fig. 8 C is the Fig. 9 sectional view along another cross section) and Figure 10 B (figure
10B is the top view of Fig. 9) shown in, the silicon-on-insulator substrate 100 be formed with fin 106 deposits
Dummy gate material layer.Dummy gate material layer forms graphical photoresist, to not being patterned immediately
The dummy gate material layer that photoresist covers performs etching, to form dummy gate 111.Dummy gate 111
Along being parallel to second direction B-B of semiconductor substrate surface 100a (in second direction B-B the present embodiment
First direction A-A different) extend, and across the fin 106 of fin formula field effect transistor.That is, virtual
A part (two end portions of dummy gate 111) for grid 111 is positioned at both sides (Figure 10 B of fin 106
In upper and lower both sides), specifically, be in above the buried oxide layer 202 of fin 106 both sides, a part
(mid portion of dummy gate 111) is positioned at the top of fin 106.Fin 106 by dummy gate 111
The part (in Figure 10 B mid portion) between two dotted lines surrounded is in order to form fin formula field effect transistor
Raceway groove 112.
Then fin 106 is carried out ion implanting, the fin 106 of dummy gate 111 both sides can be positioned at
Part forms the source/drain 114 of fin formula field effect transistor.Owing to fin 106 is formed at buried oxide layer
Above in the of 202, the fin 106 of adjacent fin formula field effect transistor, each fin field effect in Semiconductor substrate 100
Answering between the source electrode of transistor 106, drain electrode is isolation, decreases the generation of leakage current.At insulator
After forming the source/drain 114 of fin formula field effect transistor on upper silicon substrate 100, can refer to above-mentioned enforcement
The processing technology of example is to form fin formula field effect transistor on silicon substrate 100 on insulator.Due to follow-up
Processing technology is same as the previously described embodiments, is not repeated herein.
Accordingly, present invention also offers a kind of fin formula field effect transistor, it may utilize in the present invention
State manufacture method to be formed.As fig 6 f illustrates, and combine Fig. 5 A to Fig. 5 E, Fig. 6 A to Fig. 6 E, figure
7A to Fig. 7 B, Fig. 8 A to Fig. 8 C, Fig. 9, Figure 10 A to Figure 10 B, fin formula field effect transistor bag
Include: forming fin 106 on a semiconductor substrate 100, fin 106 is along being parallel to semiconductor substrate surface
The first direction of 100a extends；High-K gate dielectric layer 118, high-K gate dielectric layer 118 is along being parallel to half
The second direction (second direction is different from described first direction) of conductor substrate surface 100a extends, and horizontal
Stride across fin 106.That is, a part for high-K gate dielectric layer 118 is positioned at the both sides of fin 106, specifically,
It is in the top of the fleet plough groove isolation structure 107 ' of fin 106 both sides (when fin formula field effect transistor is formed
On insulator during silicon substrate, a part for high-K gate dielectric layer 118 is positioned at the embedment oxygen of fin 106 both sides
Change the top of layer 202), a part is positioned at the top of fin 106；It is formed at above high-K gate dielectric layer 118
Metal gates, metal gates also along be parallel to semiconductor substrate surface 100a second direction extend,
The both sides of metal gates are formed with interlayer dielectric layer 117, the sidewall of interlayer dielectric layer 117 and metal gates it
Between there is gap.When fin formula field effect transistor is also formed with the second side wall 115, the second side wall 115
Between interlayer dielectric layer 117 and metal gates, between the second side wall 115 and the sidewall of metal gates
There is gap.
Compared with prior art, the invention have the advantages that
In fin formula field effect transistor, the high-K gate dielectric layer on metal gates two side is removed efficiently, and keeps away
Exempt to produce between metal gates and source/drain parasitic capacitance, and will not be to fin during removing
Other semiconductor structure in field-effect transistor causes damage, and makes the fin formula field effect transistor of formation have
There is good electric property.
Above by the explanation of embodiment, professional and technical personnel in the field should be able to be made to be more fully understood that the present invention,
And can reproduce and use the present invention.Those skilled in the art can according to principle specifically described herein
To above-described embodiment as various changes and modifications to be without departing from the spirit and scope of the present invention
Obviously.Therefore, the present invention should not be construed as being limited to above-described embodiment shown in this article, its
Protection domain should be defined by appending claims.
Claims (17)
1. the manufacture method of a fin formula field effect transistor, it is characterised in that described manufacture method include with
Lower step:
Thering is provided Semiconductor substrate, form fin on the semiconductor substrate, described fin is partly led along being parallel to
The first direction of body substrate surface extends；
Forming dummy gate in the Semiconductor substrate being formed with described fin, described dummy gate is along parallel
Second direction in semiconductor substrate surface extends, and across described fin；
Form the first side wall at described dummy gate along the both sides being parallel to described first direction, fin is entered
Row ion implanting, to form the source electrode of described fin formula field effect transistor, drain electrode；
After forming described source electrode, drain electrode, form interlayer dielectric layer, remove described dummy gate, in institute
The position stating dummy gate forms opening, is sequentially depositing high-K gate dielectric layer, metal gate material layer
To fill described opening, form metal gates；
Remove described first side wall, and the high-K gate dielectric layer on metal gates sidewall successively so that described
Gap is there is in said first direction between interlayer dielectric layer and the sidewall of metal gates.
Manufacture method the most according to claim 1, it is characterised in that in the both sides of described dummy gate
After forming the first side wall and fin being carried out ion implanting, form the second side in the both sides of described dummy gate
Wall, described second side wall, the material of the first side wall differ, and then fin carries out ion implanting again.
Manufacture method the most according to claim 2, it is characterised in that described fin is carried out ion implanting
For low concentration ion implanting, the described ion implanting that again carries out fin is intermediate concentration or high concentration ion note
Enter.
Manufacture method the most according to claim 1, it is characterised in that the material of described first side wall is
Porous material.
Manufacture method the most according to claim 4, it is characterised in that the material of described first side wall is
Amorphous carbon.
Manufacture method the most according to claim 5, it is characterised in that the removal side of described first side wall
Method is that ashing processes, and its etching gas used includes O2、CO2、N2、H2、NH3、CH4In extremely
Few one.
Manufacture method the most according to claim 1, it is characterised in that described Semiconductor substrate is body silicon
Substrate, the step forming fin on the semiconductor substrate includes: form ditch in described Semiconductor substrate
Groove, the Semiconductor substrate of the protrusion between adjacent described groove constitutes described fin.
Manufacture method the most according to claim 7, it is characterised in that be formed with partly leading of fin described
The step forming dummy gate on body substrate includes:
Filling material in described groove is the insulation material layer of silicon oxide, to form fleet plough groove isolation structure,
Then fleet plough groove isolation structure is performed etching, make the top of described fleet plough groove isolation structure less than described half
The surface of conductor substrate；
Deposition dummy gate material layer, forms graphical photoresist on described dummy gate material layer, right
Dummy gate material layer covered by photoresist is not had to perform etching, to form dummy gate, described virtual
A part for grid is positioned at above the fleet plough groove isolation structure of fin both sides, and a part is positioned at the top of described fin.
Manufacture method the most according to claim 1, it is characterised in that described Semiconductor substrate is insulation
Silicon substrate on body, it includes buried oxide layer and the silicon layer that the substrate stacked gradually, material are silicon oxide,
The step forming fin on the semiconductor substrate includes: form graphical light on the semiconductor substrate
Photoresist layer, performs etching the silicon layer not being photo-etched glue-line covering, forms described fin.
Manufacture method the most according to claim 9, it is characterised in that be formed with the half of fin described
The step forming dummy gate on conductor substrate includes:
The Semiconductor substrate be formed with fin deposits dummy gate material layer, at described dummy gate material
Graphical photoresist is formed on layer, to not having dummy gate material layer covered by photoresist to perform etching,
To form dummy gate, above the buried oxide layer of the both sides that a part for described dummy gate is positioned at fin,
A part is positioned at the top of fin.
11. manufacture methods according to claim 8, it is characterised in that on described metal gates sidewall
The minimizing technology of high-K gate dielectric layer be wet etching, its etching agent used is to high-K gate dielectric layer
Etch rate more than the etch rate being pointed to fleet plough groove isolation structure below high-K gate dielectric layer.
12. manufacture methods according to claim 10, it is characterised in that on described metal gates sidewall
The minimizing technology of high-K gate dielectric layer be wet etching, its etching agent used is to high-K gate dielectric layer
Etch rate more than the etch rate being pointed to silicon layer below high-K gate dielectric layer.
13. according to the manufacture method described in claim 11 or 12, it is characterised in that described etching agent is
Absolute alcohol.
14. manufacture methods according to claim 1, it is characterised in that the thickness of described first side wall
For 5nm～10nm.
15. 1 kinds of fin formula field effect transistors, it is characterised in that including:
Forming fin on a semiconductor substrate, described fin is along the first party being parallel to semiconductor substrate surface
To extension；
High-K gate dielectric layer, described high-K gate dielectric layer is along the second party being parallel to semiconductor substrate surface
To extension, and across described fin；
Being formed at the metal gates above high-K gate dielectric layer, the sidewall of described metal gates is not by high K grid
Dielectric layer covers, and described metal gates is formed with inter-level dielectric along the both sides being parallel to described first direction
, between described interlayer dielectric layer and the sidewall of metal gates, there is gap in said first direction in layer.
16. fin formula field effect transistors according to claim 15, it is characterised in that described interlayer is situated between
The second side wall, described second side wall and described metal it is formed with between the sidewall of matter layer and described metal gates
Gap is there is between the sidewall of grid.
17. fin formula field effect transistors according to claim 15, it is characterised in that described gap
Width is 5nm～10nm.
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| CN104576385A (en) * | 2013-10-14 | 2015-04-29 | 中国科学院微电子研究所 | FinFET structure and manufacturing method thereof |
| CN105355558A (en) * | 2014-08-19 | 2016-02-24 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| ES2597129B1 (en) * | 2015-07-13 | 2017-11-08 | Consejo Superior De Investigaciones Científicas (Csic) | ION SENSOR OF DIFFERENTIAL MEASURE |
| CN107978526B (en) * | 2016-10-25 | 2020-12-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor structure |
| CN111697052B (en) * | 2019-03-15 | 2023-09-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN114503264A (en) * | 2022-01-04 | 2022-05-13 | 长江存储科技有限责任公司 | Semiconductor device, memory device and forming method thereof |
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| CN100524661C (en) * | 2006-02-16 | 2009-08-05 | 南亚科技股份有限公司 | Semiconductor device with slot type grid and producing method thereof |
| US8264048B2 (en) * | 2008-02-15 | 2012-09-11 | Intel Corporation | Multi-gate device having a T-shaped gate structure |
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