CN104810265A - Forming method of semiconductor device - Google Patents
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- CN104810265A CN104810265A CN201410042103.4A CN201410042103A CN104810265A CN 104810265 A CN104810265 A CN 104810265A CN 201410042103 A CN201410042103 A CN 201410042103A CN 104810265 A CN104810265 A CN 104810265A
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Abstract
The invention provides a forming method of a semiconductor device and the forming method includes the following steps: firstly adopting a first planarization process to remove a dielectric layer of a part of thickness and then forming a restoration dielectric layer on the dielectric layer. After the restoration dielectric layer is capable of filling fully the previously removed part of the dielectric layer, grooves formed in the surface of the dielectric layer improve the planeness of the surface of the dielectric layer. Therefore, in a follow-up procedure, a second planarization process is adopted to remove the restoration dielectric layer and the dielectric layer so that after a pseudo grid material layer is exposed, the planeness of the surface of the dielectric layer is effectively improved so that it is prevented that larger groove defects are formed in the surface of the dielectric layer. Therefore, the pseudo grid material layer can be removed in a follow-up procedure and grid electrode grooves are formed in the dielectric layer and when the grid electrode grooves are filled with a grid electrode material, it is prevented that grooves are formed in the surface of the dielectric layer and the grooves are filled with the grid electrode material so that conductive layers which connect adjacent grid electrodes are formed. Therefore, an electric conductive phenomenon among the grid electrodes is prevented and defects of the performance of the grid electrodes are reduced.
Description
Technical field
The present invention relates to semiconductor and form field, especially relate to a kind of formation method of semiconductor device.
Background technology
Along with the development of ic manufacturing technology, the integrated level of integrated circuit constantly increases, and the characteristic size of integrated circuit also constantly reduces, and also strict all the more for the quality requirement of electric elements each in integrated circuit.Then integrated circuit preparation technology constantly reforms, to improve the quality of obtained integrated circuit electric elements.
As in the grid preparation technology of COMS, before post tensioned unbonded prestressed concrete (gate last) technique replaces gradually, grid (gate first) technique is to improve the quality of grid.Before so-called, grid technique refers to, after forming opening, directly in opening, fills grid material in the dielectric layer of Semiconductor substrate, forms grid, carries out source and drain injection afterwards, and carry out annealing process to activate the ion in source and drain, thus forms source region and drain region.But in front grid technique, in annealing process, grid is inevitably subject to high-temperature heating, it can cause the threshold voltage vt of transistor to drift about, thus affects the electric property of semiconductor device.
In rear grid technique, shown in figure 1, first form pseudo-gate material layer (not indicating in figure) over the semiconductor substrate 10, etch described pseudo-gate material layer afterwards, described Semiconductor substrate 10 forms pseudo-grid structure 11; Ion is injected in described Semiconductor substrate 10, after forming the source/drain region 14 of pseudo-grid structure 11, shown in figure 2, metallization medium layer 12 in described Semiconductor substrate 10, described dielectric layer 12 covers described pseudo-grid structure 11, adopt CMP(cmp afterwards) remove dielectric layer 12 in described pseudo-grid structure 11, to the pseudo-gate material layer exposing described pseudo-grid structure 11; Shown in figure 3, remove described pseudo-grid structure 11 in etching, thus form gate recess 13 in dielectric layer 12 after, in described gate recess 13, fill grid material form grid (not shown).
Rear grid technique successfully avoids the high temperature introduced when forming source region and drain region and for the damage of grid, thus improves the electric property of the semiconductor device formed.
But in actual mechanical process, shown in figure 4, after the cmp process, there will be the defect of groove 15 on the surface of described dielectric layer 12.Follow-up in described gate recess 13, fill grid material after, in described depression 15, one deck conductive layer can be formed equally.Described conductive layer can cause and conduct phenomenon (gate bridge) between the grid of follow-up formation, thus affects the performance of semiconductor device.
For this reason, in rear grid technique, how to avoid forming groove at dielectric layer surface after the cmp process, and then avoid conducting phenomenon (gate bridge) between grid in subsequent technique, to guarantee that the performance of the final semiconductor device formed is the problem that those skilled in the art need solution badly.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device, reduces to conduct phenomenon between grid and grid.
For solving the problem, the invention provides a kind of formation method of semiconductor device, comprising:
There is provided Semiconductor substrate, form pseudo-grid structure on the semiconductor substrate, described pseudo-grid structure comprises pseudo-gate material layer;
Form dielectric layer on the semiconductor substrate, described dielectric layer covers described pseudo-grid structure;
The first flatening process is adopted to remove the described dielectric layer of segment thickness;
Formed on remaining media layer surface and repair dielectric layer;
The second flatening process is adopted to remove described reparation dielectric layer and remaining media layer, until expose described pseudo-gate material layer.
Alternatively, the thickness of described reparation dielectric layer is
Alternatively, form the step of repairing dielectric layer to comprise: adopt SACVD technique to form described reparation dielectric layer;
Described SACVD technique adopts TEOS and O
3form described reparation dielectric layer.
Alternatively, the technological parameter adopting SACVD technique to form described reparation dielectric layer comprises:
Control temperature is 400 ~ 500 DEG C, and air pressure is 500 ~ 700torr, TEOS and O
3flow-rate ratio be 1:30 ~ 1:18.
Alternatively, the described dielectric layer adopting the first flatening process to remove segment thickness comprises: adopt the CMP of fixed-abrasive grinding steps to remove the dielectric layer of segment thickness.
Alternatively, the pseudo-gate material layer of described pseudo-grid structure is also coated with hard mask layer, and described dielectric layer also covers described hard mask layer;
The described dielectric layer removing segment thickness comprises:
The first flatening process is adopted to remove the described dielectric layer of part, until expose described hard mask layer.
Alternatively, the method adopting the second flatening process to remove described reparation dielectric layer and remaining media layer is; Adopt the CMP of slurry grinding steps.
Alternatively, described dielectric layer comprises first medium layer and second dielectric layer, and the formation process of described dielectric layer comprises:
Control temperature is 400 ~ 500 DEG C, passes into TEOS and O
3, form first medium layer on the semiconductor substrate, described first medium layer covers described pseudo-grid structure;
Control temperature is 350 ~ 500 DEG C, passes into TEOS and O
2, described first medium layer forms second dielectric layer.
Alternatively, the described dielectric layer adopting the first flatening process to remove segment thickness comprises:
First adopt the CMP of slurry grinding steps, grind described second dielectric layer, extremely at least first medium layer described in exposed portion;
Afterwards, adopt the CMP of fixed-abrasive grinding steps, continue the described dielectric layer of grinding;
The step adopting the second flatening process to remove described reparation dielectric layer and remaining media layer comprises: adopt the CMP of slurry grinding steps to carry out described second flatening process.
Alternatively, the thickness of described second dielectric layer is
Compared with prior art, technical scheme of the present invention has the following advantages:
Remove the dielectric layer of segment thickness at employing first flatening process after, described dielectric layer is formed and repairs dielectric layer.After described reparation dielectric layer can fill full removal part dielectric layer in time, at the groove that described dielectric layer surface is formed, improve the evenness of dielectric layer surface.Thus reparation dielectric layer and dielectric layer can be removed at follow-up employing second flatening process, after exposing pseudo-gate material layer, effectively improve the evenness of described dielectric layer surface, avoid forming comparatively big groove defect at dielectric layer surface.Technique scheme can in the pseudo-gate material layer of follow-up removal, gate recess is formed in described dielectric layer, and when filling grid material in gate recess, avoid being formed with groove based on described dielectric layer surface, and in these grooves, fill grid material simultaneously, formed and connect the conductive layer of neighboring gates, and then occur conducting phenomenon (gate bridge) between grid, reduce grid defect.
Accompanying drawing explanation
Fig. 1 and Fig. 4 is the structural representation of the rear grid technique of a kind of semiconductor device of prior art;
Fig. 5 to Figure 11 is the structural representation of the semiconductor device that formation method one embodiment of semiconductor device of the present invention is formed;
Figure 12 is the performance comparison figure of semiconductor device and the existing semiconductor device adopting formation method one embodiment of semiconductor device of the present invention to be formed.
Embodiment
As described in the background art, in rear grid technique, after the structural dielectric layer of the pseudo-grid of removal, larger groove can be formed at dielectric layer surface; The pseudo-grid structure of follow-up removal, gate recess is formed in dielectric layer, and fill in gate recess in grid material process, conductive layer can be formed in the groove on dielectric layer top layer, these conductive layers can cause between neighboring gates and conduct phenomenon (gate bridge), reduce the performance of semiconductor device.
Analyze its reason, existing grinding is removed in the CMP of the dielectric layer of pseudo-grid superstructure, comprises slurry (Slurry) grinding steps and fixed-abrasive (Fix Abrasive) grinding steps.Grind compared to Slurry, Fix Abrasive grinding can control grinding endpoint better, thus at the structural dielectric layer of the pseudo-grid of removal, to expose in the process of pseudo-grid structure, comprise: after first adopting Slurry grinding to remove the dielectric layer of part, adopt Fix Abrasive grinding technics again, until close on grinding endpoint; Afterwards, then adopting Slurry to grind, removing last remaining a small amount of dielectric layer, to exposing pseudo-gate material layer.But, Fix Abrasive grinds for dielectric layer surface damage larger, thus after Fix Abrasive grinds, dielectric layer surface there will be larger groove defect, even if the slurry grinding of follow-up employing, also cannot make up the depression defect formed at dielectric layer surface based on FixAbrasive grinding well.
Follow-up in the described pseudo-grid structure of removal, form gate recess in dielectric layer after, the groove of dielectric layer surface can be connected adjacent gate recess; While filling grid material afterwards in gate recess, conductive layer can be formed in the groove of described dielectric layer surface, thus cause between neighboring gates and conduct phenomenon (gate bridge).
For this reason, the invention provides a kind of formation method of semiconductor device, after effectively can avoiding removing the dielectric layer in pseudo-gate material layer, form the defect of the larger groove of area at dielectric layer surface.Thus when follow-up formation grid, avoid the conductive layer forming conducting neighboring gates in the groove of described dielectric layer, thus cause and conduct phenomenon between grid.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The structural representation of the formation method of the semiconductor device that Fig. 5 to Figure 11 provides for the present embodiment.
Shown in first reference diagram 5, the formation method of the semiconductor device that the present embodiment provides comprises:
There is provided Semiconductor substrate 100, described Semiconductor substrate 100 forms pseudo-grid structure 20, described pseudo-grid structure comprises pseudo-gate material layer 21.
In the present embodiment, the pseudo-gate material layer 21 of described pseudo-grid structure is coated with hard mask layer 22, is formed with sidewall (not indicating in figure) at the sidewall of described hard mask layer 22 and pseudo-gate material layer 21.
The formation process of described pseudo-grid structure 20 comprises: first adopt CVD(chemical vapour deposition technique) in described Semiconductor substrate 100, form pseudo-gate material layer, and hard mask layer is formed in pseudo-gate material layer; On described hard mask layer, apply photoresist afterwards, and in photoresist, form photoetching agent pattern after the techniques such as exposure imaging, and etch described hard mask layer and pseudo-gate material layer with described photoetching agent pattern, form pseudo-grid structure 20; Side wall is formed afterwards on the sidewall of remaining hard mask layer 22 and pseudo-gate material layer 21.
In the present embodiment, described Semiconductor substrate 100 can be silicon substrate, and the material of described pseudo-gate material layer 21 is chosen as polysilicon, and the material of described hard mask layer 22 is chosen as silicon nitride.
In other embodiments except the present embodiment, described Semiconductor substrate also can be germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate; The material of described hard mask layer 22 also can be carborundum, carbonitride of silicium etc.Common Semiconductor substrate, pseudo-grid material, and hard mask layer all can use in the present invention, it does not limit protection scope of the present invention.
Afterwards, with the side wall on described pseudo-grid structure 20 sidewall for mask, in the Semiconductor substrate 100 of described pseudo-grid structure 20 both sides, inject ion, form grid source region and drain region 16.
Then, with reference to shown in figure 6, in described Semiconductor substrate 100, form dielectric layer 30, described dielectric layer 30 covers described pseudo-grid structure 20.
In the present embodiment, the second dielectric layer 32 that described dielectric layer comprises first medium layer 31 and is positioned on described first medium layer 31.
In the present embodiment, the material of described first medium layer 31 and second dielectric layer 32 is silica.But the first medium layer 31 be filled between described pseudo-grid structure 20, compared to the second dielectric layer 32 on first medium layer 31, its material is softer, and uniformity is better, avoids forming too much space between adjacent pseudo-grid structure.In the present embodiment, second dielectric layer 32 is compared to first medium layer 31, and material is harder, in subsequent planarization technique, effectively can increase process window.
In the present embodiment, the formation process of described first medium layer 31 is time atmospheric pressure chemical vapor deposition (Sub-Atmospheric Chemical Vapor Deposition is called for short SACVD), and concrete technology comprises:
In adjustment reaction chamber, temperature is 400 ~ 500 DEG C, and air pressure is 500 ~ 700torr, passes into TEOS (tetraethoxysilane) and O in reaction chamber
3, described Semiconductor substrate 100 forms first medium layer.Described TEOS and O
3flow-rate ratio be 1:30 ~ 1:18, particularly, as described in the flow of TEOS be 600 ~ 3500L/min, O
3flow control at about 18000L/min.It is moderate that above-mentioned flow control can obtain soft durometer, has good uniformity and the good silica of density.
In the present embodiment, described first medium layer 31 covers described pseudo-grid structure 20.
Afterwards, described first medium layer 31 forms second dielectric layer 32.In the present embodiment, the formation process of described second dielectric layer 32 is SACVD, specifically comprises:
In adjustment reaction chamber, temperature is 350 ~ 500 DEG C, and air pressure is 500 ~ 700torr, passes into TEOS (tetraethoxysilane) and O in reaction chamber
2, thus second dielectric layer 32 is formed on described first medium layer 31.Compared to first medium layer 31, the hardness of the second dielectric layer 32 adopting above-mentioned technique to be formed is better, in subsequent CMP process, effectively can increase process window.
In the present embodiment, the thickness of described second dielectric layer 32 is
After the described dielectric layer 30 of formation, adopt flatening process to remove the described dielectric layer 30 of part, expose the pseudo-gate material layer 22 of pseudo-grid structure 20.
In the present embodiment, Fig. 7 to Figure 10 is the process schematic representation of the dielectric layer 30 removed in described pseudo-grid structure 20.
Wherein, the schematic diagram for the described dielectric layer of employing first flatening process removal part shown in Fig. 7 and Fig. 8.Described first flatening process comprises:
Shown in first reference diagram 7, slurry grinding technics is first adopted to remove the part second dielectric layer 32 being positioned at the superiors, until expose at least part of first medium layer 31.
Described slurry grinding technics comprises spray ground slurry above dielectric layer, and adopts polishing pad to grind described dielectric layer with specific speed.Period, described ground slurry has corrosiveness for dielectric layer, coordinates polishing pad for the grinding steps of dielectric layer, efficiently can remove described dielectric layer 30, and after grinding technics, remaining dielectric layer has good surface smoothness.
Slurry grinding technics effectively can improve the efficiency of CMP, and remaining dielectric layer surface has good evenness, but has corrosiveness based on slurry for dielectric layer, thus, is difficult to control polishing end point.
In the present embodiment, after the most dielectric layer of removal, when exposing at least part of described first medium layer, described slurry grinding technics can be stopped, change into and adopt fixed-abrasive (Fix Abrasive) grinding steps to continue the described dielectric layer 30 of grinding, the technique that described Fix Abrasive grinds comprises:
Polishing pad attaches grind and paste, described grinding contains part grinding agent in pasting, and in CMP process, on described dielectric layer, sprays suitable water, and the grinding agent in grinding subsides dissolves, thus participates in CMP.Fix Abrasive grinding technics can not produce excessive corrosion to dielectric layer, thus can control the grinding endpoint of CMP well.
After removal part dielectric layer 30, when the surperficial distance to the pseudo-gate material layer 21 of pseudo-grid structure 20 of remaining certain media layer is the first thickness, stop described Fix Abrasive grinding steps.
In conjunction with reference to shown in figure 8, in the present embodiment, after exposing described hard mask layer 22, stop adopting Fix Abrasive grinding technics abrasive media layer 30.Namely, in the present embodiment, described first thickness is greater than the thickness that 0 is less than or equal to hard mask layer 22.
In other embodiments except the present embodiment, the CMP of Fix Abrasive grinding steps can be only adopted to remove the described dielectric layer of part completely, until the surperficial distance to the pseudo-gate material layer 21 of pseudo-grid structure 20 of remaining certain media layer is the first thickness.Above-mentioned simple change also in protection scope of the present invention, but is compared and the present embodiment, and the grinding rate that the above-mentioned CMP through comprising Fix Abrasive grinding steps removes part dielectric layer is lower.
Shown in figure 9, in the present embodiment, after described Fix Abrasive grinding steps, remaining described first medium layer 31 is formed one deck and repairs dielectric layer 33.
In conjunction with reference to shown in figure 8 and Fig. 9, in the present embodiment, after CMP is ground to and exposes described hard mask layer 22, be formed with the larger groove of area 23 on the surface of first medium layer 31.By analysis, softer based on first medium layer 31, and the technique that Fix Abrasive grinds is less for the corrosion dynamics of first medium layer 31, the dielectric layer surface evenness thus after grinding and uniformity poor, thus form described groove 23 on the surface of first medium layer 31.In the forming process of subsequent gate, in Semiconductor substrate while deposition of gate material, can at described groove 15(as shown in Figure 4) in formation conductive layer, described conductive layer is electrically connected adjacent grid and occurs conducting phenomenon (gate bridge) between grid
In the present embodiment, after described first medium layer 31 forms described reparation dielectric layer 33, described reparation dielectric layer 33 can fill described groove 23, and using described reparation dielectric layer 33 and first medium layer 31 as an integral medium layer, the evenness of the dielectric layer surface of pseudo-grid superstructure effectively can be improved.
In the present embodiment, the material of described reparation dielectric layer 33 is silicon dioxide, and formation process is SACVD technique, specifically comprises:
In adjustment reaction chamber, temperature is 400 ~ 500 DEG C, and air pressure is 500 ~ 700torr, passes into TEOS (tetraethoxysilane) and O in reaction chamber
3, wherein, described TEOS and O
3flow-rate ratio be 1:3 ~ 1:1.8, thus form one deck silicon oxide layer on remaining first medium layer 31, as reparation dielectric layer.
Alternatively, in the present embodiment, the material of described reparation dielectric layer 33 is identical with the material of described first medium layer 31, thus the compatibility of described reparation dielectric layer 33 and described first medium layer 31.
In conjunction with reference to shown in Figure 10, after the described reparation dielectric layer 33 of formation, using described reparation dielectric layer 33 and first medium layer 31 as an integral medium layer, CMP is adopted to continue abrasive media layer, until expose described pseudo-gate material layer 21.
In the present embodiment, the CMP of grinding described reparation dielectric layer 33 and first medium layer 31 is slurry grinding steps.Now, apart from the thinner thickness of the dielectric layer (comprise first medium layer and repair dielectric layer) above described pseudo-gate material layer 21, adopt slurry grinding technics, after dielectric layer in the described pseudo-gate material layer 21 of slow removal (comprising: the reparation hypothallus of part and first medium layer) and hard mask layer, the surface smoothness of the dielectric layer formed after can effectively improving CMP.
Based on described slurry grinding technics meeting etching dielectric layer, the removed amplitude of dielectric layer is larger, if the thickness of described reparation dielectric layer 33 is too small, remove dielectric layer to follow-up slurry grinding technics and leave enough buffering surpluses, the dielectric layer that slurry grinding technics may be caused to remove too much and too much removes described pseudo-gate material layer 21, adds the technology difficulty of the operation of slurry grinding technics; And if described reparation dielectric layer 33 is excessive, blocked up dielectric layer, reduces slurry grinding and remove described pseudo-gate material layer 21 efficiency, but also dielectric layer 33 is repaired in increase formation, and remove the process costs repairing dielectric layer 33.In the present embodiment, the thickness of described reparation dielectric layer 33 is chosen as
With reference to shown in Figure 10, filling full described groove 23 with described reparation dielectric layer 33, and adopting the second flatening process to remove unnecessary reparation dielectric layer 33 and first medium layer 31, until expose described pseudo-gate material layer 21.
In the present embodiment, described second flatening process is the CMP adopting slurry polishing step.Continue with reference to shown in Figure 10, after the second flatening process, the dielectric layer surface exposing described pseudo-gate material layer 21 does not have obvious groove defect, surface smoothness and having good uniformity.
In conjunction with reference to Figure 11, after exposing described pseudo-gate material layer 21, remove described pseudo-gate material layer 21, in described first medium layer 31, form gate recess 40.Follow-up filling in described gate recess 40 expires grid material, in order to form grid.Based on the surface smoothness that described gate recess 40 periphery dielectric layer is good, avoid and form conductive layer in described dielectric layer, cause adjacent grid to occur conducting phenomenon.
Figure 12 is the performance comparison figure of semiconductor device and the existing semiconductor device adopting the formation method of embodiment of the present invention semiconductor device to be formed.
Wherein, the longitudinal axis of Figure 12 is the number (that is, defect number) conducting appearring in the same chip semiconductor substrate that obtains of Scanning Detction grid, and abscissa is the sample of detected semiconductor device.Dotted line 01 is the test curve of existing semiconductor device (comparative example), the test curve of the semiconductor device that solid line 02 obtains for the formation method of semiconductor device (embodiment) adopting the embodiment of the present invention and provide.
Embodiment is after Fix Abrasive grinding steps, described dielectric layer is formed and repairs dielectric layer, then removes in pseudo-gate material layer with the grinding of slurry grinding steps, the semiconductor device formed after unnecessary dielectric layer; Comparative example is after Fix Abrasive grinding steps, the semiconductor device formed after directly removing dielectric layer unnecessary in pseudo-gate material layer with the grinding of slurry grinding steps.Wherein, each step CMP grinding steps technique of each group sample is identical.
As shown in Figure 12, the defect number of the semiconductor device adopting the above embodiment of the present invention to obtain is significantly less than the defect number of existing semiconductor device.That is: the performance of the semiconductor device adopting the above embodiment of the present invention to obtain is better than the performance of existing semiconductor device.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for semiconductor device, is characterized in that: comprising:
There is provided Semiconductor substrate, form pseudo-grid structure on the semiconductor substrate, described pseudo-grid structure comprises pseudo-gate material layer;
Form dielectric layer on the semiconductor substrate, described dielectric layer covers described pseudo-grid structure;
The first flatening process is adopted to remove the described dielectric layer of segment thickness;
Formed on remaining media layer surface and repair dielectric layer;
The second flatening process is adopted to remove described reparation dielectric layer and remaining media layer, until expose described pseudo-gate material layer.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the thickness of described reparation dielectric layer is
3. the formation method of semiconductor device as claimed in claim 1, is characterized in that, forms the step of repairing dielectric layer and comprises: adopt SACVD technique to form described reparation dielectric layer;
Described SACVD technique adopts TEOS and O
3form described reparation dielectric layer.
4. the formation method of semiconductor device as claimed in claim 3, is characterized in that, the technological parameter adopting SACVD technique to form described reparation dielectric layer comprises:
Control temperature is 400 ~ 500 DEG C, and air pressure is 500 ~ 700torr, TEOS and O
3flow-rate ratio be 1:30 ~ 1:18.
5. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the described dielectric layer adopting the first flatening process to remove segment thickness comprises: adopt the CMP of fixed-abrasive grinding steps to remove the dielectric layer of segment thickness.
6. the formation method of semiconductor device as claimed in claim 5, it is characterized in that, the pseudo-gate material layer of described pseudo-grid structure is also coated with hard mask layer, and described dielectric layer also covers described hard mask layer;
The described dielectric layer removing segment thickness comprises:
The first flatening process is adopted to remove the described dielectric layer of part, until expose described hard mask layer.
7. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the method adopting the second flatening process to remove described reparation dielectric layer and remaining media layer is; Adopt the CMP of slurry grinding steps.
8. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, described dielectric layer comprises first medium layer and second dielectric layer, and the formation process of described dielectric layer comprises:
Control temperature is 400 ~ 500 DEG C, passes into TEOS and O
3, form first medium layer on the semiconductor substrate, described first medium layer covers described pseudo-grid structure;
Control temperature is 350 ~ 500 DEG C, passes into TEOS and O
2, described first medium layer forms second dielectric layer.
9. the formation method of semiconductor device as claimed in claim 8, is characterized in that, the described dielectric layer adopting the first flatening process to remove segment thickness comprises:
First adopt the CMP of slurry grinding steps, grind described second dielectric layer, extremely at least first medium layer described in exposed portion;
Afterwards, adopt the CMP of fixed-abrasive grinding steps, continue the described dielectric layer of grinding;
The step adopting the second flatening process to remove described reparation dielectric layer and remaining media layer comprises: adopt the CMP of slurry grinding steps to carry out described second flatening process.
10. the formation method of semiconductor device as claimed in claim 8, it is characterized in that, the thickness of described second dielectric layer is
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| CN109285773A (en) * | 2018-09-12 | 2019-01-29 | 上海华力集成电路制造有限公司 | The manufacturing method of semiconductor devices |
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| US20120052666A1 (en) * | 2010-08-26 | 2012-03-01 | Globalfoundries Inc. | Method of fabricating a semiconductor device using compressive material with a replacement gate technique |
| CN102386085A (en) * | 2010-09-06 | 2012-03-21 | 中国科学院微电子研究所 | Planarization method for back gate process and device structure thereof |
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| US20130224944A1 (en) * | 2012-02-27 | 2013-08-29 | Globalfoundries Inc. | Methods for fabricating integrated circuits using tailored chamfered gate liner profiles |
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| CN109285773A (en) * | 2018-09-12 | 2019-01-29 | 上海华力集成电路制造有限公司 | The manufacturing method of semiconductor devices |
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