CN114758981B - Planarization method and wafer after filling deep trench with silicon dioxide - Google Patents
Planarization method and wafer after filling deep trench with silicon dioxide Download PDFInfo
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- CN114758981B CN114758981B CN202110021933.9A CN202110021933A CN114758981B CN 114758981 B CN114758981 B CN 114758981B CN 202110021933 A CN202110021933 A CN 202110021933A CN 114758981 B CN114758981 B CN 114758981B
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- silicon dioxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Abstract
The invention discloses a planarization method after filling deep trenches with silicon dioxide, which comprises the following steps: step one, grinding once to make silicon dioxide surface higher than groove surface at least
Step two, high Wen Mihua is carried out on the silicon dioxide; and step three, secondary grinding so as to enable the silicon dioxide surface to be flush with the groove surface. The planarization method obtains a flat and perfect trench surface through common CMP-high temperature densification-high selectivity CMP. The invention also provides a wafer comprising the deep trench processed by the method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a planarization method after filling deep trenches with silicon dioxide and a wafer containing the deep trenches processed by the method.
Background
During wafer processing, deep trenches are filled with silicon dioxide (SiO 2 ) There is a significant cost advantage over filling polysilicon. Thus, filling the deep trenches with silicon dioxide is beneficial for cost savings. The deep trench surface after filling with silicon dioxide typically requires further grinding to planarize it. In the prior art, CMP (chemical mechanical polishing) is typically directly used to polish after filling the deep trenches with silicon dioxide, as shown in fig. 1. However, due to the defect that the filled silicon dioxide may contain shrinkage cavity or water vapor, when a high temperature process is encountered in the subsequent processing process, the silicon dioxide in the deep trench further densifies the structure under the action of high temperature, so that pits are formed on the surface, and a contact layer between the silicon dioxide in the deep trench and an upper layer substance is not flat any more, thereby affecting the final electrical performance of the wafer. As a modification, a step of high Wen Mihua may be added before CMP, as shown in fig. 2. However, due to the greater stress of the thicker silicon dioxide layer at high Wen Mihua, cracks across the trench often occur at the deep trench surface, which cracks further degrade during the subsequent CMP process, resulting in a significant reduction in yield.
Therefore, how to improve the surface morphology of deep trenches filled with silicon dioxide is a technical problem to be solved in the field of semiconductor production.
Disclosure of Invention
In order to solve the existing technical problems, the application provides a planarization method after filling deep trenches with silicon dioxide, wherein a flat and complete trench surface is obtained through common CMP-high temperature densification-high selectivity CMP. The invention also provides a wafer comprising the deep trench processed by the method.
According to the present invention, there is provided a planarization method after filling deep trenches with silicon dioxide, comprising:
step one, grinding once to make silicon dioxide surface higher than groove surface at least
Step two, high Wen Mihua is carried out on the silicon dioxide; and
and step three, secondary grinding is carried out so that the silicon dioxide surface is flush with the groove surface.
According to one embodiment of the invention, after one polishing, the silicon dioxide surface is at most higher than the trench surface
According to one embodiment of the invention, high Wen Mihua comprises heating at 920-1380 ℃ for at least 20min.
According to one embodiment of the invention, the temperature of high Wen Mihua is 1150 ℃.
According to one embodiment of the invention, the time to height Wen Mihua is less than 60 minutes.
According to one embodiment of the invention, the selectivity of the secondary grinding is higher than that of the primary grinding, the selectivity being the ratio of the amount of silicon dioxide removed to the amount of silicon nitride removed resulting from grinding.
According to one embodiment of the present invention, the selection ratio of one grinding is 2-6:1.
According to one embodiment of the invention, the secondary grinding is selected at a ratio of 15-25:1.
According to the present invention, there is provided a wafer comprising deep trenches processed using the planarization method described above.
By adopting the technical scheme, compared with the prior art, the invention has the following advantages:
1. with the method according to the present invention, a portion of the silicon dioxide remains after the first polishing, the surface is planarized by the second polishing after collapse of the high Wen Mihua, and the silicon dioxide in the deep trench is densified and is not affected by the subsequent high temperature process.
2. By using the method provided by the invention, the silicon dioxide on the surface of the wafer is flatter by first grinding, so that the concentration of the stress on the surface of the wafer caused by uneven heating at the height of Wen Mihua is avoided, the possibility of cracking on the surface of the wafer is effectively reduced, and the higher yield is ensured.
3. According to the method, the production cost is effectively reduced on the premise of ensuring the enough flatness of the flattened silicon dioxide surface and avoiding the occurrence of cracking defects on the wafer surface by reasonably controlling the operation parameters such as the grinding ratio, the high Wen Mihua temperature, the high time and the like.
Drawings
FIG. 1 shows a schematic diagram of one example of planarizing the surface of a deep trench filled with silicon dioxide in the prior art;
FIG. 2 shows a schematic diagram of another example of planarizing the surface of a deep trench filled with silicon dioxide in the prior art;
figure 3 shows a flow chart of a planarization method after filling a deep trench with silicon dioxide in accordance with the present invention;
fig. 4 shows a schematic diagram of a planarization method after filling the deep trenches with silicon dioxide in accordance with the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Fig. 3 and 4 show a flow chart and a schematic diagram, respectively, of a planarization method after filling a deep trench with silicon dioxide in accordance with the present invention. Compared with the prior art, the planarization method provided by the invention adopts primary grinding-high-temperature densification-secondary grinding to obtain the deep groove surface morphology which is always smooth and does not contain cracking defects.
Specifically, pits are usually left on the surface of the deep trench after the silicon dioxide is filled, so that the surface of the silicon dioxide at the moment presents an uneven appearance. Firstly, the wafer surface is ground once to obtain a generally flat silicon dioxide surface, and a part of silicon dioxide needs to be reserved after the grinding so as to ensure that the collapse formed on the silicon dioxide surface in the subsequent high Wen Mihua process does not affect the silicon dioxide in the groove. Experiments show that the collapse amount of the silicon dioxide is about 7% of the total height of the silicon dioxide due to the high Wen Mihua, so that the height of the surface of the silicon dioxide which is remained after one grinding and is higher than the surface of the groove is at least higher than the collapse amount, for example, the collapse amount can be set to be 2-3 times. In one embodiment of the invention, the silicon dioxide surface may be at least higher than the trench surface after one grinding
And secondly, heating the wafer for a period of time at a certain temperature to perform high Wen Mihua treatment on the wafer so as to eliminate the defects of water vapor, shrinkage cavity and the like in the silicon dioxide, so that the structure of the wafer is more compact. The temperature of the high-temperature densification can be set to be higher than the highest temperature of the subsequent process to avoid surface dishing caused by further densification of the silicon dioxide when the subsequent process with higher temperature is encountered; however, too high a temperature of Wen Mihua can lead to device damage within the wafer and increased costs. In embodiments of the present invention, the heating temperature of high Wen Mihua can be set at 920-1380 ℃, preferably 1150 ℃; the heating time may be not less than 20 minutes to ensure a stable densification effect, preferably not more than 60 minutes to save costs. Finally, can be used for the oxidation ofThe silicon surface is subjected to a secondary grinding so that the silicon dioxide surface is flush with the trench surface.
In an embodiment of the present invention, a layer of silicon nitride (SiN) may be deposited on the Substrate (Substrate) surface when the deep trenches are filled with silicon dioxide. Since silicon nitride has a large hardness, it can function as a polish stop layer during planarization of silicon dioxide. As shown in fig. 4, according to the planarization method of the present invention, only the silicon dioxide on the upper portion is removed during the first polishing step, and the silicon nitride layer is not touched; and in the step three, the secondary grinding is carried out, and the grinding liquid with higher grinding rate ratio of silicon oxide to silicon nitride can be used for grinding the groove silicon dioxide filling layer. Since silicon dioxide is polished at a much higher rate than silicon nitride, silicon nitride is relatively polished, and thus polishing will not continue when touching silicon nitride. In order to save polishing cost, the trench silicon oxide filling layer may be polished with a polishing liquid having a lower polishing rate ratio of silicon oxide to silicon nitride than that of the secondary polishing, i.e., the selection ratio of the secondary polishing (high selectivity CMP) is higher than that of the primary polishing (normal CMP) at the time of the primary polishing. Wherein the selection ratio (or polishing rate ratio) is a ratio of a removal amount (or polishing rate) of silicon dioxide to a removal amount (or polishing rate) of silicon nitride caused by polishing. In embodiments of the present invention, the selection ratio of primary grinding may be 2-6:1 and the selection ratio of secondary grinding may be 15-25:1. To further save grinding costs, it is possible to set a lower cost one grinding to remove as much silica as possible. In an embodiment of the invention, after one grinding, the silicon dioxide surface is higher than the trench surface at most
After planarization is completed, the silicon nitride layer may be removed according to practical requirements in a conventional manner in the art, for example, but not limited to, a phosphoric acid tank soaking wet etching method is used to remove the silicon nitride layer.
By using the method for planarization, on one hand, the overall flat silicon dioxide surface obtained by one-time grinding before the height Wen Mihua can be uniformly heated, so that the stress concentration of local areas of the surface is not easy to occur; on the other hand, the concave surface formed by the height Wen Mihua after primary planarization is flatter than the concave surface formed by the height Wen Mihua directly after the silicon dioxide filling, which is beneficial to the smooth secondary grinding. Based on the two reasons, the possibility of cracking on the surface of the wafer can be effectively reduced, and higher yield is ensured. In addition, the silicon dioxide bears the highest temperature in the wafer preparation process in the high Wen Mihua process, so that the silicon dioxide cannot be densified again to form a concave due to high temperature in the subsequent process, namely, cannot be influenced by the subsequent high-temperature process.
The foregoing examples merely illustrate embodiments of the invention and are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (9)
1. A planarization method after filling a deep trench with silicon dioxide, comprising:
step one, grinding once to make silicon dioxide surface higher than groove surface at least
Step two, high Wen Mihua is carried out on the silicon dioxide; and
and thirdly, directly performing secondary grinding after the high-temperature densification so as to enable the silicon dioxide surface to be flush with the groove surface.
2. The planarization method of claim 1, wherein said silicon dioxide surface is at most higher than the trench surface after said one polishing
3. The planarization method of claim 1, wherein said high temperature densification comprises heating at 920-1380 ℃ for at least 20 minutes.
4. The planarization method of claim 1, wherein said high temperature densification temperature is 1150 ℃.
5. The planarization method of claim 1, wherein said high temperature densification time is less than 60 minutes.
6. The planarization method of claim 1, wherein said second polishing has a selectivity ratio that is higher than a selectivity ratio of said first polishing, said selectivity ratio being a ratio of an amount of silicon dioxide removed by polishing to an amount of silicon nitride removed.
7. The planarization method of claim 6, wherein said one-shot polishing has a selectivity of 2-6:1.
8. The planarization method of claim 6, wherein said secondary polishing is selected at a ratio of 15-25:1.
9. A wafer comprising deep trenches processed using the planarization method of any one of claims 1-8.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124183A (en) * | 1997-12-18 | 2000-09-26 | Advanced Micro Devices, Inc. | Shallow trench isolation formation with simplified reverse planarization mask |
| US6197658B1 (en) * | 1998-10-30 | 2001-03-06 | Taiwan Semiconductor Manufacturing Company | Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity |
| JP2005072358A (en) * | 2003-08-26 | 2005-03-17 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| CN103035486A (en) * | 2012-09-28 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for simultaneously filling and flattening deep trenches with different sizes |
| CN103415914A (en) * | 2011-03-08 | 2013-11-27 | 应用材料公司 | Post-planarization densification |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531523A (en) * | 2013-10-30 | 2014-01-22 | 上海华力微电子有限公司 | Preparation method of STI (shallow trench isolation) structure |
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- 2021-01-08 CN CN202110021933.9A patent/CN114758981B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6124183A (en) * | 1997-12-18 | 2000-09-26 | Advanced Micro Devices, Inc. | Shallow trench isolation formation with simplified reverse planarization mask |
| US6197658B1 (en) * | 1998-10-30 | 2001-03-06 | Taiwan Semiconductor Manufacturing Company | Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity |
| JP2005072358A (en) * | 2003-08-26 | 2005-03-17 | Seiko Epson Corp | Manufacturing method of semiconductor device |
| CN103415914A (en) * | 2011-03-08 | 2013-11-27 | 应用材料公司 | Post-planarization densification |
| CN103035486A (en) * | 2012-09-28 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for simultaneously filling and flattening deep trenches with different sizes |
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