KR100355865B1 - planari-zation method and polishing material for a insulator film of a semiconductor device - Google Patents
planari-zation method and polishing material for a insulator film of a semiconductor device Download PDFInfo
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- KR100355865B1 KR100355865B1 KR1019990067699A KR19990067699A KR100355865B1 KR 100355865 B1 KR100355865 B1 KR 100355865B1 KR 1019990067699 A KR1019990067699 A KR 1019990067699A KR 19990067699 A KR19990067699 A KR 19990067699A KR 100355865 B1 KR100355865 B1 KR 100355865B1
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- oxide film
- nitride film
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000005498 polishing Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000012212 insulator Substances 0.000 title description 2
- 239000000463 material Substances 0.000 title 1
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 239000002245 particle Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910021642 ultra pure water Inorganic materials 0.000 claims description 4
- 239000012498 ultrapure water Substances 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 3
- 101100366711 Arabidopsis thaliana SSL13 gene Proteins 0.000 description 2
- 101100366561 Panax ginseng SS11 gene Proteins 0.000 description 2
- 239000003082 abrasive agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000006703 hydration reaction Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09G—POLISHING COMPOSITIONS; SKI WAXES
- C09G1/00—Polishing compositions
- C09G1/02—Polishing compositions containing abrasives or grinding agents
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Abstract
본 발명에 따른 반도체 소자의 평탄화 방법에서는 규소 기판 위에 스트레스 방지층으로 패드 산화막을 증착하고, 그 위에 질화막을 증착한다. 질화막, 패드 산화막 및 규소 기판을 차례로 식각하여 트렌치를 형성한 다음, 트렌치 내에 열산화 방법으로 라이너 산화막을 형성하고, 그 상부에 산화막을 8,000~10,500Å 정도 증착한다. 이어, CMP 공정을 실시하여 산화막 표면이 질화막과 거의 같아질 때까지 산화막을 연마하고 질화막을 제거한다. 산화막을 연마할 때 희석된 HF를 포함하는 연마제를 사용함으로써 산화막의 연마 제거 속도를 높인다. 따라서, 산화막의 밀도차 때문에 위치에 따른 연마 속도 차이에 의해 활성 영역이 손상되는 것을 방지할 수 있으며, 공정수가 감소되고 불순물 입자의 생성을 방지할 수 있다,In the method of planarizing a semiconductor device according to the present invention, a pad oxide film is deposited on a silicon substrate as a stress preventing layer, and a nitride film is deposited thereon. The nitride film, the pad oxide film, and the silicon substrate are sequentially etched to form a trench, and then a liner oxide film is formed in the trench by a thermal oxidation method, and an oxide film is deposited thereon at about 8,000 to 10,500 kPa. The CMP process is then performed to polish the oxide film and remove the nitride film until the oxide film surface is almost the same as the nitride film. When polishing the oxide film, the polishing removal rate of the oxide film is increased by using an abrasive containing diluted HF. Therefore, it is possible to prevent the active region from being damaged by the difference in polishing speeds depending on the position due to the difference in density of the oxide film, and the number of processes can be reduced and generation of impurity particles can be prevented.
Description
본 발명은 반도체 소자용 절연막의 평탄화 방법 및 이에 사용되는 연마제에 관한 것이다.The present invention relates to a planarization method of an insulating film for a semiconductor device and an abrasive used therein.
일반적으로 반도체 소자 분리 방법으로 LOCOS(local oxidation of silicon) 소자 분리와 얕은 트렌치 소자 분리(STI : shallow trench isolation) 등이 있다.In general, semiconductor device isolation methods include local oxidation of silicon (LOCOS) device isolation and shallow trench isolation (STI).
LOCOS는 공정이 간소하고 생성되는 산화막질이 좋다는 이점이 있으나, 소자 분리 영역이 차지하는 면적이 크기 때문에 미세화에 한계가 있을 뿐만 아니라 버즈 비크(bird's beak)가 발생한다.LOCOS has the advantage of a simple process and good oxide film quality, but due to the large area occupied by the device isolation region, there is a limit to miniaturization and a bird's beak occurs.
반면에, 얕은 트렌치 소자 분리는 건식 식각을 이용하여 실리콘 기판에 얕은 트렌치를 만들고 그 속에 절연물을 채우는 방법으로서, 버즈 비크와 관련된 문제가 적고, 채워진 트렌치는 표면을 평탄하게 하므로 소자 분리 영역이 차지하는 면적이 작아서 미세화에 유리하다.On the other hand, shallow trench isolation is a method of forming a shallow trench in a silicon substrate using dry etching to fill an insulator therein, which is less troubled by the buzz beak and the filled trench flattens the surface, thus occupying the area of the isolation region. It is small and is advantageous for miniaturization.
그러면, 첨부한 도면을 참조하여 종래에 따른 소자 분리 영역 형성에 대하여 상세히 설명한다.Next, the device isolation region formation according to the related art will be described in detail with reference to the accompanying drawings.
먼저, 도 1a에 도시한 바와 같이, 규소 기판(1) 위에 패드(pad) 산화막(2)과 질화막(3)을 연속하여 형성한 다음, 질화막(3), 패드 산화막(2) 및 규소 기판(1)을 차례로 식각하여 트렌치(101)를 형성한다.First, as shown in FIG. 1A, a pad oxide film 2 and a nitride film 3 are successively formed on the silicon substrate 1, and then the nitride film 3, the pad oxide film 2, and the silicon substrate ( 1) is sequentially etched to form the trench 101.
다음, 도 1b에 도시한 바와 같이 트렌치(101)의 벽면에 얇은 라이너(liner) 산화막(4)을 형성한 다음, 두꺼운 산화막(5)을 증착하다. 이때, 산화막(5)은 트렌치(101)에 의한 단차로 인해 트렌치(101) 쪽으로 움푹 들어간 형태를 이룬다.Next, as shown in FIG. 1B, a thin liner oxide film 4 is formed on the wall surface of the trench 101, and then a thick oxide film 5 is deposited. At this time, the oxide film 5 has a recessed shape toward the trench 101 due to the step by the trench 101.
다음, 도 1c에 도시한 바와 같이 CMP(chemical-mechanical polishing)의 균일도를 향상시키기 위해 산화막(5)을 패터닝하여 트렌치(101) 상부를 제외한 부분을 제거한다.Next, as illustrated in FIG. 1C, the oxide film 5 is patterned to remove uniform portions except the upper portion of the trench 101 in order to improve the uniformity of chemical-mechanical polishing (CMP).
이어, 도 1d에 도시한 바와 같이 산화막(5)을 CMP 방법으로 연마한다.Next, as shown in FIG. 1D, the oxide film 5 is polished by the CMP method.
다음, 도 1e에 도시한 바와 같이 습식 식각 방법으로 질화막(3)을 제거한다.Next, as illustrated in FIG. 1E, the nitride film 3 is removed by a wet etching method.
이와 같이 얕은 트렌치 소자 분리는 트렌치에 의한 단차로 인해 트렌치 내에 절연물을 형성한 다음 평탄화하는 공정이 필요한데, 연마 방법으로 평탄화할 때 위치에 따라 절연물의 밀도가 달라 연마 속도 차이가 나므로 활성 영역이 과도하게연마된다.As described above, the shallow trench isolation requires a step of forming an insulating material in the trench and then flattening due to the step difference caused by the trench. To be polished.
연마 속도를 균일하게 하기 위해 절연막을 식각한 후 연마하게 되면 오염 입자(particle)가 발생되고 이러한 입자는 기판 표면에 스크래치를 유발시킨다.When the insulating film is etched and polished to make the polishing rate uniform, contaminating particles are generated and these particles cause scratches on the substrate surface.
또한, 연마 후 질화막을 제거할 때 활성 영역에 질화막이 남게되어 불량이 발생한다.In addition, when the nitride film is removed after polishing, a nitride film remains in the active region, thereby causing a defect.
본 발명의 과제는 절연막의 평탄화시 연마 속도의 균일성을 확보하는 것이다.An object of the present invention is to ensure uniformity in polishing rate when the insulating film is planarized.
본 발명의 다른 과제는 절연막의 평탄화시 오염 입자의 생성을 방지하는 것이다.Another object of the present invention is to prevent the generation of contaminating particles during planarization of the insulating film.
본 발명의 다른 과제는 반도체 소자의 활성 영역의 손상을 줄이는 것이다.Another object of the present invention is to reduce the damage of the active region of the semiconductor device.
도 1a 내지 도 1e는 종래의 기술에 따른 얕은 트렌치 소자 분리 제조 방법을 공정 순서에 따라 나타낸 단면도이고,1A to 1E are cross-sectional views illustrating a method of manufacturing a shallow trench isolation device according to a related art according to a process sequence;
도 2 내지 도 5는 본 발명에 따른 얕은 트렌치 소자 분리 제조 방법을 공정 순서에 따라 나타낸 단면도이다.2 to 5 are cross-sectional views showing a shallow trench device isolation manufacturing method according to the present invention in the order of process.
이러한 과제를 해결하기 위해 본 발명에서는 트렌치를 덮는 산화막을 식각하지 않고 HF를 포함하는 연마제로 연마한다.In order to solve this problem, in the present invention, the oxide film covering the trench is polished with an abrasive containing HF without etching.
본 발명에 따른 반도체 소자의 평탄화 방법에서는 반도체 기판 상부에 질화막을 형성한 다음, 질화막과 반도체 기판을 차례로 식각하여 트렌치를 형성한다. 트렌치 및 질화막 상부에 산화막을 형성하고 HF를 포함하는 연마제를 사용하여 산화막과 질화막을 선택적으로 연마한 후, 질화막을 제거한다.In the method of planarizing a semiconductor device according to the present invention, a nitride film is formed on the semiconductor substrate, and the nitride film and the semiconductor substrate are sequentially etched to form a trench. An oxide film is formed over the trench and the nitride film, and the oxide film and the nitride film are selectively polished using an abrasive containing HF, and then the nitride film is removed.
본 발명에서 연마 방법은 CMP 방법을 사용할 수 있다.In the present invention, the polishing method may use a CMP method.
여기서, 연마제는 연마 입자와 KOH, H2O2, 그리고 초순수를 더 포함할 수 있는데, 연마 입자는 SiO2, Al2O3및 Ce2O3중 어느 하나로 이루어질 수 있다.Here, the abrasive may further comprise abrasive particles and KOH, H 2 O 2 , and ultrapure water, the abrasive particles may be made of any one of SiO 2 , Al 2 O 3 and Ce 2 O 3 .
HF는 H2O와 49% HF의 혼합 비율이 100:1이며, HF의 중량비는 14.3±1 wt%인 것이 좋다.For HF, the mixing ratio of H 2 O and 49% HF is 100: 1, and the weight ratio of HF is 14.3 ± 1 wt%.
본 발명에서는 산화막을 연마할 때 산화막에 대한 연마 제거율이 높은 희석된 HF를 포함하는 연마제를 사용함으로써 산화막과 질화막의 연마 속도 선택비를 높일 수 있으므로, 산화막의 밀도 차이에 의해 활성 영역이 과도하게 연마되어 손상을 입히는 문제를 해결할 수 있다. 또한, 불순물 입자가 발생하지 않으며, 공정수가 감소된다.In the present invention, since the polishing rate selection ratio of the oxide film and the nitride film can be increased by using an abrasive containing diluted HF having a high removal rate for polishing the oxide film, the active region is excessively polished due to the difference in density of the oxide film. To solve the problem of damage. In addition, no impurity particles are generated and the number of steps is reduced.
그러면, 첨부한 도면을 참고로 하여 본 발명의 실시예에 따른 얕은 트렌치 소자 분리 제조 방법에 대하여 상세하게 설명한다.Next, a shallow trench device isolation manufacturing method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 도 6에 도시한 바와 같이, (100) P형 에피(epi) 규소 기판(11) 위에 이후 형성될 질화막(13)과의 스트레스(stress) 방지층으로 패드 열산화막(12)을 150Å 정도의 두께로 증착하고, 이어, LPCVD(low pressure chemical vapor deposition) 방법으로 질화막(13)을 2,000Å 정도의 두께로 증착한다. 다음, 질화막(13), 패드 열산화막(12) 및 규소 기판(11)을 차례로 건식 식각하여 트렌치(111)를 형성한다. 여기서, 트렌치(111)의 깊이는 약 5,000Å 정도이다.First, as shown in FIG. 6, the pad thermal oxide film 12 is formed on the (100) P-type epi silicon substrate 11 as a stress preventing layer with the nitride film 13 to be formed later. After the deposition, the nitride film 13 is deposited to a thickness of about 2,000 kPa by low pressure chemical vapor deposition (LPCVD). Next, the trench 111 is formed by dry etching the nitride film 13, the pad thermal oxide film 12, and the silicon substrate 11 in order. Here, the depth of the trench 111 is about 5,000 kPa.
다음, 도 7에 도시한 바와 같이 트렌치(111)의 스트레스 완화를 위해 트렌치(111)의 벽면에 열산화 방법으로 얇은 라이너 산화막(14)을 형성한 다음,APCVD(atmosphere pressure chemical vapor deposition) 방법으로 두꺼운 산화막(15)을 8,000~10,500Å 정도 증착하고, 열처리하여 산화막(15)의 밀도를 높인다. 이때, 트렌치(111)에 의한 단차로 인해 트렌치(111) 상부의 산화막(15)은 트렌치(111) 쪽으로 움푹 들어간 형태를 이룬다.Next, as shown in FIG. 7, a thin liner oxide film 14 is formed on the wall of the trench 111 by thermal oxidation to relieve stress of the trench 111, and then, by APCVD (atmosphere pressure chemical vapor deposition) method. A thick oxide film 15 is deposited at about 8,000 to 10,500 kPa and heat treated to increase the density of the oxide film 15. At this time, due to the step by the trench 111, the oxide film 15 of the upper portion of the trench 111 forms a recessed side toward the trench 111.
다음, 도 8에 도시한 바와 같이 CMP 공정을 실시하여 산화막(15)의 표면이 질화막(13)과 거의 같아질 때까지 산화막(15)을 연마한다. 이때, 질화막(13)과 산화막(15)에 대해 높은 선택비를 가지는 연마제(slurry)를 사용하는데, 이러한 연마제의 성분은 다음과 같다. 연마 입자는 SiO2, Al2O3및 Ce2O3중 하나 이상으로 이루어지며 이들의 평균 입경은 200 nm 이하이다. 여기에 수화(hydration) 반응을 위한 KOH와 OH-이온 농도 유지를 위한 H2O2, 그리고 초순수(deionized water) 등을 포함하는 것이 기존의 연마제인데, 본 실시예에서는 산화막의 연마 제거율을 높이기 위한 희석된 HF(DHF : diluted HF)를 더 첨가한다. 기존 연마제로는 SiO2, KOH, H2O2및 초순수를 포함하는 Cavot사의 제품 SS11이 있는데 예를 들면 SS11 84.7 내지 86.7 wt%에 DHF를 13.3 내지 15.3 wt% 혼합하여 사용할 수 있다. DHF는 H2O와 49% HF의 혼합 비율이 100:1인 것을 사용한다.Next, as illustrated in FIG. 8, the oxide film 15 is polished until the surface of the oxide film 15 is substantially the same as the nitride film 13 by performing a CMP process. In this case, an abrasive having a high selectivity with respect to the nitride film 13 and the oxide film 15 is used, and the components of the abrasive are as follows. The abrasive particles consist of at least one of SiO 2 , Al 2 O 3 and Ce 2 O 3 , and their average particle diameter is 200 nm or less. The conventional abrasives include KOH for the hydration reaction, H 2 O 2 for maintaining the concentration of OH − ions, and deionized water. In this embodiment, the polishing rate of the oxide film is increased. Add diluted HF (DHF: diluted HF). Conventional abrasives include SS11 manufactured by Cavot, Inc., which includes SiO 2 , KOH, H 2 O 2 and ultrapure water. For example, 13.11 to 15.3 wt% of DHF may be mixed with 84.7 to 86.7 wt% of SS11. DHF uses a mixture having a mixing ratio of H 2 O and 49% HF of 100: 1.
이와 같이 HF를 첨가하면 산화막(15)의 제거 속도가 빨라지므로, 산화막(15)의 밀도가 위치에 따라 달라 밀도가 낮은 지역이 먼저 연마되어 하부의 질화막(13)이 드러나더라도, 밀도가 높은 지역의 산화막(15)이 연마되어 그 하부의질화막(13)이 드러날 때까지 먼저 드러난 질화막(13)은 거의 연마되지 않는다. 따라서, 밀도가 달라 연마 후 활성 영역이 손상을 입는 것을 방지할 수 있다.As the HF is added, the removal rate of the oxide film 15 is increased. Therefore, even if the density of the oxide film 15 varies depending on the location, a region having a low density is polished first, and the lower nitride film 13 is exposed. The nitride film 13 exposed first is hardly polished until the oxide film 15 is polished to expose the lower nitride film 13. Therefore, since the density is different, it is possible to prevent the active region from being damaged after polishing.
다음, 도 9에 도시한 바와 같이 질화막(13)을 제거한다.Next, the nitride film 13 is removed as shown in FIG.
한편, 본 발명에서는 한 번의 사진 식각 공정으로만 트렌치를 형성하므로 공정수가 감소된다.Meanwhile, in the present invention, since the trench is formed by only one photo etching process, the number of processes is reduced.
본 발명에서는 질화막과 산화막의 연마 속도 선택비를 높여 산화막의 밀도가 위치에 따라 다르더라도 최종 연마는 균일한 위치에서 끝나므로 활성 영역이 거의 손상되지 않으면서, 불순물 입자의 생성을 방지할 수 있다. 또한, 공정수가 감소되어 비용을 줄일 수 있다.In the present invention, even if the density of the oxide film varies depending on the position by increasing the polishing rate selection ratio of the nitride film and the oxide film, the final polishing is finished at a uniform position, and thus the generation of impurity particles can be prevented without damaging the active region. In addition, the number of processes can be reduced to reduce costs.
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| JPH02109332A (en) * | 1988-10-19 | 1990-04-23 | Canon Inc | Manufacture of semiconductor substrate |
| US5801082A (en) * | 1997-08-18 | 1998-09-01 | Vanguard International Semiconductor Corporation | Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits |
| JPH11121607A (en) * | 1997-10-14 | 1999-04-30 | Nec Corp | Manufacture of semiconductor device |
| US5976951A (en) * | 1998-06-30 | 1999-11-02 | United Microelectronics Corp. | Method for preventing oxide recess formation in a shallow trench isolation |
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| JPH02109332A (en) * | 1988-10-19 | 1990-04-23 | Canon Inc | Manufacture of semiconductor substrate |
| US5801082A (en) * | 1997-08-18 | 1998-09-01 | Vanguard International Semiconductor Corporation | Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits |
| JPH11121607A (en) * | 1997-10-14 | 1999-04-30 | Nec Corp | Manufacture of semiconductor device |
| US5976951A (en) * | 1998-06-30 | 1999-11-02 | United Microelectronics Corp. | Method for preventing oxide recess formation in a shallow trench isolation |
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