KR100781871B1 - Method of forming field oxide of semiconductor device - Google Patents

Method of forming field oxide of semiconductor device Download PDF

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KR100781871B1
KR100781871B1 KR1020010039026A KR20010039026A KR100781871B1 KR 100781871 B1 KR100781871 B1 KR 100781871B1 KR 1020010039026 A KR1020010039026 A KR 1020010039026A KR 20010039026 A KR20010039026 A KR 20010039026A KR 100781871 B1 KR100781871 B1 KR 100781871B1
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gap
device isolation
forming
film
region
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KR20030002252A (en
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노용주
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

본 발명은 반도체 소자의 소자 격리막 형성시 과도한 연마량을 감소시켜 디싱이 없는 소자 격리막을 형성하는 방법에 관한 것으로, 셀 영역 및 주변 영역의 활성 영역 상부의 갭-필 산화막만을 식각하여 소자 격리막 형성 영역의 갭-필 산화막 두께와 비슷하게 함으로써, 연마량을 감소시키고 균일도가 향상된다.The present invention relates to a method of forming a device isolation layer without dishing by reducing excessive polishing amount when forming a device isolation layer of a semiconductor device, and etching only a gap-fill oxide layer over the active region of a cell region and a peripheral region to form an element isolation layer formation region. By making it close to the gap-fill oxide film thickness of, the polishing amount is reduced and the uniformity is improved.

Description

반도체 소자 격리막 형성 방법{METHOD OF FORMING FIELD OXIDE OF SEMICONDUCTOR DEVICE}Method for forming semiconductor device isolation layer {METHOD OF FORMING FIELD OXIDE OF SEMICONDUCTOR DEVICE}

도 1a 내지 도 1d는 종래의 소자 격리막 형성 방법을 설명하기 위한 단면도들.1A to 1D are cross-sectional views illustrating a conventional method of forming a device isolation film.

도 2a 내지 도 2e는 본 발명에 따른 소자 격리막 형성 방법에 의해 제조된 반도체 소자를 도시한 단면도들.2A to 2E are cross-sectional views showing semiconductor devices manufactured by the device isolation film forming method according to the present invention.

[도면의 주요부분에 대한 부호의 설명][Explanation of symbols on the main parts of the drawings]

1, 10 : 반도체 기판 2, 20 : 패드 산화막1, 10: semiconductor substrate 2, 20: pad oxide film

3, 30 : 패드 질화막 4, 40 : 트렌치3, 30: pad nitride film 4, 40: trench

5, 50 : 갭-필 산화막 6, 70 : 소자 격리막
60 : 마스크 패턴5, 50: gap-fill oxide film 6, 70: device isolation film
60: mask pattern

본 발명은 반도체 소자의 소자 격리막 형성 방법에 관한 것으로, 소자 격리막 형성시 과도한 연마량을 감소시켜 디싱이 없는 소자 격리막을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation layer of a semiconductor device, and to a method for forming an isolation layer without dishing by reducing an excessive polishing amount when forming a device isolation layer.

도 1a 내지 도 1d는 종래의 소자 격리막 형성 방법을 설명하기 위한 단면도이다.
도 1a 내지 도 1d를 참조하면, 반도체 기판(1)의 상부에 패드 산화막(2), 패드 질화막(3)을 순차적으로 형성한다. 소자 격리막을 형성하고자 하는 영역 상부의 패드 질화막(3), 패드 산화막(2) 전체 및 상기 소자 격리막을 형성하고자 하는 영역의 반도체 기판(1)을 소정 깊이까지 식각하여 트렌치(4)를 형성한다. 그 다음에 반도체 기판(1)의 전면에 일정한 두께의 갭-필 산화막(5)을 형성한 후 패드 질화막(3)이 노출되도록 갭-필 산화막(5)을 연마하여 소자 격리막(6)을 형성한다.1A to 1D are cross-sectional views illustrating a conventional method of forming a device isolation film.
1A to 1D, a pad oxide film 2 and a pad nitride film 3 are sequentially formed on the semiconductor substrate 1. The trench 4 is formed by etching the pad nitride film 3 over the region where the device isolation film is to be formed, the entire pad oxide film 2, and the semiconductor substrate 1 in the region where the device isolation film is to be formed to a predetermined depth. After that, a gap-fill oxide film 5 having a constant thickness is formed on the entire surface of the semiconductor substrate 1, and then the gap-fill oxide film 5 is polished to expose the pad nitride film 3 to form the device isolation film 6. do.

종래의 소자 격리막 형성 방법은 트렌치 깊이가 매우 깊은 경우 증착하는 갭-필 산화막의 두께가 커지게 되어 연마량이 증가하여 연마 후의 균일도가 저하되며, 디싱이 발생하고 연마 시간 증가로 인한 소모재 사용량이 증가하여 공정 단가가 상승한다는 문제점이 있었다.In the conventional device isolation layer formation method, when the depth of the trench is very deep, the thickness of the gap-fill oxide film to be deposited is increased to increase the amount of polishing, resulting in a decrease in the uniformity after polishing. As a result, there was a problem that the process cost increases.

본 발명은 상기 문제점을 해결하기 위해 셀 영역 및 주변 영역의 활성 영역 상부의 갭-필 산화막만을 식각하여 소자 격리막 형성 영역의 갭-필 산화막 두께와 비슷하게 함으로써, 연마량을 감소시키고 균일도가 향상된 반도체 소자 격리막 형성 방법을 제공하는데 그 목적이 있다.In order to solve the above problem, the semiconductor device can reduce the amount of polishing and improve the uniformity by etching only the gap-fill oxide film on the active region of the cell region and the peripheral region so as to be similar to the gap-fill oxide thickness of the device isolation region. It is an object of the present invention to provide a method for forming a separator.

본 발명에 따른 반도체 소자 격리막 형성 방법은 반도체 기판의 상부에 패드 산화막, 패드 질화막을 순차적으로 형성하는 단계와, 소자 격리막을 형성하고자 하는 영역 상부의 상기 패드 질화막, 패드 산화막 전체 및 상기 소자 격리막을 형성하고자 하는 영역의 반도체 기판을 소정 깊이까지 식각하여 트렌치를 형성하는 단계와, 상기 반도체 기판 전면에 일정한 두께의 갭-필 산화막을 형성하는 단계와, 상기 소자 격리막을 형성하고자 하는 영역 상부에 마스크 패턴을 형성하는 단계와, 상기 마스크 패턴을 식각 마스크로 상기 소자 격리막을 형성하고자 하는 영역을 제외한 영역의 상기 갭-필 산화막을 식각하되, 하측의 갭-필 산화막이 남도록 플루오르계의 식각제를 이용하여 건식 식각으로 수행하는 단계와, 상기 마스크 패턴을 제거하는 단계 및 상기 패드 질화막이 노출되도록 상기 갭-필 산화막을 연마하는 단계를 포함하는 것을 특징으로 한다.The method of forming a semiconductor device isolation film according to the present invention comprises the steps of sequentially forming a pad oxide film and a pad nitride film on an upper portion of a semiconductor substrate, and forming the pad nitride film, the entire pad oxide film, and the device isolation film over the region where the device isolation film is to be formed. Forming a trench by etching a semiconductor substrate in a desired region to a predetermined depth, forming a gap-fill oxide film having a predetermined thickness on the entire surface of the semiconductor substrate, and forming a mask pattern on the region where the device isolation layer is to be formed. Forming the mask pattern using the mask pattern as an etch mask, and etching the gap-fill oxide film in a region other than the region in which the device isolation layer is to be formed, using a fluorine-based etchant to leave a gap-fill oxide film at a lower side thereof. Performing etching, removing the mask pattern, and removing the mask pattern. Characterized in that it comprises the step of grinding the field oxide film, said gap such that the pad nitride layer is exposed.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 2a 내지 도 2e는 본 발명에 따른 소자 격리막 형성 방법에 의해 제조된 반도체 소자를 도시한 단면도이다.
도 2a 내지 도 2e를 참조하면, 반도체 기판(10)의 상부에 패드 산화막(20), 패드 질화막(30)을 순차적으로 형성한다. 패드 질화막(30)은 그 두께가 200 내지 2500Å인 것이 바람직하다. 2A to 2E are cross-sectional views showing semiconductor devices manufactured by the device isolation film forming method according to the present invention.
2A to 2E, the pad oxide film 20 and the pad nitride film 30 are sequentially formed on the semiconductor substrate 10. It is preferable that the thickness of the pad nitride film 30 is 200-2500 kPa.

삭제delete

소자 격리막을 형성하고자 하는 영역 상부의 패드 질화막(30), 패드 산화막(20) 및 상기 소자 격리막을 형성하고자 하는 영역의 반도체 기판(10)을 소정 깊이까지 식각하여 트렌치(40)를 형성한다. 트렌치(40)는 그 깊이가 5000 내지 25000Å인 것이 바람직하다.The trench 40 is formed by etching the pad nitride layer 30, the pad oxide layer 20, and the semiconductor substrate 10 in the region where the device isolation layer is to be formed to a predetermined depth. The trench 40 preferably has a depth of 5000 to 25000 mm 3.

그 다음에 반도체 기판(10)의 전면에 일정한 두께의 갭-필 산화막(50)을 형성한다. 갭-필 산화막(50)은 그 두께가 3000 내지 30000Å인 것이 바람직하다.
다음에는 소자 격리막을 형성하고자 하는 영역 상부에 마스크 패턴(60)을 형성하고, 마스크 패턴(60)을 식각 마스크로 소자 격리막을 형성하고자 하는 영역인 트렌치(40)를 제외한 영역의 갭-필 산화막(50)을 선택적으로 식각한다. 갭-필 산화막(50)은 HF 등의 플루오르계의 식각제를 이용하여 건식 식각하는 것이 바람직하며, 식각 깊이는 3000 내지 25000Å인 것이 바람직하다.
그 다음, 패드 질화막(30)이 노출되도록 갭-필 산화막(50)을 연마하여 소자 격리막(70)을 형성한다. 갭-필 산화막(50)의 연마 공정은 50 내지 300㎚ 크기의 실리카, 알루미나 연마제가 첨가된 pH8 내지 11인 슬러리를 이용하여 수행하는 것이 바람직하다.Then, a gap-fill oxide film 50 having a predetermined thickness is formed on the entire surface of the semiconductor substrate 10. The gap-fill oxide film 50 preferably has a thickness of 3000 to 30000 kPa.
Next, the mask pattern 60 is formed on the region where the device isolation layer is to be formed, and the gap-fill oxide film of the region other than the trench 40 which is the region where the device isolation layer is to be formed using the mask pattern 60 as an etch mask ( Selectively etch 50). The gap-fill oxide film 50 is preferably dry etched using a fluorine-based etchant such as HF, and the etching depth is preferably 3000 to 25000 kPa.
Then, the gap-fill oxide film 50 is polished to expose the pad nitride film 30 to form the device isolation film 70. The polishing process of the gap-fill oxide film 50 is preferably performed using a slurry having a pH of 8 to 11 to which silica and alumina abrasives of 50 to 300 nm size are added.

본 발명에 의한 반도체 소자 격리막 형성 방법은 셀 영역 및 주변 영역의 활성 영역만을 식각하여 갭-필 산화막의 두께를 소자 격리막 형성 영역의 갭-필 산화막 두께와 비슷하게 함으로써, 연마량을 감소시키고 균일도가 향상시키는 효과가 있다.In the method of forming a semiconductor device isolation layer according to the present invention, the thickness of the gap-fill oxide film is etched by etching only active regions of the cell region and the peripheral region, thereby reducing the amount of polishing and improving the uniformity. It is effective to let.

Claims (7)

반도체 소자의 소자 격리막을 형성하는 소자 격리막 형성 방법에 있어서,In the device isolation film forming method of forming a device isolation film of a semiconductor device, 반도체 기판의 상부에 패드 산화막, 패드 질화막을 순차적으로 형성하는 단계;Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate; 상기 소자 격리막을 형성하고자 하는 영역 상부의 상기 패드 질화막, 패드 산화막 전체 및 상기 소자 격리막을 형성하고자 하는 영역의 반도체 기판을 소정 깊이까지 식각하여 트렌치를 형성하는 단계;Forming a trench by etching the pad nitride layer, the entire pad oxide layer, and the semiconductor substrate in the region where the device isolation layer is to be formed to a predetermined depth, over the region where the device isolation layer is to be formed; 상기 반도체 기판 전면에 일정한 두께의 갭-필 산화막을 형성하는 단계;Forming a gap-fill oxide film having a predetermined thickness on an entire surface of the semiconductor substrate; 상기 소자 격리막을 형성하고자 하는 영역 상부에 마스크 패턴을 형성하는 단계;Forming a mask pattern over a region where the device isolation layer is to be formed; 상기 마스크 패턴을 식각 마스크로 상기 소자 격리막을 형성하고자 하는 영역을 제외한 영역의 상기 갭-필 산화막을 식각하되, 하측의 갭-필 산화막이 남도록 플루오르계의 식각제를 이용하여 건식 식각으로 수행하는 단계;Etching the gap-fill oxide layer except for the region where the device isolation layer is to be formed using the mask pattern as an etch mask, and performing dry etching using a fluorine-based etchant so that a lower gap-fill oxide layer remains. ; 상기 마스크 패턴을 제거하는 단계; 및 Removing the mask pattern; And 상기 패드 질화막이 노출되도록 상기 갭-필 산화막을 연마하는 단계Polishing the gap-fill oxide layer to expose the pad nitride layer 를 포함하는 것을 특징으로 하는 반도체 소자 격리막 형성 방법.Method for forming a semiconductor device isolation film comprising a. 제 1 항에 있어서,The method of claim 1, 상기 패드 질화막은 그 두께가 200 내지 2500Å인 것을 특징으로 하는 반도체 소자 격리막 형성 방법.And the pad nitride film has a thickness of 200 to 2500 mW. 제 1 항에 있어서,The method of claim 1, 상기 트렌치는 그 깊이가 5000 내지 25000Å인 것을 특징으로 하는 반도체 소자 격리막 형성 방법.And said trench has a depth of 5000 to 25000 microns. 제 1 항에 있어서,The method of claim 1, 상기 갭-필 산화막은 그 두께가 3000 내지 30000Å인 것을 특징으로 하는 반도체 소자 격리막 형성 방법.And the gap-fill oxide film has a thickness of 3000 to 30000 GPa. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 갭-필 산화막을 선택적으로 식각하는 단계는 그 식각 깊이가 3000 내지 25000Å인 것을 특징으로 하는 반도체 소자 격리막 형성 방법.And selectively etching the gap-fill oxide film has an etching depth of 3000 to 25000 kPa. 제 1 항에 있어서,The method of claim 1, 상기 패드 질화막이 노출되도록 상기 갭-필 산화막을 연마하는 단계는 50 내지 300㎚ 크기의 실리카, 알루미나 연마제가 첨가된 pH8 내지 11인 슬러리를 이용하여 수행되는 것을 특징으로 하는 반도체 소자 격리막 형성 방법.And polishing the gap-fill oxide film so that the pad nitride film is exposed, using a slurry having a pH of 8 to 11 to which silica and alumina abrasive having a size of 50 to 300 nm are added.
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KR19980060884A (en) * 1996-12-31 1998-10-07 김영환 Device isolation insulating film formation method of semiconductor device
KR19990048259A (en) * 1997-12-09 1999-07-05 구본준 Device isolation method of semiconductor device
KR20000044882A (en) * 1998-12-30 2000-07-15 김영환 Method for forming shallow trench isolation film of semiconductor device

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KR19980060884A (en) * 1996-12-31 1998-10-07 김영환 Device isolation insulating film formation method of semiconductor device
KR19990048259A (en) * 1997-12-09 1999-07-05 구본준 Device isolation method of semiconductor device
KR20000044882A (en) * 1998-12-30 2000-07-15 김영환 Method for forming shallow trench isolation film of semiconductor device

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