KR20070114465A - Chemical mechanical poshing method in a semiconductor device using a ceria based slurry - Google Patents

Abstract

A CMP(Chemical Mechanical Polishing) method of a semiconductor device by using a ceria based slurry is provided to simplify a total process by improving a polishing speed and preventing a dishing effect. A hard mask pattern is formed on an upper surface of a semiconductor substrate(100) having an active region. A polysilicon layer is formed to fill a gap between hard mask patterns. A first CMP process for the polysilicon layer is performed to expose the hard mask patterns by using a ceria based slurry of first PH density. A second CMP process for the residual polysilicon layer and the hard mask patterns is performed by using a ceria based slurry of second PH density. The first PH density is larger than the second PH density.

Description

CMP method of semiconductor device using ceria-based slurry {Chemical mechanical poshing method in a semiconductor device using a ceria based slurry}

1 is a graph showing the results of CMP of respective films using a ceria base slurry under the same conditions.

2 to 5 are cross-sectional views of respective processes for describing the CMP method of the semiconductor device according to the embodiment of the present invention.

The present invention relates to a chemical mechanical polishing (CMP) method of a semiconductor device, and more particularly to a CMP method using a ceria-based slurry.

In general, the CMP process is a method of planarizing the material layer, for example, mainly used to fill the material into a predetermined opening. The CMP process requires an abrasive for polishing the material layer, and a ceria based slurry is generally used as such an abrasive. In the semiconductor manufacturing process, deionized water and diluted ceria base slurry are used in the CMP process. Is provided. Such diluted ceria base slurries have the advantage of preventing dishing, and are mainly used to form landing plugs in contact with the source / drain regions.

However, as shown in FIG. 1, the diluted ceria base slurry has a considerably lower removal amount of the polysilicon film constituting the landing plug as compared to a general oxide slurry. That is, according to the graph of FIG. 1, when the polysilicon film was CMP by using the diluted ceria-based slurry and the oxide slurry, the difference was about 10 times or more.

Conventionally, CMP is first performed using an oxidized slurry, and then second plug CMP is used to insulate the landing plugs. However, when the CMP process is performed in two steps as described above, two slurries must be used in one CMP equipment, and thus, the process is cumbersome.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a CMP method of a semiconductor device capable of preventing a dishing phenomenon and improving a removal rate while using one slurry.

In order to achieve the above technical problem, the present invention forms a hard mask pattern on a semiconductor substrate having an active region, and then forms a polysilicon film so as to fill between the hard mask patterns. The polysilicon film is first CMP to expose the hard mask pattern with a ceria base slurry having a first PH concentration, and then the residual polysilicon film and the hard mask pattern are second with a predetermined thickness to a ceria base having a second PH concentration. CMP. The first PH concentration is preferably greater than the second PH concentration.

It is preferable that the said 1st PH concentration is 9-11, and it is preferable that the said 2nd PH concentration is 3-7.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 to 5 are cross-sectional views of respective processes for describing the CMP method of the semiconductor device according to the embodiment of the present invention.

Referring to FIG. 2, gate electrodes 110 are formed on the semiconductor substrate 100 in a known manner. A gate insulating film (not shown) is formed on the bottom surface of the gate electrode 110 to insulate the semiconductor substrate 100. In addition, a hard mask layer 120 is formed on the top and side surfaces of the gate electrode 110. The hard mask film 120 is then provided to form a self-aligned landing pad, and may be formed of, for example, a silicon nitride film. Next, the interpoly oxide layer 130 is formed to sufficiently fill the gap between the gate electrodes 110. In this case, a process of forming a source / drain region (not shown) on both sides of the gate electrode 110 between forming the hard mask layer 120 and forming the inter poly oxide layer 130. Can be done.

Referring to FIG. 3, the interpoly oxide layer 130 is etched to expose an active region, that is, a region including the gate electrode 110 and a source / drain region therebetween. A plug conductive layer, for example, a doped polysilicon layer 140 is deposited on the inter poly oxide layer 130 to fill the gate electrode 110.

Referring to FIG. 4, a first CMP is performed on the doped polysilicon layer 140 and the inter poly oxide layer 130 until the surface of the hard mask layer 120 is exposed. The primary CMP is carried out using a ceria-based slurry diluted PH of about 9 to 11.

At this time, when the PH concentration of the ceria-based slurry is increased, the polishing rate, that is, the removal rate of the polysilicon film is increased. Specifically, in the CMP of silicon (Si, polysilicon), the Si-Si bond is preferentially polarized and then hydrolyzed. At this time, the positively polarized Si reacts with OH- to form Si-OH, and the negatively polarized Si reacts with water (H2O) to form Si-H. The Si-OH bond and the Ce-OH bond thus formed form a Ce-O-Si bond, and finally, the silicon oxide film (SiO ₂ ) is removed by Si-O-Si cleaving. By increasing the PH of the diluted ceria base slurry by this principle, the polishing rate of polysilicon is increased. Therefore, the polysilicon film can be removed at a high speed without using an oxidizing slurry. The PH concentration of the ceria based slurry can be achieved by the addition of a chemical agent to the slurry. In addition, a stop point of the first CMP through which the hard mask layer 120 is exposed may be determined by a motor current end point detector (EPD) or an optical EPD. Here, reference numeral 142 denotes a polysilicon film primarily polished.

As shown in FIG. 5, the polysilicon film 142 polished to expose the hard mask film 120 is secondarily CMPed to form the landing plug 145. At this time, the second CMP process is precisely performed by using a ceria base slurry adjusted to a pH of about 3 to 7 so that the dipping phenomenon of the landing plug 145 and the loss of the interpoly oxide film 130 do not occur. . As such, the ceria-based slurry having a low PH concentration has a low polishing rate, but can precisely proceed with CMP without the occurrence of dipping. In addition, since most of the polysilicon film is removed by the first CMP, the polysilicon film of the thin film may be etched in the second CMP step, so that even using a ceria-based slurry having a low PH concentration does not significantly affect the polishing rate.

Thus, by using the same ceria base slurry which differs in PH concentration, the polishing efficiency can be greatly improved. In the present embodiment, the landing plug has been described as an example, but it can be applied to all processes using the CMP process.

As described in detail above, according to the present invention, in the method of CMPing a polysilicon film, the polysilicon film is primarily CMP using a ceria base slurry having a relatively high PH concentration, and then a relatively low PH concentration is obtained. Secondary CMP is carried out with the ceria-based slurry having.

Accordingly, dicing phenomenon can be prevented while improving the polishing rate (removal efficiency) using one kind of ceria base slurry. This can simplify the process.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (5)

Forming a hard mask pattern on a semiconductor substrate having an active region; Forming a polysilicon layer to fill the hard mask pattern; Primary CMP of the polysilicon film to expose the hard mask pattern with a ceria base slurry having a first PH concentration; And Performing a second CMP on the residual polysilicon layer and the hard mask pattern by a predetermined thickness with a ceria base having a second PH concentration, Wherein the first PH concentration is greater than the second PH concentration. The method of claim 1, The first PH concentration is 9 to 11 CMP method of a semiconductor device. The method of claim 1, The second PH concentration is 3 to 7 CMP method of the semiconductor device. The method of claim 1, A CMP method of a semiconductor device in which a gate electrode is further formed in the hard mask pattern. The method of claim 1, Between the step of forming the hard mask pattern and the step of forming the polysilicon film, Forming an oxide layer to fill the hard mask pattern; And And etching the oxide layer to expose the active region.

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