JP5116229B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having a trench type element isolation structure.

  Conventionally, an insulating film (hereinafter also referred to as “element isolation film”) for electrically isolating elements from each other in a semiconductor device is a silicon oxide film by HDP-CVD (High Density Plasma Chemical Vapor Deposition) method. It is manufactured by embedding. In this manufacturing method, first, a silicon oxide film and a silicon nitride film are sequentially deposited on a silicon substrate. Thereafter, a groove is formed in a predetermined region by a lithographic method and a dry etching method, and a silicon oxide film is embedded using an HDP-CVD method. At this time, if a fine groove having an aspect ratio exceeding 5.0 is present, a void is generated in the silicon oxide film buried by the HDP-CVD method. Thereafter, the surface of the silicon oxide film is planarized by a CMP (Chemical Mechanical Polishing) method using the silicon nitride film as a stopper film. Thereafter, the silicon nitride film and the silicon oxide film are sequentially removed by wet etching.

  Next, the substrate surface is oxidized by a thermal oxidation method to form a silicon oxide film as a screen film (sacrificial oxide film) for ion implantation, and the well implantation or transistor threshold value is determined by the ion implantation method. For the injection. Thereafter, the silicon oxide film as the screen film is removed again by a wet etching method to form a gate oxide film having a predetermined thickness. While performing wet etching as described above, the gap in the silicon oxide film appears as a fine opening on the surface, and the gate electrode material is buried in the groove formed by the gap and remains unremoved during etching. It causes micro short circuit. As described above, since the filling method by CVD is a method of sequentially depositing films, voids are likely to be generated.

In recent years, instead of the CVD method, SOD (Spin-On Dielectric), that is, a method of filling a separation groove with a coating film has been proposed. In the SOD method, a film using polysilazane (SiH ₂ NH) _n as a material is embedded as an element isolation film of a semiconductor device. FIG. 4 is a process diagram for forming an element isolation film by the SOD method. In this method, first, a silicon oxide film 43 and a silicon nitride film 44 are sequentially deposited on a silicon substrate 41 as shown in FIG. Thereafter, a groove is formed in a predetermined region by a lithographic method and a dry etching method. Subsequently, spin coating is performed using a solution in which polysilazane is dissolved in dibutyl ether, and dibutyl ether as a solvent is removed by baking at several hundred degrees Celsius, and the polysilazane film 46 is embedded in the separation groove. At this time, since the separation groove is embedded by application of fluid, no void is generated in principle. On the other hand, since the chemical bond in polysilazane at this point is weak, it is fragile as an insulating film and is in an unstable state. If left untreated, the following hydrolysis reaction occurs, and a portion of the silicon oxide film is gradually added. To change. Further, this film has a weak bonding force as an oxide film and contains a large amount of impurities such as ammonia.
SiH ₂ NH + 2H ₂ O → SiO ₂ + NH ₃ + 2H ₂
Therefore, heat treatment in a water vapor atmosphere diffuses the oxidizing agent (water vapor) into the film, forcibly proceeds with the hydrolysis reaction, changes the polysilazane film to a silicon oxide film, and fires it to a more stable film. To do. FIG. 4A is a cross-sectional view at the stage where this process is completed. The polysilazane film 46 is thin, and the portion oxidized into the silicon oxide film 47 by baking is expressed darkly. As shown in FIG. 4 (a), the degree of firing varies depending on the pattern, and the hydrolysis reaction does not proceed as deeply as seen from the surface of the film. In general, the diffusion of the oxidizing agent (water vapor) proceeds with time. Due to the profile of the polysilazane film after coating, the oxidant (water vapor) does not reach the fine separation groove pattern far from the surface and the hydrolysis reaction does not proceed. There is a difference. On the other hand, if baking is continued for a long time, the polysilazane in the fine separation groove far from the surface can also be fired. For this reason, firing is often performed for a long time. In this case, the oxidizing agent reaches the Si substrate surface in the separation groove having a large opening, and the oxidation reaction of silicon proceeds on the element isolation side wall and the separation bottom surface. Therefore, since the shape change due to the oxidative expansion causes a large stress in the substrate and deteriorates the device characteristics, it is not preferable to advance the baking process to a predetermined amount or more.

  Next, the surface of the silicon oxide film 47 is planarized by CMP using the silicon nitride film 44 as a stopper film. FIG. 4B is a cross-sectional view at the stage where this process is completed. Thereafter, the silicon nitride film 44 is removed by a wet etching method using hot phosphoric acid, and the silicon oxide film 43 is sequentially removed by a wet etching method using diluted hydrofluoric acid. FIG. 4C is a cross-sectional view at the stage where this process is completed. Since the etching rate of the polysilazane film is faster than the etching rate of the silicon oxide film by dilute hydrofluoric acid, the change to the silicon oxide film hardly occurs. The finer the groove pattern, the faster the upper surface is etched.

  Next, the substrate surface is oxidized by a thermal oxidation method to form a silicon oxide film (not shown) as a screen film (sacrificial oxide film) for ion implantation, and well implantation or ion implantation is performed. Implantation for determining the threshold value of the transistor is performed, and the silicon oxide film which is the screen film is removed again by wet etching using diluted hydrofluoric acid. At this time, since the polysilazane film having a low degree of firing is etched faster, the finer separation groove pattern has its upper surface retreated more greatly. Thereafter, a gate oxide film having a predetermined thickness is formed, and then a gate electrode 48 is formed. FIG. 4D is a cross-sectional view at the stage where this process is completed, and as described above, the finer separation groove pattern has its upper surface receding to form a large depression. FIG. 5A shows a plan view at this stage. In FIG. 5A, FIG. 4D is a cross-sectional view when the gate electrode 58 is cut by IVD-IVD. 5A, a cross-sectional view taken along VB-VB is FIG. 5B, and a cross-sectional view taken along VC-VC is FIG. 5C. As shown in FIG. 5B, the gate electrode material 59 is buried in the recess and remains unremoved at the time of etching, causing a micro short between the adjacent gate electrodes 58a and 58b, and at the end of the active region, the silicon substrate. The corners of the gate electrode are exposed, thinning of the gate oxide film occurs, reliability decreases, or gate electric field concentration (fringe) occurs, and the threshold value is likely to decrease.

On the other hand, there is a method in which baking is performed after CMP (see Patent Document 1). However, the spin coat layer before firing is an unstable film, and since polysilazane containing a large amount of Si—N bonds instead of Si—O bonds is directly polished by CMP, silica (SiO ₂ ) or ceria (CeO ₂ ) is polished. ) Is a non-qualified slurry for silicon oxide film and is difficult to flatten. Actually, when these slurries are used for polishing a polysilazane film, the rate is remarkably fast due to weak bonding, but the rate decreases at a place containing a lot of Si-N bonds. It is uniform. Even if a film containing SiN bonds is polished with a slurry that makes it easy to polish, it is difficult to stop polishing using a silicon nitride film used as a mask layer for element isolation formation as a stopper film. The film thickness cannot be made uniform.
JP 2004-179614 A

  An object of the present invention is to provide a method for manufacturing a semiconductor device in which an insulating film embedded on a substrate has no gap, has a small pattern dependency of firing, and has a small pattern dependency of the shape and thickness of the insulating film.

  The present invention relates to a method for manufacturing a semiconductor device in which an insulating film for electrically separating elements from each other is formed on a semiconductor substrate, the step of forming a mask layer on the semiconductor substrate, and patterning the mask layer A step of forming first and second groove portions having different groove widths on the substrate using the patterned mask layer, a step of forming a silicon insulating film on the substrate by a coating method, and a silicon insulating film A first baking step of baking a part of the silicon oxide film into a silicon oxide film, a planarization step of removing and flattening the silicon oxide film outside the mask layer by CMP, and a second baking of the silicon insulating film The method includes a firing step and a step of forming a gate electrode.

  When the element isolation film is formed by the manufacturing method of the present invention, no gap is generated in the element isolation film, so that the gate electrode material is taken in and does not cause a micro short circuit. In addition, since the pattern dependency of the shape and thickness of the element isolation film is small, the pattern dependency of element characteristics can be reduced.

  A mask layer made of silicon nitride or the like is formed on the semiconductor substrate, the mask layer is patterned, and then the first groove portion and the second groove portion having different groove widths are formed on the substrate using the mask layer. Next, a silicon insulating film is formed on the substrate by a coating method, and a part of the silicon insulating film is modified into a silicon oxide film by the first baking step, and then the silicon oxide film outside the mask layer is formed. Then, the silicon insulating film is baked into a silicon oxide film by a second baking step, and then a gate electrode having a predetermined thickness is formed. Since an insulating film is embedded on the substrate by a coating method, a fine element isolation film free from voids can be formed in principle.

  The application of the silicon insulating material to the substrate is preferably a spin coating method in that a uniform silicon insulating film can be easily obtained. In addition to the thermal oxidation method, a method such as a radical oxidation method can be used for firing, but the method using water vapor or the like as an oxidation species can be expected to progress oxidation by a hydrolysis reaction even at a relatively low temperature. Is preferable.

  Generally, when a spin-coated insulating film is baked and then flattened by CMP, the influence of the pattern is reflected on the baking degree. On the other hand, if baking is performed after planarization by CMP, the spin coat film before baking is an unstable film that dissolves easily in the cleaning liquid after polishing, and the polishing rate is fast, so flattening by CMP is difficult. is there. In the present invention, by performing baking both before and after CMP, it is possible to achieve both highly flat polishing using a silicon nitride film as a stopper film and uniform baking with little variation between patterns. Regardless of this, it is possible to form a microelement isolation film that is substantially uniform, has no depressions, and has a substantially constant shape and film thickness.

  The first groove portion has a larger groove width than the second groove portion, and in the first firing step, in the first groove portion, which is largely opened, oxidizing species such as water vapor diffuses in the silicon insulating film to the bottom portion of the groove. A mode in which the calcination is performed is preferable. In this case, the degree of firing is different depending on the pattern, but since most of the portion to be removed in the next polishing process by CMP is completely changed to the silicon oxide film, the polishing rate is changed regardless of the pattern. It can be kept constant, and the finished film thickness of the silicon insulating film can be made uniform. In addition, in the second firing step, the unfired insulating film is changed almost completely into a dense silicon oxide film, including the fine separation portion, and becomes a stable isolation insulating film.

In the first baking step, baking is performed so that the oxidizing species do not diffuse into the mask layer, and in the next planarization step, polishing is performed using a slurry having a high selection ratio of the silicon oxide film to the silicon insulating film containing nitrogen. This embodiment is preferable. In this case, after the first baking, the oxidizing species has progressed partway through the coating film. Subsequently, as a slurry having a high selection ratio of the silicon oxide film to the silicon insulating film made of polysilazane or the like, for example, ceria (CeO _When the ceria slurry using ₂ ) as a raw material is polished by the CMP method, the polishing rate is lowered in a portion where the degree of firing is low and hydrolysis has not progressed, and the polishing can be stopped in a flattened state. Polishing with ceria slurry has a very high selection ratio of the silicon oxide film to the silicon nitride film, so that very high smoothness can be obtained by polishing using the silicon nitride film as a stopper film. Thereafter, almost all of the unsintered insulating film is changed into a dense and stable silicon oxide film including the fine separation portion in the second firing step.

  Compared to the first groove portion that opens largely, in the second groove portion that opens small, the diffusion of the oxidized species tends to be slow, and the firing tends not to proceed. Accordingly, there is no difference between the patterns in the final baking level, and almost all of the layers including the fine separation portion are dense and stable, so that a small opening is formed in the second baking step. In the groove portion, it is preferable to perform firing in a state where the oxidized species diffuses in the silicon insulating film to the bottom portion of the groove.

As shown in FIG. 7, the silicon insulating film 76 formed by the coating method has a flat portion B at a position lower than the flat portions A and C on the mask layer 74 in the opening region I of the first groove portion having a large opening. Have. When the depth from the upper surface of the mask layer (silicon nitride film 74) to the bottom of the groove is d, the first groove having a large opening varies depending on the thickness of the silicon insulating film 76. _In many cases, ₁ is about twice or more the depth d.

On the other hand, the silicon insulating film 76 has a hole D having a curved surface at the deepest portion in the opening region II. However, in the opening region III, the opening width is the same as the opening width W ₃ of the second groove portion having a small opening. When the size is further reduced, the hole portion is eventually not recognized, and the flat portion E having the same height as the flat portions A and C on the mask layer 74 is provided. The second grooves may differ depending on the thickness of the silicon insulating film 76, usually, often the width W ₂ is less than about 2 times the depth d, for example, the minimum fine separation unit in a semiconductor chip, etc. Is applicable.

  A mode in which the silicon oxide film is wet-etched with a mixed solution of ammonia solution and hydrofluoric acid solution (buffered hydrofluoric acid solution) after the second baking step is preferable. By providing such an etching step, even if a difference in the degree of baking occurs, the difference in etching rate between the coating film after baking and the silicon oxide film formed by thermal oxidation becomes small, and the coating film Since the relative etching rate is lowered, a difference between patterns hardly occurs in the shape after etching.

  Therefore, according to the present invention, it is possible to avoid the trouble that the gate electrode material is buried in the recess and remains without being removed during the etching, and a micro short circuit occurs. Furthermore, the element isolation film is largely retracted, the corner of the silicon substrate is exposed at the edge of the active region, and thinning of the gate oxide film occurs, leading to a decrease in reliability and concentration of the gate electric field (fringe). )) And problems such as lowering the threshold can be avoided.

Example 1
A method for manufacturing a semiconductor device of the present invention will be described with reference to FIG. First, a silicon oxide film having a thickness of 5 to 20 nm is formed on a silicon substrate by a thermal oxidation method, and then a silicon nitride film is deposited to a thickness of 50 to 200 nm by a LP-CVD (Low Pressure Chemical Vapor Deposition) method. Form. Next, after patterning a mask layer made of a silicon nitride film and a silicon oxide film by lithography and dry etching, the silicon substrate is dug down to a depth of 200 to 400 nm using this mask layer, and FIG. As shown, a silicon oxide film 3 and a silicon nitride film 4 are provided on a silicon substrate 1 and a groove is formed in a predetermined region where an element isolation film is to be formed.

Thereafter, in order to remove the etching damage layer, it is preferable to oxidize the side wall and the bottom surface of the groove by thermal oxidation for 5 to 20 nm and to cover the silicon substrate with a high-quality silicon oxide film (not shown). Next, a solution in which polysilazane is dissolved in dibutyl ether is applied by spin coating, baking is performed at 100 to 200 ° C. for about 1 to 5 minutes, the solvent dibutyl ether is removed, and the polysilazane film 6 is formed as an insulating film. Embedded in the separation groove. Since this operation is an operation of embedding the separation groove by applying a fluid, a void is not generated in principle. FIG. 1A is a cross-sectional view at the stage where this process is completed. At this time, the chemical bond in the polysilazane is weak, so that the insulating film is fragile and unstable. For this reason, heat treatment is performed in a water vapor atmosphere to cause the next hydrolysis reaction to change into a silicon oxide film.
SiH ₂ NH + 2H ₂ O → SiO ₂ + NH ₃ + 2H ₂
At this time, first, heat treatment is performed in a water vapor atmosphere at 400 to 600 ° C., but firing is performed in a state where water vapor as an oxidizing agent diffuses in the insulating film to the bottom of the groove. FIG. 2 illustrates the firing state of the polysilazane film 26 when a silicon oxide film 23 and a silicon nitride film 24 are formed on the silicon substrate 21, and then a polysilazane film 26 is spin-coated and then heat-treated. The initial state of the heat treatment is shown in FIG. 2A, the intermediate state is shown in FIG. 2B, and the late state is shown in FIG. 2C. Region 20 in FIG. 2 represents a region having an oxidant concentration sufficient to allow the hydrolysis reaction to proceed. In this embodiment, the oxidizing agent is diffused rather than the state of FIG. 2B, and the heat treatment is performed to a state close to FIG. By such a heat treatment, the oxidant diffuses to such an extent that the groove portion having a large opening just reaches the silicon substrate surface, and in the other regions, it reaches the vicinity of the surface of the silicon nitride film 24. The conditions such as the heat treatment time are adjusted so that the oxidant diffuses into the surface. For example, the treatment is performed at a temperature of 500 to 600 ° C. for 10 to 30 minutes.

  Thereafter, the hydrolysis reaction is advanced by performing a heat treatment at a high temperature of 600 ° C. or higher, for example, at 900 to 1100 ° C. for 30 to 90 minutes in an inert gas atmosphere such as nitrogen. Further, excess oxidant and generated ammonia are diffused out of the system to be removed from the film, and finally, as shown in FIG. 1B, in most regions other than the fine separation region, the polysilazane film 6 changes to a dense silicon oxide film 7 and becomes a stable film. In FIG. 1B, a polysilazane film that has not been completely baked is expressed in a light color, and a portion that has changed to a silicon oxide film by baking is expressed in a dark color. As described above, the degree of baking varies depending on the pattern, but most of the portion to be removed in the next polishing process by CMP is completely changed to the silicon oxide film 7.

Next, using the silicon nitride film 4 as a stopper film, the silicon oxide film 7 outside the mask layer is removed by CMP to flatten the surface of the substrate. At this time, in order to obtain a high selection ratio with respect to the silicon nitride film 4, it is desirable to polish using a ceria (CeO ₂ ) slurry. However, the polishing rate is low for a polysilazane film having a low degree of firing and containing a large amount of nitrogen. In order to decrease, it is preferable to use silica slurry so that the polishing rate does not decrease. FIG. 1C is a cross-sectional view at the stage where this process is completed. At this time, a part of the polysilazane film having a low degree of firing and an incomplete hydrolysis reaction is exposed on the surface of the fine separation portion.

  Subsequently, it is again baked in a water vapor atmosphere to be hydrolyzed, and the fine separation portion is also almost completely changed into a silicon oxide film. Also at this time, first, heat treatment is performed in a water vapor atmosphere at 400 to 600 ° C., and in order to cause the diffusion of the oxidant to occur in the range of about the film thickness of the coating film or less, for example, at a temperature of 500 to 600 ° C. For about 10-30 minutes. Thereafter, heat treatment is performed at a high temperature of 600 ° C. or higher, for example, at 900 to 1100 ° C. for 30 to 90 minutes in an inert gas atmosphere such as nitrogen, and the hydrolysis reaction is allowed to proceed completely. The ammonia is diffused out of the system and removed from the film. Thereby, finally, almost all of the polysilazane film 6 including the fine separation portion is changed into the dense silicon oxide film 7, and becomes a stable isolation insulating film. FIG. 1D is a cross-sectional view at the stage where this process is completed.

  Next, the silicon nitride film 4 is removed by a wet etching method using hot phosphoric acid, and the silicon oxide film 3 is sequentially removed by a wet etching method using diluted hydrofluoric acid. Thereafter, the substrate surface is baked by a thermal oxidation method to form a silicon oxide film (not shown) as a screen film (sacrificial oxide film) for ion implantation. Next, well implantation or implantation for determining the threshold value of the transistor is performed by ion implantation, and the silicon oxide film as a screen film is removed again by wet etching using diluted hydrofluoric acid. In the wet etching so far, the etching rate is almost uniform regardless of the pattern, so the separation film thickness is almost uniform in all patterns including the fine separation groove pattern, and the shape of the end is almost independent of the pattern. Equal element isolation films can be formed. Thereafter, a gate oxide film having a predetermined thickness is formed, and then a gate electrode 8 is formed. FIG. 1E is a cross-sectional view at the stage where this process is completed.

  FIG. 6A shows a plan view at this stage. In FIG. 6A, FIG. 1E is a cross-sectional view when the gate electrode 68 is cut by IE-IE. 6A, a cross-sectional view taken along VIB-VIB is FIG. 6B, and a cross-sectional view taken along VIC-VIC is FIG. 6C. Unlike the case shown in FIG. 5B, in FIG. 6B, there is no depression in the fine separation region, and the gate electrode material is not buried in the depression, so that no micro short circuit occurs between the gate electrodes 68a and 68b.

  In the wet etching process of silicon oxide film, if a buffered hydrofluoric acid solution in which ammonia solution and hydrofluoric acid solution are mixed is used as the etching solution instead of dilute hydrofluoric acid, it is formed by thermal oxidation with the polysilazane film after firing. The difference in etching rate with the silicon oxide film is reduced. Therefore, since the etching rate of the polysilazane film is relatively lowered, even if there is a slight difference in the degree of firing, it is difficult for the difference in pattern between the patterns to occur after etching.

  As described above, the amount of recession on the upper surface of the silicon oxide film 7 due to wet etching is substantially uniform regardless of the pattern, so that a large depression does not occur in a fine separation groove pattern. For this reason, a decrease in reliability due to thinning of the gate oxide film and a decrease in threshold value of the transistor due to concentration (fringe) of the gate electric field are unlikely to occur.

Example 2
A method for manufacturing a semiconductor device of the present invention will be described with reference to FIG. The steps up to FIG. 3A are the same as those in the first embodiment. After forming a mask layer made of the silicon oxide film 33 and the silicon nitride film 34 on the silicon substrate 31, a groove is formed. Further, as in the first embodiment, heat treatment is performed in a water vapor atmosphere to cause the following hydrolysis reaction to change the polysilazane film 36 into a silicon oxide film.
SiH ₂ NH + 2H ₂ O → SiO ₂ + NH ₃ + 2H ₂
The heat treatment is first performed in a water vapor atmosphere at 400 to 600 ° C., but the oxidation is performed only in a range where the diffusion of the oxidizing agent is smaller than the film thickness of the coating film, that is, as shown in FIG. Spread the agent. Therefore, on the active region, conditions such as the heat treatment time are adjusted so that the oxidizing agent does not reach the silicon nitride film 24 as well. As the heat treatment conditions, for example, the temperature is 400 to 500 ° C. and 5 to 10 minutes. Thereafter, the hydrolysis reaction is allowed to proceed by heat treatment at a high temperature of 600 ° C. or higher, for example, 900 to 1100 ° C. for 30 to 90 minutes in an inert gas atmosphere such as nitrogen, and the excess oxidant and the generated ammonia are converted into a system. It is diffused outside and removed from the film. FIG. 3B is a cross-sectional view at the stage where this process is completed. The polysilazane film 36 that has not been baked is expressed in white color, and the portion that has changed to a silicon oxide film by baking is expressed in dark color. In this way, the firing is in the middle of the film, and a large amount of nitrogen remains in the unchanged part of the polysilazane film.

Next, the silicon oxide film outside the mask layer is removed by CMP using a slurry made of ceria (CeO ₂ ) having a high selection ratio of the silicon oxide film to the silicon nitride film, and the surface of the substrate is removed. Flatten. At this time, when the surface of the polysilazane film containing a large amount of nitrogen having a low degree of baking and not undergoing hydrolysis reaction is exposed, the polishing rate is lowered and the polishing is stopped in a flattened state. FIG. 3C is a cross-sectional view at the stage where this process is completed.

  Subsequently, heat treatment is performed again in a water vapor atmosphere to cause hydrolysis, and almost all the portions are completely changed into the silicon oxide film 37. For example, after treatment at a temperature of 500 to 600 ° C. for 10 to 30 minutes, heat treatment is performed at 900 to 1100 ° C. for 30 to 90 minutes in an inert gas atmosphere such as nitrogen to completely complete the hydrolysis reaction. Make it progress. Thereby, finally, almost all of the polysilazane film 36 including the fine separation portion is changed to the dense silicon oxide film 37, and becomes a stable insulating film. FIG. 3D is a cross-sectional view at the stage where this process is completed. Thereafter, the silicon oxide film above the silicon nitride film 34 is removed by CMP using a slurry made of ceria as a raw material again.

  Polishing with ceria slurry has a very high selectivity of the silicon oxide film to the silicon nitride film, and very high flatness can be obtained by polishing using the silicon nitride film as a stopper. On the other hand, in a polysilazane film having a low degree of firing, the polishing rate decreases. Therefore, by performing the second firing, there is no polishing residue and very flat polishing can be performed.

  Next, the silicon nitride film 34 is removed by a wet etching method using hot phosphoric acid, and the silicon oxide film 33 is sequentially removed by a wet etching method using diluted hydrofluoric acid. Thereafter, the substrate surface is baked by a thermal oxidation method to form a silicon oxide film (not shown) as a screen film (sacrificial oxide film) for ion implantation, and well implantation or transistor by ion implantation. After the implantation for determining the threshold value, the silicon oxide film as the screen film is removed again by wet etching using diluted hydrofluoric acid. In the wet etching so far, the etching rate is uniform regardless of the pattern, so the separation film thickness is uniform in all patterns including the fine separation groove pattern, and the element isolation is the same regardless of the shape of the edge. A film can be formed. Thereafter, a gate oxide film having a predetermined thickness is formed, and then a gate electrode 38 is formed. FIG. 3E is a cross-sectional view at the stage where this process is completed.

  In the process of wet etching of silicon oxide film, instead of dilute hydrofluoric acid, a buffered hydrofluoric acid solution, which is a mixture of ammonia solution and hydrofluoric acid solution, is used as the etching solution. The difference in etching rate with the silicon oxide film formed is reduced. Therefore, since the etching rate of the polysilazane film is relatively lowered, even if there is a slight difference in the degree of firing, a difference in pattern after etching hardly occurs between patterns. As described above, the amount of recession of the upper surface of the silicon oxide film 37 in the wet etching is almost uniform regardless of the pattern, so that a large depression is not generated in a fine separation groove pattern. Therefore, it is difficult to cause a reduction in reliability due to thinning of the gate oxide film and a reduction in threshold value of the transistor due to concentration (fringe) of the gate electric field. Furthermore, since the firing range in the uneven state is made smaller than in Example 1, the substrate is excessively oxidized in the two firings, the element isolation film expands, and stress is generated. It is possible to prevent the characteristics from deteriorating.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the present invention, since an element isolation film having a very narrow groove width can be formed, it is possible to widely manufacture a fine semiconductor device that is drawn mainly with a rule that the line width of a circuit is 100 nm or less.

It is process drawing which shows the manufacturing method of the semiconductor device of this invention. It is a schematic diagram which shows the baking state of a polysilazane film | membrane. It is process drawing which shows the manufacturing method of the semiconductor device of this invention. It is process drawing which forms an element isolation film by the conventional SOD method. It is a figure which shows the conventional semiconductor device in which the gate electrode was formed. It is a figure which shows the semiconductor device of this invention in which the gate electrode was formed. It is a schematic diagram which shows the formation state of the silicon insulating film in this invention.

Explanation of symbols

  1 silicon substrate, 3, 7 silicon oxide film, 4 silicon nitride film, 6 polysilazane film, 8 gate electrode.

Claims (6)

A method of manufacturing a semiconductor device, wherein an insulating film for electrically separating elements from each other is formed on a semiconductor substrate,
Forming a mask layer on the semiconductor substrate;
Patterning the mask layer;
Forming a first groove and a second groove having different groove widths on the substrate using the patterned mask layer;
Forming a silicon insulating film on the substrate by a coating method;
A first baking step of baking a part of the silicon insulating film into a silicon oxide film;
A planarization step of planarizing by removing the silicon oxide film outside the mask layer by a CMP method;
A second baking step of baking the silicon insulating film;
Forming a gate electrode,
The second groove portion has a groove width smaller than that of the first groove portion,
In the second baking step, baking is performed in the second groove portion in a state where the oxidized species diffuses in the silicon insulating film to the bottom portion of the groove ,
The second firing step, a method of manufacturing a semiconductor device comprising a heating step in a steam atmosphere, and a heating process in an inert gas atmosphere to chromatic in this order.   The first groove portion has a larger groove width than the second groove portion, and in the first baking step, in the first groove portion, the oxidized species diffuses in the silicon insulating film to the bottom of the groove. The method for manufacturing a semiconductor device according to claim 1, wherein baking is performed at a temperature.   3. The semiconductor device according to claim 2, wherein the silicon insulating film formed by the coating method has a flat portion at a position lower than the flat portion on the mask layer in the opening region of the first groove portion. Manufacturing method.   In the first baking step, baking is performed so that the oxidizing species do not diffuse into the mask layer, and in the planarization step, polishing is performed using a slurry having a high selection ratio of the silicon oxide film to the silicon insulating film. The method of manufacturing a semiconductor device according to claim 1, wherein:   The said silicon insulating film formed by the said coating method has a flat part in substantially the same height as the flat part on the said mask layer in the opening area | region of a 2nd groove part. A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of wet etching the silicon oxide film with a mixed solution of an ammonia solution and a hydrofluoric acid solution after the second baking step.

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