KR20080061515A - Method of fabricating the trench isolation layer for semiconductor device - Google Patents

Abstract

A method of forming an isolation layer of a semiconductor device is provided to cure an upper and a lower part of a trench uniformly by performing a curing process after flattening a PSZ film although the trench having a large aspect ratio is buried with the PSZ film. A trench is formed on a semiconductor substrate(102). The trench is gap-filled with an insulation layer by forming an insulation layer(118) above the semiconductor substrate. The insulation layer remains in the trench only by flattening the insulation layer. An isolation layer is formed by performing the curing process to the insulation layer.

Description

Method of fabricating the trench isolation layer for semiconductor device

1A to 1F are cross-sectional views of a device illustrated to explain a method of forming a device isolation film of a semiconductor device according to a preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

102 semiconductor substrate 104 gate insulating film

106: insulating film for floating gate 108: buffer oxide film

110: nitride film 112: hard mask

114: trench 116: liner oxide film

118: insulating film

The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device capable of forming a device isolation film by applying a shallow trench isolation (STI) process to a separation region of a substrate.

In general, a semiconductor device formed on a silicon wafer includes a device isolation region for electrically separating each semiconductor device. In particular, as semiconductor devices have been highly integrated and miniaturized, research into not only the size of each individual device but also the device isolation region has been actively conducted. The reason for this is that the formation of the device isolation region is an initial step in all the manufacturing steps, and depends on the size of the active area and the process margin of the post-process step.

In the device isolation region, a field oxide film is formed by a conventional method such as Local Oxidation of Silicon (LOCOS) or Profiled Grove Isolation (PGI), thereby defining an active region. Among them, in the LOCOS method, a nitride film, which is an anti-oxidation mask defining an active region, is formed on a semiconductor substrate, patterned to expose a predetermined portion of the semiconductor substrate, and then the exposed semiconductor substrate is oxidized to isolate the device. A field oxide film used as a region is formed. The LOCOS method has the advantage of a simple process and the ability to separate large and narrow portions at the same time. However, a bird's beak is formed by lateral oxidation, so that the width of the device isolation region is widened. reduce the effective area of the drain region. In addition, when the field oxide film is formed, stress is concentrated at the edges of the oxide film due to the difference in thermal expansion coefficient, so that a crystal defect occurs in the silicon substrate and thus a leakage current is increased. In addition, as the degree of integration of semiconductor devices has recently increased, design rules have decreased, and thus the size of device isolation layers separating semiconductor devices from semiconductor devices has also been reduced by the same scale, so that device separation methods such as LOCOS are applied. This limit has been reached.

The STI (Shallow Trench Isolation) method applied to solve this problem is as follows. First, a nitride film having a different etching selectivity from the semiconductor substrate is formed on the semiconductor substrate, and the nitride film is patterned to form the nitride film in order to use the nitride film as a hard mask. In the etching process using the nitride film pattern as a hard mask, the semiconductor substrate is etched to a predetermined depth to form a trench, and then an insulating film, for example, a high density plasma (HDP) oxide film or an O ₃ − A gap fill is performed with a TEOS oxide film or the like. Subsequently, chemical mechanical polishing (CMP) is performed to form a device isolation layer filling the trench.

However, in the technology below 80nm, the aspect ratio of the trench increases as the process technology becomes finer, and voids are generated even when a complicated process such as DED (deposition-etch-deposition) is performed due to the limitation of the HDP oxide film. There is a problem in that the productivity of the HDP oxide film is reduced even if it does not occur or voids occur. In addition, in the case of filling the trench using the O ₃ -TEOS oxide film, it is possible to improve the sidewall step coverage by increasing the initial O ₃ concentration, but it is difficult to control the seam. In addition, in the recent trend of device development such as a recess gate, trenches should be formed vertically or preferably have a negative slope, and the HDP oxide film and the O ₃ -TEOS oxide film may be formed. In the trench structure, void generation cannot be suppressed.

The present invention can easily gap fill a trench having a high aspect ratio by using a PSZ film, and a curing process is performed by forming a PSZ film, performing a planarization process, and then curing a lower portion of the PSZ film formed in a trench having a high aspect ratio. Can be.

According to a method of forming a device isolation film of a semiconductor device according to a preferred embodiment of the present invention, providing a semiconductor substrate having a trench formed therein, forming an insulating film on the semiconductor substrate and gap filling the trench with an insulating film; And forming an isolation layer by performing a planarization process on the upper portion of the insulating film to leave the insulating layer only in the trench and performing a curing process on the insulating layer.

The method may further include performing a heat treatment process on the insulating layer before performing the planarization process. For the heat treatment process, a first heat treatment process is performed at a first temperature, a second heat treatment process is performed at a second temperature higher than the first temperature, and a third heat treatment process at a third temperature higher than the second temperature. Can be carried out. The first temperature may be a temperature of 50 to 150 ℃, the second temperature is a temperature of 150 to 250 ℃, the third temperature may be a temperature of 250 to 400 ℃.

The curing process may be performed by a wet oxidation process. In the curing process, H ₂ gas and O ₂ gas may be used as 1: 2. The curing process may be carried out at a temperature of 300 to 600 ℃ and a pressure of 200 to 500 torr (torr).

The insulating layer may be formed of PSZ. The insulating layer may be formed to a thickness of 4000 to 6000 kPa while the semiconductor substrate is rotated at a speed of 1000 to 2000 rpm. The method may further include reducing the height of the device isolation layer after the curing process.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A to 1F are cross-sectional views of a device illustrated to explain a method of forming a device isolation film of a semiconductor device according to a preferred embodiment of the present invention.

Referring to FIG. 1A, a gate insulating film 104, a floating gate insulating film 106, a buffer oxide film 108, a nitride film 110, and a hard mask 112 are formed on a semiconductor substrate 102 on which a device isolation region is defined. Form. Preferably, the gate insulating film 104 is formed of an oxide film and may serve as a tunnel oxide film in a NAND flash memory device. Preferably, the floating gate insulating film 106 may be formed of polysilicon.

Referring to FIG. 1B, a photoresist pattern (not shown) is formed on the hard mask 112. The photoresist pattern is formed on the hard mask 112 corresponding to the active region so that the device isolation region is opened. The hard mask 112, the nitride film 110, the buffer oxide film 108, the floating gate conductive film 106 and the gate insulating film 104 are patterned by an etching process using a photoresist pattern, and then the semiconductor substrate 102 is subsequently patterned. A portion of) is etched to form trench 114.

Referring to FIG. 1C, a liner oxide layer 116 is formed on the entire structure of the semiconductor substrate 102 including the trench 114. The liner oxide 116 is intended to facilitate gap fill of the trench 114 in subsequent processes. Next, an insulating film 118 is formed over the entire structure of the semiconductor substrate 102 to gap fill the trench 114. The insulating film 118 is preferably formed by spin coating using PSZ (Poly Silazane). To this end, the insulating film 118 may be formed to a thickness of 4000 to 6000 kPa by supplying a liquid PSZ to the upper portion of the semiconductor substrate 102 in a state in which the semiconductor substrate 102 is rotated at a speed of 1000 to 2000 rpm.

Subsequently, a heat treatment process may be performed on the insulating film 118 to increase the density of the insulating film 118 and to discharge the impurity gas included in the insulating film 118 to improve the film quality of the insulating film 118. In the heat treatment process, after performing the first heat treatment process at a temperature of 50 to 150 ° C. for 10 minutes to 30 minutes, the second heat treatment process is performed at a temperature of 150 to 250 ° C. and a third heat treatment process at a temperature of 250 to 400 ° C. Can be completed.

Referring to FIG. 1D, a planarization process such as a chemical mechanical polishing (CMP) process is performed on the upper portion of the insulating layer 118 to planarize the upper portion of the insulating layer 118. In this case, the nitride film 110 serves as an etch stop film to expose the nitride film 110 formed under the hard mask 112. The hard mask 112 (see FIG. 1C) may be removed together with the upper portion of the insulating layer 118.

Subsequently, a curing process is performed on the insulating film 118. In the curing process, oxygen and other elements other than silicon in the insulating film 118 are replaced with oxygen to form silicon oxide, whereby the density of the insulating film 118 is further increased and the impurity gas contained in the insulating film 118 is further removed. 118) can be improved. For this purpose, the curing process is preferably carried out by a wet oxidation process using H ₂ gas and O ₂ gas at a temperature of 300 to 600 ° C. and a pressure of 200 to 500 torr (1: 2).

In the prior art, a curing process for the PSZ film was performed immediately after the trench was filled with the PSZ film. However, when the aspect ratio of the trench is large, the surface of the PSZ film is preferentially cured so that the PSZ film under the trench may not be cured. In this case, the lower portion of the trench may not be cured and may be formed as a porous film due to remaining hydrogen. In addition, the difference in volume during the curing process is severe, causing stress differences due to thermal expansion and cracks may occur. In the present invention, however, the trench is filled with a PSZ film and then the planarization process is performed to remove the upper PSZ film, thereby reducing the thickness of the cured PSZ film. Thereafter, the PSZ film may be easily cured by performing a curing process on the PSZ film.

Referring to FIG. 1E, the nitride film 110 is removed. The nitride film 110 may be removed by wet etching using phosphoric acid as an etching solution for 10 to 30 minutes.

Referring to FIG. 1F, portions of the insulating layer 118 and the liner oxide layer 116 are removed to adjust the effective fox height (EFH). To this end, wet etching may be performed for 3 to 5 minutes using an etchant mixed with H 2 O and HF in a ratio of 100: 1.

According to the method of forming a device isolation film of a semiconductor device of the present invention, even if a trench having a high aspect ratio is buried using a PSZ film, a flattening process is performed on the PSZ film and then a curing process is performed to uniformly cure the upper and lower portions of the trench. Can be.

Claims (10)

Providing a trench with a formed semiconductor substrate; Forming an insulating film on the semiconductor substrate to gap fill the trench with an insulating film; Performing a planarization process on an upper portion of the insulating film to leave the insulating film only in the trench; And And forming a device isolation film by performing a curing process on the insulating film. The method of claim 1, And performing a heat treatment process on the insulating film before performing the planarization process. The method of claim 2, For the heat treatment process, a first heat treatment process is performed at a first temperature, a second heat treatment process is performed at a second temperature higher than the first temperature, and a third heat treatment process at a third temperature higher than the second temperature. A device isolation film forming method of a semiconductor device. The method of claim 3, The first temperature is a temperature of 50 to 150 ℃, the second temperature is a temperature of 150 to 250 ℃, the third temperature is a device isolation film forming method of a semiconductor device. The method of claim 1, And the curing step is performed by a wet oxidation process. The method of claim 5, The curing process is a device isolation film forming method of a semiconductor device using H ₂ gas and O ₂ gas 1: 2. The method of claim 6, The curing process is a device isolation film forming method of a semiconductor device performed at a temperature of 300 to 600 ℃ and a pressure of 200 to 500 torr (torr). The method of claim 1, And the insulating film is PSZ. The method of claim 8, And the insulating film is formed to a thickness of 4000 to 6000 kPa while the semiconductor substrate is rotated at a speed of 1000 to 2000 rpm. The method of claim 1, And lowering the height of the device isolation layer after the curing process.

Images