JP2007234880A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for reducing variations in the width of an STI (shallow trench isolation) step when an element isolation layer formed by STI method is polished together with a stopper nitride film. <P>SOLUTION: A method of manufacturing a semiconductor device comprises a step of forming a pad oxide film on a semiconductor substrate having an element formation region and an element isolation region set therein; a step of forming a stopper nitride film on the pad oxide film; a step of forming a resist mask covering the surface of the stopper nitride film in a region other than the element isolation region; a step of forming a separation groove by etching the stopper nitride film, the pad oxide film, and the semiconductor substrate with use of the resist mask as a mask; a step of forming the silicon oxide film into the stopper oxide film and the separation groove by removing the resist mask; a first polishing step of exposing the stopper nitride film by polishing the silicon oxide film using a cerium-oxide-based slurry; and a second polishing step of forming an element isolation layer, by polishing the exposed stopper nitride film and the silicon oxide film on the separation groove using a potassium-hydroxide-based slurry. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device in which an element isolation layer is formed by an STI (Shallow Trench Isolation) method.

In a conventional method for manufacturing a semiconductor device, when an element isolation layer is formed by the STI method, a pad oxide film made of silicon oxide (SiO ₂ ) and silicon nitride (SiN) are formed on a semiconductor substrate made of silicon (Si). A stopper nitride film, etc., are sequentially laminated, and a resist mask is formed by exposing the element isolation region by photolithography. Using this as a mask, the stopper nitride film, pad oxide film, etc. and the semiconductor substrate are etched to form isolation grooves. Then, after removing the resist mask, a silicon oxide film made of silicon oxide is formed on the stopper nitride film in the element formation region and in the isolation groove by a CVD (Chemical Vapor Deposition) method, and then by a ceria-based slurry using cerium oxide (CeO ₂ ) CPM (Chemical Mechanical l Polishing) to flatten the silicon oxide film, then further polish the silicon oxide film with diluted ceria-based slurry to expose the stopper nitride film, and remove the stopper nitride film etc. by wet etching to separate An element isolation layer in which silicon oxide is buried in the groove is formed, and the STI step T between the semiconductor wafers (the step from the upper surface of the element isolation layer after removing the stopper nitride film and the pad oxide film from the upper surface of the semiconductor substrate. (Refer to Patent Document 1, for example).
JP-A-2005-175110 (9th page, paragraph 0048-10th page, paragraph 0058, FIGS. 2 to 4)

  However, in the conventional technique described above, the silicon nitride film for forming the element isolation layer is polished with a ceria-based slurry to expose the stopper nitride film. Therefore, in the actual manufacturing process, the stopper nitride film is not formed. The silicon oxide film may remain due to flatness or the like, and when the silicon oxide film remains, the remaining silicon oxide film in the step of removing the stopper nitride film that selectively etches silicon nitride is used as a mask. Since the stopper nitride film remains, it is necessary to further polish the stopper nitride film so that the silicon oxide film does not actually remain.

The inventor polished the silicon oxide film for forming the element isolation layer by the CMP method using the ceria-based slurry, and further distributed the STI step T of each semiconductor device formed on the semiconductor wafer when the stopper nitride film was polished. Was investigated.
FIG. 11 is a graph showing the distribution of STI steps at the center of the chip of each semiconductor device when the silicon oxide film and the stopper nitride film are polished by ceria-based slurry. FIG. 12 shows the silicon oxide film and stopper nitride film by the ceria-based slurry. FIG. 13 is a graph showing the distribution of the STI step at the outer periphery of each semiconductor device when polished, and FIG. 13 shows the center and outer periphery of the chip in the semiconductor device when the silicon oxide film and the stopper nitride film are polished by a ceria-based slurry. It is a graph which shows distribution of the difference of STI level | step difference with.

The horizontal axis in FIGS. 11 to 13 is a measurement position in which the semiconductor device 2 painted black on the semiconductor wafer 1 shown in FIG. 2 is shown in order from the left side, and the vertical axis is the sixth position located at the center of the semiconductor wafer 1. This is the difference between the STI step T of the semiconductor device 2 (referred to as a reference chip) and the measured STI step T of each semiconductor device 2.
Further, the chip central portion and the chip outer peripheral portion are the positions of the semiconductor device 2 shown in white in order to indicate the portions with reference numerals A and B in FIG.

FIG. 7 shows the film thickness distribution after the formation of the silicon oxide film for forming the element isolation layer of the semiconductor wafer 1 in this investigation. FIG. 7 shows 10 thickness distribution measurements of the silicon oxide film on the dividing line 3 in the vicinity of the semiconductor device 2 along the arrangement direction of the semiconductor device 2 where the STI step T shown in FIG. 2 was measured.
As shown in FIGS. 11 and 12, when the silicon oxide film and the stopper nitride film are polished with a ceria-based slurry, the large unevenness of the silicon oxide film shown in FIG. 7 is flattened by polishing.

  Further, when the polishing amount of the stopper nitride film indicated by the broken line in FIGS. 11 and 12 is small (98 mm (angstrom) in the illustrated example), the variation width of the STI step T at each measurement position of the semiconductor wafer is small. When the polishing amount indicated by the solid line in FIGS. 11 and 12 is large (202 mm in the illustrated example), the variation width of the STI step T increases. This also applies to the variation width of the difference in the STI step T between the chip central portion and the chip outer peripheral portion in the semiconductor device 2 shown in FIG.

That is, when the stopper nitride film is further polished so that the silicon oxide film does not remain, if the ceria-based slurry is polished, the variation width of the STI step T in the semiconductor wafer and the semiconductor device increases.
As described above, when the variation width of the STI step T in the semiconductor wafer and the semiconductor device becomes large, the STI step T is formed by etching when the gate electrode is formed by patterning the polysilicon layer formed on the semiconductor substrate thereafter. Polysilicon remains in an unetched portion where the etching rate is large, resulting in variations in the electrical characteristics of the formed semiconductor element due to the conductivity of the remaining polysilicon, thereby reducing the yield of the manufactured semiconductor device. There is a problem of making it.

Further, if the etching time is lengthened in order to eliminate the etching residue, there is a problem that the manufacturing efficiency of the semiconductor device is lowered.
This is particularly important when forming a semiconductor element having a SAC (Self Align Contact) structure.
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide means for reducing the variation width of the STI step when the element isolation layer formed by the STI method is polished together with the stopper nitride film. And

  In order to solve the above-described problems, the present invention provides a method for manufacturing a semiconductor device in which a pad oxide film is formed on a semiconductor substrate in which an element formation region and an element isolation region are set, and on the pad oxide film, A step of forming a stopper nitride film; a step of forming a resist mask on the stopper nitride film covering a region excluding the element isolation region; and the stopper nitride film, the pad oxide film, and the semiconductor using the resist mask as a mask Etching the substrate to form a separation groove; removing the resist mask; forming a silicon oxide film on the stopper oxide film and the separation groove; and using a ceria-based slurry to form the silicon oxide A first polishing step of polishing the film to expose the stopper nitride film, and using the potassium hydroxide-based slurry, the exposed stopper nitride film and the isolation groove Characterized in that it comprises a second polishing step of forming a silicon oxide film and the element isolation layer is polished and the.

  Thereby, the present invention flattens the unevenness of the upper surface of the silicon oxide film for forming the element isolation layer using the ceria-based slurry in the first polishing step, and then the potassium hydroxide-based slurry in the second polishing step. Thus, the silicon oxide film and the stopper nitride film can be uniformly polished while maintaining the flattened state as it is, and the effect of reducing the variation width of the STI step is obtained.

  Embodiments of a semiconductor device manufacturing method according to the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory view showing a method for manufacturing a semiconductor device of an embodiment, FIG. 2 is an explanatory view showing a measurement position of an STI step of the semiconductor wafer of the embodiment, and FIG. It is explanatory drawing shown.
1 and 2, reference numeral 1 denotes a semiconductor wafer. As shown in FIG. 2, the dividing lines 3 when the semiconductor device 2 is manufactured by dividing the semiconductor wafer 1 into individual pieces are set vertically and horizontally.

In FIG. 1, reference numeral 4 denotes a semiconductor substrate made of single crystal silicon of a semiconductor wafer 1, where an element formation region 5 is formed as a region for forming a semiconductor element, and an element isolation layer 9 described later is provided between adjacent element formation regions 5. An element isolation region 6 is set as a region for formation.
Reference numeral 7 denotes a pad oxide film, which is a thin film (about 150 mm in this embodiment) made of silicon oxide having a relatively thin film thickness formed on the semiconductor substrate 4 by a thermal oxidation method or the like.

Reference numeral 8 denotes a stopper nitride film, which is a thick film (about 1900 mm in this embodiment) made of silicon nitride having a relatively large thickness formed on the pad oxide film 7 by a CVD method or the like. It functions as an index indicating the end of polishing by.
An element isolation layer 9 is a silicon oxide film made of silicon oxide embedded in an isolation trench 10 formed by digging the element isolation region 6 set around the element formation region 5 of the semiconductor substrate 4 by dry etching. 11 is an insulating layer formed by scraping the upper surface side by polishing by a CMP method, which will be described later, and has a function of electrically insulating and separating the adjacent element forming regions 5 of the semiconductor substrate 4.

  In order to solve the problem in the case where the stopper nitride film 8 is further polished by the CMP method using the ceria-based slurry, the inventor performs the polishing on the semiconductor wafer 1 when the stopper nitride film 8 and the silicon oxide film 11 are simultaneously polished. When the slurry that does not increase the variation width of the STI step T is studied, and the stopper nitride film 8 and the silicon oxide film 11 are polished at the same time by polishing by a CPM method using a potassium hydroxide-based slurry using potassium hydroxide (KOH). It was found that it is possible to suppress an increase in the variation width of the STI step T.

  FIG. 4 is a graph showing the distribution of the STI step at the center of the chip of each semiconductor device when the silicon oxide film and the stopper nitride film are polished with a potassium hydroxide-based slurry. FIG. FIG. 6 is a graph showing the distribution of STI steps on the outer periphery of the chip of each semiconductor device when the stopper nitride film is polished. FIG. 6 shows the chip in the semiconductor device when the silicon oxide film and the stopper nitride film are polished with a potassium hydroxide-based slurry. FIG. 7 is a graph showing the film thickness distribution after the formation of the silicon oxide film for forming the element isolation layer of the semiconductor wafer.

The horizontal and vertical axes in FIGS. 4 to 6 are the same as those in FIGS. 11 to 13.
Further, the measurement positions of the semiconductor wafer 1 and the semiconductor device 2 where the STI step T is measured are the same as in the above case (see FIGS. 2 and 3).
As shown in FIGS. 4 and 5, when the silicon oxide film 11 is polished with a potassium hydroxide-based slurry and the stopper nitride film 8 is further polished, the large unevenness of the silicon oxide film 11 shown in FIG. However, the variation width of the STI step T in the case where the polishing amount of the stopper nitride film 8 indicated by the broken line in FIGS. 4 and 5 is 240 mm and the polishing amount indicated by the solid line is 410 mm is the polishing amount. Even if it increases, it has not expanded. This also applies to the variation width of the difference in the STI step T between the chip central portion and the chip outer peripheral portion in the semiconductor device 2 shown in FIG.

  That is, if polishing is performed with a potassium hydroxide-based slurry, the silicon oxide film 11 and the stopper nitride film 8 are mixed even when the silicon oxide film 11 and the stopper nitride film 8 formed of different materials are mixed while maintaining the uneven state before polishing. The stopper nitride film 8 can be uniformly polished, and the tendency does not change even if the polishing amount is increased. By using this, the STI step T in the semiconductor wafer 1 and the semiconductor device 2 can be reduced. The knowledge that it was possible to reduce the variation width was obtained.

A method for manufacturing the semiconductor device of this example will be described below in accordance with the process indicated by P in FIG.
A semiconductor substrate 4 in which P1, an element formation region 5 and an element isolation region 6 are set is prepared, a thin pad oxide film 7 is formed on the semiconductor substrate 4 by thermal oxidation, and a CVD method is formed on the pad oxide film 7. Thus, a thick stopper nitride film 8 is formed.

P2, a resist mask covering the region excluding the element isolation region 6, that is, the element formation region 5 is formed on the stopper nitride film 8 by photolithography, and the stopper nitride film 8 and the pad oxide film 7 are formed by dry etching using the resist mask as a mask. Then, the semiconductor substrate 4 is etched to form a separation groove 10 having a depth from the upper surface of the semiconductor substrate 4 of about 4000 mm.
The resist mask formed in P3 and process P2 is removed, a protective oxide film having a thickness of about 300 mm made of silicon oxide is formed on the inner surface of the isolation groove 10 by thermal oxidation, and the stopper nitride film 8 and the isolation are formed by CVD. Silicon oxide is deposited in the trench 10 to form a silicon oxide film 11 having a thickness of about 7000 mm. At this time, the upper surface of the silicon oxide film 11 is in a state where irregularities are formed.

The silicon oxide film 11 is polished by the CMP method using P4, ceria-based slurry, and the stopper nitride film 8 is slightly polished (about 30 mm in this embodiment) to expose the stopper nitride film 8 (first polishing) Process).
At this time, the unevenness on the upper surface of the silicon oxide film 11 formed in the process P3 is flattened.
Next, the exposed stopper nitride film 8 and the silicon oxide film 11 on the isolation trench 10 are polished by CMP using a potassium hydroxide-based slurry to form an element isolation layer 9 (second polishing step). .

The amount of polishing at this time may be in a range where the silicon oxide film 11 remaining on the stopper nitride film 8 can be removed, that is, in the range of 200 to 300 mm, but to the extent that the underlying pad oxide film 7 is not exposed, that is, pad oxidation. It is desirable to polish to such an extent that the stopper nitride film 8 remains on the film 7 with a thickness of 20 to 100 mm.
After polishing with P6, potassium hydroxide-based slurry, the silicon oxide film 11 is cleaned with hydrofluoric acid (HF), and silicon nitride is selectively etched by wet etching with hot phosphoric acid (Hot-H ₂ PO ₄ ). Then, the stopper nitride film is removed, and then the silicon oxide is etched by wet etching with hydrofluoric acid to remove the pad oxide film 7.

During the etching for removing the pad oxide film 7, the upper surface of the element isolation layer 9 is also etched, and the STI step T is formed to have the same height as the thickness of the stopper nitride film 8 left on the pad oxide film 7. Is done.
In this way, the element isolation layer 9 embedded in the isolation trench 10 by the STI method of this embodiment is formed, and the memory element or MOSFET (Metal Oxide Semiconductor Fielder) is formed in the element isolation region 5 insulated and isolated by the element isolation layer 9. The semiconductor device 1 of this embodiment is formed by dividing the semiconductor wafer 1 on which the semiconductor element such as the Effect Transistor) is formed into pieces along the dividing line 3.

The distribution of the STI step T in the semiconductor wafer 1 and the semiconductor device 2 formed as described above is shown in FIGS.
FIG. 8 is a graph showing the distribution of STI steps at the center of the chip of each semiconductor device when the silicon oxide film and the stopper nitride film are polished by the manufacturing method of the embodiment. FIG. FIG. 10 is a graph showing the distribution of STI steps at the outer periphery of the chip of each semiconductor device when the stopper nitride film is polished. FIG. 10 shows the chip in the semiconductor device when the silicon oxide film and the stopper nitride film are polished by the manufacturing method of the embodiment. It is a graph which shows distribution of the difference of the STI level | step difference of a center part and a chip | tip outer peripheral part.

The horizontal and vertical axes in FIGS. 8 to 10 are the same as those in FIGS. 11 to 13.
Further, the measurement positions of the semiconductor wafer 1 and the semiconductor device 2 where the STI step T is measured are the same as in the above case (see FIGS. 2 and 3), and silicon for forming the element isolation layer 9 of the semiconductor wafer 1 is used. The film thickness distribution after the formation of the oxide film 11 is the same as in FIG.
In the manufacturing method of this embodiment, that is, the silicon oxide film 11 is polished with a ceria-based slurry in the first polishing step, and then the silicon oxide film 11 and the stopper nitride film 8 are polished with a potassium hydroxide-based slurry in the second polishing step. In the case of polishing, as shown in FIGS. 8 and 9, even when the stopper nitride film 8 is polished by 200 mm or more, the variation width of the STI step T in the semiconductor wafer 1 is within 100 mm. It can be seen that the variation width is greatly suppressed as compared with the variation width of 200 mm of the STI step T when the stopper nitride film 8 is polished by 200 mm or more with only the ceria-based slurry shown. This also applies to the variation width of the difference in the STI step T between the chip central portion and the chip outer peripheral portion in the semiconductor device 2 shown in FIG.

  That is, in the polishing method of the present embodiment, the unevenness on the upper surface of the silicon oxide film 11 for forming the element isolation layer 9 is first flattened using a ceria-based slurry, and then silicon oxide is oxidized using a potassium hydroxide-based slurry. Since the film 11 and the stopper nitride film 8 are uniformly polished, the silicon oxide film 11 and the stopper nitride film 8 can be polished while maintaining the state flattened with the ceria-based slurry, and the STI step T varies. The width can be reduced.

  The thus obtained semiconductor wafer 1 on which the element isolation layer 9 is formed by the STI method of this embodiment does not leave the silicon oxide film 11 on the stopper nitride film 8 after the element isolation layer 9 is formed. The stopper nitride film 8 in P6 can be easily removed, and the polysilicon formed in the element formation region 5 does not remain due to the etching residue when the gate electrode made of polysilicon is formed thereafter. The electrical characteristics of the element can be stabilized, the yield of the manufactured semiconductor device 2 can be improved, and the manufacturing efficiency of the semiconductor device 2 can be increased without the need for extending the etching time for eliminating the etching residue. .

This is particularly effective when forming a SAC-structured semiconductor element that allows the formation of contact plugs up to the vicinity of the interface between the element formation region 5 and the element isolation region 6.
As described above, in this embodiment, when a device isolation layer is formed by polishing a silicon oxide film formed on an isolation groove and a stopper nitride film formed on a semiconductor substrate, first, a ceria-based slurry is used. The silicon nitride film is polished to expose the stopper nitride film, and then the stopper nitride film and the silicon oxide film on the isolation trench are polished using a potassium hydroxide slurry to form an element isolation layer. The surface of the silicon oxide film for forming the element isolation layer is flattened using a ceria-based slurry, and then maintained flat using a potassium hydroxide-based slurry. The film can be uniformly polished, and the variation width of the STI step T can be reduced.

  In the present embodiment, the semiconductor substrate is described as being a bulk substrate made of single crystal silicon. However, the semiconductor substrate is not limited to the above, and a semiconductor substrate having an SOI (Silicon On Insulator) structure may be used. A semiconductor substrate having a silicon on sapphire structure may be used. In short, any semiconductor substrate capable of forming an element isolation layer by the STI method can achieve the same effects as described above if the present invention is applied.

Explanatory drawing which shows the manufacturing method of the semiconductor device of an Example Explanatory drawing which shows the measurement position of the STI level | step difference of the semiconductor wafer of an Example Explanatory drawing which shows the measurement position of the STI level | step difference of the semiconductor device of an Example The graph which shows distribution of the STI level difference of the chip | tip center part of each semiconductor device at the time of grind | polishing a silicon oxide film and a stopper nitride film with a potassium hydroxide type | system | group slurry. The graph which shows distribution of the STI level | step difference of the chip | tip outer periphery part of each semiconductor device at the time of grind | polishing a silicon oxide film and a stopper nitride film with potassium hydroxide type | system | group slurry. The graph which shows distribution of the difference of the STI level difference of the chip | tip center part and chip | tip outer periphery part in a semiconductor device at the time of grind | polishing a silicon oxide film and a stopper nitride film with potassium hydroxide type | system | group slurry. The graph which shows the film thickness distribution after formation of the silicon oxide film for forming the element isolation layer of a semiconductor wafer The graph which shows distribution of the STI level difference of the chip | tip center part of each semiconductor device at the time of grind | polishing a silicon oxide film and a stopper nitride film with the manufacturing method of an Example The graph which shows distribution of the STI level | step difference of the chip | tip outer peripheral part of each semiconductor device at the time of grind | polishing a silicon oxide film and a stopper nitride film with the manufacturing method of an Example The graph which shows distribution of the difference of the STI level difference of the chip | tip center part in a semiconductor device, and a chip | tip outer periphery part at the time of grind | polishing a silicon oxide film and a stopper nitride film with the manufacturing method of an Example. The graph which shows distribution of STI level difference of the chip center part of each semiconductor device at the time of polishing a silicon oxide film and a stopper nitride film by ceria system slurry The graph which shows distribution of the STI level | step difference of the chip | tip outer peripheral part of each semiconductor device at the time of grind | polishing a silicon oxide film and a stopper nitride film with a ceria-based slurry The graph which shows distribution of the difference of the STI level difference of the chip | tip center part in a semiconductor device and a chip | tip outer periphery at the time of grind | polishing a silicon oxide film and a stopper nitride film with a ceria-based slurry

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor device 3 Dividing line 4 Semiconductor substrate 5 Element formation area 6 Element isolation area 7 Pad oxide film 8 Stopper nitride film 9 Element isolation layer 10 Separation groove 11 Silicon oxide film

Claims (3)

Forming a pad oxide film on a semiconductor substrate in which an element formation region and an element isolation region are set;
Forming a stopper nitride film on the pad oxide film;
Forming a resist mask on the stopper nitride film covering a region excluding the element isolation region;
Etching the stopper nitride film, the pad oxide film, and the semiconductor substrate using the resist mask as a mask to form an isolation groove;
Removing the resist mask and forming a silicon oxide film on the stopper oxide film and in the separation groove;
Using a ceria-based slurry, a first polishing step of polishing the silicon oxide film to expose the stopper nitride film;
A second polishing step of forming an element isolation layer by polishing the exposed stopper nitride film and the silicon oxide film on the isolation groove using a potassium hydroxide-based slurry;
A method for manufacturing a semiconductor device, comprising: In claim 1,
A method of manufacturing a semiconductor device, wherein a polishing amount in the second polishing step is larger than a polishing amount in the first polishing step. In claim 1,
A method of manufacturing a semiconductor device, wherein a polishing amount in the first polishing step is set to 30 angstroms, and a polishing amount in the second polishing step is set in a range of 200 angstroms to 300 angstroms.

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